A BiCMOS technology with 660-MHz vertical p-n-p transistor foranalog/digital ASICs

A fully complementary BiCMOS technology based on a 2-μm process designed for 12-V analog/digital applications is described. In this technology, a triple diffused vertical p-n-p transistor and n-p-n bipolar and CMOS devices are integrated in a single chip. A transition frequency of 660 MHz and a collector-to-emitter breakdown voltage of over 15 V have been obtained for the collector-isolated p-n-p transistor by adding only one extra mask to a conventional 2-μm BiCMOS process. The total number of masks is 20 with double-layer metallization. A unity gain frequency of 52 MHz and a DC gain of 85 dB have been obtained for a single-supply operational amplifier with a vertical p-n-p first stage. The propagation delay time for a CMOS two-NAND gate was 1.27 ns driving three loads and 3 mm of metal     

A novel polysilicon thin-film transistor with a p-n-p structuredgate electrode

We propose and fabricate a novel polycrystalline silicon thin-film transistor (poly-Si TFT) which exhibits the properties of an offset gated structure in the OFF state, while acting as a nonoffset structure in the ON state. The fabrication process is compatible with the conventional nonoffset poly-Si TFT's process and does not require any additional mask. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the nonoffset gated device, while the ON current of the new device is almost identical to the nonoffset gated device. It is observed that the ON/OFF current ratio of the proposed poly-Si TFT is improved remarkably     

Low-noise microwave bipolar transistor with sub-half-micrometer emitter width

This paper presents details of the fabrication process and performance of an n-p-n silicon microwave bipolar transistor with emitter opening widths as small as 0.3 µm. The fabrication process involves local oxidation, ion implantation, and lateral etching techniques for emitter definition. Noise figure as low as 1.0 dB at 1.5 GHz, 2.0 dB at 4 GHz, and 3.3 d B at 6 GHz were achieved. Measured noise figures andS-parameters are shown to be in approximate agreement with modeled performance based on device structure and process parameters. Prospects for further reductions in bipolar transistor noise figures are discussed.     

A heterojunction bipolar transistor with a thin α-Si emitter

In this paper, a modified silicon heterojunction bipolar transistor is proposed and demonstrated. The structure uses a very thin n⁺ amorphous silicon layer as the emitter to enhance the emitter injection efficiency and reduce the emitter resistance as well as improve the frequency response of the device     

Diffused planar InP bipolar transistor with a cadmium oxide film emitter

A novel bipolar InP transistor is demonstrated which comprises a Zn-diffused base and a transparent conductor widegap emitter made of sputtered cadmium oxide. Preliminary current gain was about 10. Owing to its less demanding planar technology the device is assessed to be promising for monolithic integration.     

Analyses of delta-doped emitter bipolar transistor

In this article, the theoretical model of delta-doped emitter bipolar transistor that included the effect of bandgap shrinkage is presented. The recombination in emitter set-back layer is also considered. We also present the calculated results for the current gain as a function of barrier height, barrier width, and emitter set-back layer thickness. The experimental results of the device are also given.     

The post-damage behavior of a MOS tunnel emitter transistor

The effect of oxide damage on the characteristics of an Al/SiO₂/n-Si MOS tunnel emitter transistor, is considered. The pre-breakdown oxide degradation is shown to reduce the current gain and to extend the S-shape segment of the collector characteristic of a device. This kind of damage may be formally modeled as an increase of the SiO₂ thickness deviation. After a soft breakdown, the transistor usually loses its bistability and has much lower gain in the range of large currents, while in the low-current mode the device behavior remains almost unchanged. Essential is the size of the zone affected by a breakdown spot, which is, to a great extent, regulated by the conductivity of an inversion layer.     

A high-performance thin-film transistor with a vertical offsetstructure

In this study, we propose a novel device structure combined with conventional hydrogenated amorphous silicon (a-Si:H) for the source and drain regions and microcrystalline silicon (μc-Si:H) for the channel region to obtain a high-performance thin-film transistor (TFT). This is a vertical a-Si:H offset structure used to suppress OFF-state current to a small value which is comparable to the conventional a-Si:H TFTs with a much higher drivability. The fabrication process is simple, low temperature (⩽300°C), and low cost, with a potential for high reliability     

Measuring the intrinsic-base-region currents of a transistor

An experimental method of cancelling depletion-layer capacitance-current flow to permit exact observations of the current flow into the transistor `intrinsic base region? is described.     

Sequential anneal effect on bipolar transistor with phosphorus-implanted emitter

An n-p-n-type bipolar transistor with an emitter region formed by a new ion implantation predeposition diffusion exhibits much less leakage current compared to that formed by a conventional process. This new emitter region has a thermal history of first anneal at 500°C, second anneal at 900°C, and third anneal at 1050°C after phosphorus implantation predeposition of 1 × 10¹⁶/cm²at 50 keV.     

Current gain of silicon bipolar transistor with polysilicon emitter contact

A two-region analysis is presented to predict the common-emitter current gain of a bipolar transistor with the polysilicon contact to the emitter for a case when the recombinations at the mono-poly interface are not negligible. The calculated current-gain enhancement for typical device parameters and for different values of interface recombination velocity show that the current-gain enhancement and its increase with decrease of emitter width is smaller for the interface with larger recombinations.     

Investigation of boron diffusion in polysilicon and its applicationto the design of p-n-p polysilicon emitter bipolar transistors withshallow emitter junctions

Ion implantation of boron into undoped polysilicon is utilized. The main goals are to characterize the diffusion of implanted boron from polysilicon, and to correlate the diffusion behavior with the electrical properties of shallow (<500 Å) p-n-p polysilicon emitter bipolar transistors. It is shown that diffusion and electrical activity problems are encountered with boron polysilicon emitters which are not present with arsenic. Base current and emitter resistance are measured on shallow p-n-p polysilicon emitter transistors, and it is shown that the use of a deliberately grown interfacial oxide layer can decrease the base current by a factor of 10 and increase the emitter resistance by a factor of around 2. Comparisons with identical n-p-n polysilicon emitter transistors show that the modeled interfacial oxide, tunneling parameters for n-p-n and p-n-p devices are inconsistent     

Sidewall effects in shallow emitter of small bipolar transistor

The current injected into a shallow emitter is studied using a two-dimensional numerical solution of the transport equations, including the effects of bandgap reduction, lifetime and surface recombination velocity. The present results show clearly the correlation between the injected current and the bowl-shaped emitter area as well as the width of metal contact.     

Optimization of transistor structure for transistor-stabilizedfield emitter arrays

Reliability of the metal-oxide-semiconductor field-effect transistor (MOSFET)-stabilized field emitters at high-field operation has been assessed by comparing two different MOSFET structures. Electrical characteristics and behavior of carriers in the device structure have been investigated by means of device simulation. One structure, which is referred to as the externally connected-MOSFET emitter, exhibits an anomalous increase in drain current, which is induced by impact ionization at the drain edge. Upon evaluating the emission characteristics, it was clarified that the anomalous current increase induced by the impact ionization degraded stability and controllability of the emission current significantly. The other structure, which is referred to as the MOSFET-structured emitter, shows higher reliability with negligible effect of impact ionization     

On the variation of cut-off frequency with emitter end concentration of a diffused base transistor

The effect of mobility degradation at high impurity concentrations on the cut-off frequency of a diffused base transistor with exponential impurity profile in the base has been considered analytically. It has been shown that the cut-off frequency exhibits a maximum with increase in emitter and concentration. The results are compared with those of complementary error function and Gaussian base impurity profiles.     

Modeling base crowding in a bipolar transistor

It is shown that in a model of a bipolar transistor with a rectangular configuration, the base-crowding effect may be represented by a diode and a resistor in parallel between the internal base point and the external base connection with an accuracy of better than four percent.     

Device characteristics of the GaAs/InGaAsN/GaAs p-n-p doubleheterojunction bipolar transistor

We have demonstrated the dc and rf characteristics of a novel p-n-p GaAs/InGaAsN/GaAs double heterojunction bipolar transistor. This device has near ideal current-voltage (I-V) characteristics with a current gain greater than 45. The smaller bandgap energy of the InGaAsN base has led to a device turn-on voltage that is 0.27 V lower than in a comparable p-n-p AlGaAs/GaAs heterojunction bipolar transistor. This device has shown f_T and f_MAX values of 12 GHz. In addition, the aluminum-free emitter structure eliminates issues typically associated with AlGaAs     

Si hetero-bipolar transistor with a fluorine-doped SiC emitter anda thin, highly doped epitaxial base

The effect of fluorine doping on SiC/Si heterojunction bipolar transistors (HBTs) is studied. The film properties of the fluorine-doped SiC and device characteristics of an HBT using the SiC emitter and a 50-nm-thick, highly doped epitaxial base (10¹⁹/cm³) are presented. The current gain is improved from 15 to 80 by doping with fluorine. The current gain is four times larger than that of a conventional poly-Si emitter homo-transistor with the same base structure. In spite of the very thin base, the Early voltage is over 100 V. Forward-bias tunneling current was hardly seen at the emitter-base junction. The fluorine appears to terminate the dangling bonds. The results show the possibility of fabricating transistors with a very thin, highly doped base