USB IP核在深亚微米设计平台中的设计与实现

将USB IP核集成到一块MP3解码芯片上，其设计在0．18μm工艺平台中进行。它可作为一个成熟的IP核嵌入到其它ASIC芯片中。     

IP核的重用与基于平台的SoC设计(上)

为了让更多的读者深入了解系统芯片(SoC)的设计方法,更快地在我国电子设计界组织和推广基于平台的SoC设计方法,作者综述了IC设计方法的发展历史,介绍了SoC芯片设计与IP软核、固核和硬核设计的关系.通过对IP核的要求和对SoC设计环境的介绍,作者展示了几十万门到几千万门组成的系统芯片设计是如何分步骤完成的.我国电子设计界还需要做哪些努力,才能孵化出数目众多的自主IP核开发服务公司,以此为基础营造自己的IP交易平台,从而以更低的成本逐步占领世界高端系统芯片产品的设计市场,为国产电子系统整机设备提供更多的具有自有知识产权模块的SoC芯片.     

基于IP核开发模式的高校集成电路设计发展策略研究

针对当前集成电路领域企业缺少原始技术积累、高校成果转化困难的问题，提出一种以IP核合作方式促进高校集成电路设计加快发展、实现高校企业双赢的创新机制。高校作为我国IC产业链中不可缺少的一部分，以西安交通大学SoC设计中心近十年来的发展历程为案例进行分析，提出基于IP核开发的高校集成电路设计发展的具体策略。     

SoC中的IP核同步设计方法

基于对IP核复用的集成效率考虑,针对片上系统的设计特点构造了一种新型的IP核模型.该模型包括用于描述IP核的延迟信息的时序接口模块、多时钟域适应的再同步接口模块和IP功能描述模块.然后给出了该模型在片上系统中的集成方法.实际电路综合结果表明,和现有IP核集成相比,应用该模型进行片上系统集成,设计效率可以提高近30%,性能提高约15%.     

基于Verilog HDL的全功能UART IP核的设计与实习

随着IC设计技术的发展，IP已经成为SOC设计的关键技术，利用已有IP可大大提高SOC设计的效率和能力。本文通过使用Vernog HDL设计UART(通用异步收发报机)的IP核，说明了IP设计的大体流程以及IP在日后IC设计中的重要作用。     

《半导体国际》互连技术研讨会2008

主题步入深亚微米的互连技术半导体产业发展至今,大部分时间内Al互连技术都扮演了极为重要的角色,铝材料和SiO2一直作为制造集成电路中的微连线或配线：0.13微米以下的设计标准中,采用铝微连线制造的器件开始在可靠性方面出现问题,铜互连工艺应运而生。基于双大马士革的Cu工艺,高／低K介质材料等已成为业界热门话题,进一步改善互连性能的需求,推动今后互连技术的发展。     

IP核设计——中国集成电路产业发展的突破口

随着集成电路设计水平和工艺技术的提高，集成电路规模越来越大，芯片设计规模和设计复杂度也急剧提高，工艺流程呈现专业化，EDA设计逐步发展和完善。到了九十年代出现了SoC芯片（系统级芯片），即可以在一个芯片上包括了CPU、DSP、逻辑电路、模拟电路、射频电路、存储器和其它电路模块以及嵌入软件等，并相互连接构成完整的系统。由于系统设计日益复杂，设计业出现了专门从事开发各种实现不同功能的IP核的专业公司，     

WISHBONE IP核互联总线

介绍了一种新兴的SOC片上总线--WISHBONE.对总线的结构、连接方式、接口信号、数据传输方式及数据顺序作了详细说明,并总结了WISHBONE总线的技术特征.     

误码测试IP核的设计

提出了一种误码测试IP核的设计方案,可嵌入通信系统,作为系统自检单元的一部分完成系统的误码测试。通过IP核内置的异步串行接口,计算机可以对IP核进行参数配置,并读取误码数据进行性能分析。文中介绍了误码测试IP核结构和关键技术的实现,最后给出了计算机上测试软件的开发方法。     

基于VHDL的哈夫曼编码器IP核设计

本文通过一个简单的哈夫曼编码器IP核的设计，研究和实现了基于FPGA的多媒体压缩技术。     

Wrapper design for multifrequency IP cores

This paper addresses the testability problems raised by intellectual property cores with multiple clock domains. The proposed solution is based on a novel core wrapper architecture and a new wrapper design algorithm. It is shown how multifrequency at-speed test response capture can be achieved via the design of capture windows without any structural modifications to the logic within the embedded core. The new features in the core wrapper architecture, which introduce limited hardware overhead, can also synchronize the external tester channels with the core's internal scan chains in the shift mode. Thus, the wrapper implementation space can be explored in order to efficiently utilize the available tester bandwidth while meeting the constraints on the maximum internal shift frequency that guarantees low testing time within the given power ratings. Using experimental data, the benefits of the proposed solution are demonstrated by analyzing the tradeoffs between the number of tester channels, testing time, area overhead, and power dissipation.     

高性能低功率turbo编码器IP核

它可提供1Mbit/s的吞吐量,时钟频率仅为8.2MHz时执行1.5GOPS,在1.5dB信噪比时位误码率达10~(-6)     

Routing architecture optimizations for high-density embedded programmable IP cores

Programmable logic cores differ from stand-alone field-programmable gate arrays in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing architecture of rectangular programmable logic cores. We quantify the effects of having different X and Y channel capacities and show that the optimum ratio between the X and Y channel widths for a rectangular core is between 1.2 and 1.5. We also present a new switch block family optimized for rectangular cores. Further, we quantify the effects of logic block pin placement. Compared with a simple extension of an existing switch block, our new architecture leads to a density improvement of up to 11.9%. Finally, we show that, if the channel width, switch block, and pin placement are chosen carefully, then the penalty for using a rectangular core (compared to a square core with the same logic capacity) is small; for a core with an aspect ratio of 2:1, the area penalty is 1.6% and the speed penalty is 3.8%.     

SoC新技术--可编程逻辑IP核

随着半导体技术的飞速发展,单个硅片上的集成度越来越高,SoC(System-On-a-Chip）已成为IC(Integrated Circuit）设计技术的主流。由于市场竞争的日益激烈,TTM(Time to Market）已成为一个非常重要的因素,直接影响到产品的市场份额和开发商的利润。如何更快、更有效的完成SoC设计逐渐成为人们关注的焦点。可编程逻辑IP核技术的出现有效的缩短了SoC的设计周期并使得芯片设计更具灵活性。本文将对这种技术进行详细的介绍。     

Reusable silicon IP cores for discrete wavelet transform applications

Architectures and methods for the rapid design of silicon cores for implementing discrete wavelet transforms over a wide range of specifications are described. These architectures are efficient, modular, scalable, and cover orthonormal and biorthogonal wavelet transform families. They offer efficient hardware utilization by exploiting a number of core wavelet filter properties and allow the creation of silicon designs that are highly parameterized, including in terms of wavelet type and wordlengths. Control circuitry is embedded within these systems allowing them to be cascaded for any desired level of decomposition without any interface glue logic. The time to produce chip designs for a specific wavelet application is typically less than a day and these are comparable in area and performance to handcrafted designs. They are also portable across a wide range of silicon foundries and suitable for field programmable gate array and programmable logic data implementation. The approach described has also been extended to wavelet packet transforms.     

基于路径延时匹配的硬件IP核知识产权保护方法

随着集成电路产业的迅速发展,集成电路设计的安全性越来越受重视,电路设计盗用等知识产权(IP)侵权行为严重损害了设计者和消费者的权益,阻碍了集成电路产业的发展。本文提出了一种有效保护IP核的方法,通过设计一个保护电路,控制功能电路运行结果的输出,在消费者未取得合法授权时,功能电路无法正常工作,从而达到了保护电路的目的。本文将该保护方法运用在实际的电路上,进行仿真并验证了该方法的有效性。     

ARM芯核的广泛应用和激烈竞争

ＡＲＭ是１９９０年１１月成立的一家英国公司,１０多年来发展迅速,现拥有员工７００多名,１９９５年~２０００年间的年均增长率达３８%,从２０００万英镑提高到１亿英镑。去年许许多多半导体公司大亏本,而ＡＲＭ的营收却独傲群芳,上升 ４５%,达到 １．４６亿英镑(约合２亿美元)。公司是一家无工厂、无芯片公司,已成长为世界顶尖的ＩＰ(知识产权设计模块)供应商,引领业界嵌入式计算技术发展潮流。     

Enhancing IP cores specifications using hierarchical composition and set theory

During the functional verification, complex interactions between multiple blocks that compose an Intellectual Property (IP) core can reveal hard-to-find bugs. Functional verification specifications must be precise to assure these interactions occur during the simulation. In this work, we are proposing a technique for improving the functional verification specification of individual blocks, preserving the occurrence of these interaction scenarios in the composition phase. Our approach was implemented for the VeriSC methodology, a SystemC-based functional verification methodology. After each block that composes the IP core was stand-alone verified, we exploit the composition phase using set theory to increase the coverage numbers and to justify why some of these numbers cannot, or need not, reach 100%. By applying our approach in a MPEG 4 video decoder design, we show how our work can save functional verification time during the hierarchical composition. Using mutation based-tests, we demonstrate that our work can contribute to error detection. Furthermore, we demonstrate the effectiveness of our approach with regard to traditional structural coverage metrics, such as line coverage and branch coverage.     

现代电子设计工具与IP核的重用

简单介绍了硬件描述语言（HDL）和IP的概念;采用HDL和IP设计方法的优点;综述了目前世界上著名的ESDA厂商的前端设计工具;推广IP设计方法中的几个重要问题;以及由此对复杂数字电路系统设计和EDA工具发展产生的影响。对我国怎样在有限的人力物力的条件下培养人才,逐步推广HDL和IP设计方法提出了建议。     

基于开源IP核的视频解码SoC平台研究

文章设计了一款基于开源IP核的SoC视频解码平台,该平台中使用的IP均经过了CQIP系统的严格评测,并在Xilinx公司的FPGA上进行了验证,实验结果证明该系统具有良好的实时性和较低的功耗,非常适合于便携式设备。