共查询到20条相似文献,搜索用时 15 毫秒
1.
《Components and Packaging Technologies, IEEE Transactions on》2008,31(3):661-669
2.
Zhuqing Zhang Sitaraman S.K. Wong C.P. 《Electronics Packaging Manufacturing, IEEE Transactions on》2004,27(1):86-93
Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated. 相似文献
3.
Tong Hong Wang Ching-Chun Wang Yi-Shao Lai Kuo-Chin Chang Chien-Hsun Lee 《Microelectronic Engineering》2008,85(4):659-664
In this paper, we study board-level thermomechanical reliability of a high performance flip-chip ball grid array package assembly subjected to an accelerated thermal cycling test condition. Different control factors are considered for an optimal design towards enhancement of the thermal fatigue resistance of solder joints. These factors include solder composition, underfill, substrate size, lid thickness, stiffener ring width, test board size, soldermask opening on the substrate side, and pad size on the test board. The shape of solder joints after reflow is estimated using Surface Evolver. The optimal design is obtained using an L18 orthogonal array according to the Taguchi optimization method. Importance of these control factors on the board-level thermomechanical reliability of the package is also ranked. 相似文献
4.
Paul S. Ho Guotao Wang Min Ding Jie-Hua Zhao Xiang Dai 《Microelectronics Reliability》2004,44(5):719-737
In this article, we review the reliability issues for plastic flip-chip packages, which have become an enabling technology for future packaging development. The evolution of area-array interconnects with high I/O counts and power dissipation has made thermal deformation an important reliability concern for flip-chip packages. Significant advances have been made in understanding the thermo-mechanical behavior of flip-chip packages based on recent studies using moiré interferometry. Results from moiré studies are reviewed by focusing on the role of the underfill to show how it reduces the shear strains of the solder balls but shifts the reliability concern to delamination of the underfill interfaces. The development of the high-resolution moiré interferometry based on the phase-shift technique provided a powerful method for quantitative analysis of thermal deformation and strain distribution for high-density flip-chip packages. This method has been applied to study plastic flip-chip packages and the results and impacts on delamination at the die/underfill interface and in the underfill region above the plated through-hole via are discussed. Here a related reliability problem of die cracking during packaging assembly and test is also discussed. Finally, we discuss briefly two emerging reliability issues for advanced flip-chip packages, one on the packaging effect on Cu/low k interconnect reliability and the other on electromigration of solder balls in flip-chip packages. 相似文献
5.
Milner D. Baldwin D.F. 《Electronics Packaging Manufacturing, IEEE Transactions on》2001,24(4):307-312
Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance 相似文献
6.
Kuo-Ning Chiang Zheng-Nan Liu Chih-Tang Peng 《Components and Packaging Technologies, IEEE Transactions on》2001,24(4):635-640
This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput 相似文献
7.
Seungbae Park Lee H.C. Sammakia B. Raghunathan K. 《Components and Packaging Technologies, IEEE Transactions on》2007,30(2):294-301
An analytical model is developed to predict the out-of- plane deformation and thermal stresses in multilayered thin stacks subjected to temperature. Coefficient of thermal expansion mismatches among the components (chip, substrate, underfill, flip-chip interconnect or C4s) are the driving force for both first and second levels interconnect reliability concerns. Die cracking and underfill delamination are the concerns for the first level interconnects while the ball grid array solder failure is the primary concern for the second level interconnects. Inadvertently, many researchers use the so-called rule of mixture in its effective moduli for the flip chip solder (C4)/underfill layer. In this study, a proper formula for effective moduli of solder (C4)/underfill layer, is presented. The classical lamination theory is used to predict the out-of-plane displacement of the chip substrate structure under temperature variation (DeltaT). The warpage and stresses resulting from the analytical formulation are compared with the 3-D finite element analysis. The study helps to design more reliable components or assemblies with the design parameters being optimized in the early stage of the development using closed form analytical solutions. 相似文献
8.
Sitaraman S.K. Raghunathan R. Hanna C.E. 《Components and Packaging Technologies, IEEE Transactions on》2000,23(3):452-461
The number of thermal cycles, the temperature range, and the time of dwell used for qualifying a microelectronic package should be based on the type of application the package is intended for. However, in the absence of specific guidelines, the industrial practice is to subject the devices to military-standard qualification tests without adequate consideration for the application the devices are intended for. This work aims at developing temperature cycling guidelines for packages used in implantable medical devices and automotive applications taking into consideration the thermal history associated with the field conditions. Numerical models have been developed that take the time- and temperature-dependent behavior of the solder joints and the viscoelastic behavior of the underfill besides the temperature-dependent orthotropic properties of the substrate for a flip-chip on board (FCOB) assembly and a flip chip chip-scale package (FCCSP) on organic board assembly. The models account for solder reflow process, underfill cure process, and burn-in testing of the devices. Qualification temperature cycling guidelines have been developed for implantable devices based on the information collected in terms of shipping, EM sterilization, and implantation temperature profiles, and for the automotive devices based on the representative field conditions 相似文献
9.
Wong E. H. Koh S. W. Lee K. H. Lim K.-M. Lim T. B. Mai Y.-W. 《Advanced Packaging, IEEE Transactions on》2006,29(4):751-759
Two advanced techniques have been developed for modeling vapor pressure within the plastic IC packages during solder reflow. The first involves the extension of the "wetness" technique to delamination along multimaterial interface and during dynamic solder reflow. Despite its simplicity, this technique is capable of offering reliable and accurate prediction for packages with high flexural rigidity. For packages with low flexural rigidity, the new "decoupling" technique that integrates thermodynamics, moisture diffusion, and structural analysis into a unified procedure has been shown to be more useful. The rigorous technique has been validated on both leadframe-based as well as laminate-based packages. With high accuracy and computational efficiency, these dynamic modeling tools will be valuable for optimization of package construction, materials, and solder reflow profile against popcorn cracking for both SnPb and Pb-free solders 相似文献
10.
Chun-Chih Chuang Tsung-Fu Yang Jin-Ye Juang Yin-Po Hung Chau-Jie Zhan Yu-Min Lin Ching-Tsung Lin Pei-Chen Chang Tao-Chih Chang 《Microelectronics Reliability》2008,48(11-12):1875-1881
A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn3.0Ag0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package. 相似文献
11.
Se Young Yang Young-Doo Jeon Soon-Bok Lee Kyung-Wook Paik 《Microelectronics Reliability》2006,46(2-4):512-522
To meet the future needs of high pin count and high performance, package size of flip-chip devices is constrained to become larger. In addition, to fulfill the environment issues, lead free solders will be replacing lead contained eutectic (Sn/37Pb) in near future. Thus, in this work, the effect of residual warpage and consequent residual stress on the reliability of large flip-chip using lead free solder is examined. Several effective experimental approaches to accurately measure residual warpage, using Moiré interferometry, shadow Moiré, and image processing schemes, are introduced. Moreover, geometric, process, and material parameters affecting the residual warpage during reflow process are discussed and some modifications are suggested. Finally, it is verified that it is crucial to accurately quantify and control the residual warpage in order to guarantee the overall reliability of flip-chip packages regardless of presence of underfill. 相似文献
12.
In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed. 相似文献
13.
The effects of underfill and its material models onthermomechanical behaviors of a flip chip package
Liu Chen Qun Zhang Guozhoag Wang Xioming Xie Zhaonian Cheng 《Advanced Packaging, IEEE Transactions on》2001,24(1):17-24
In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity 相似文献
14.
《Advanced Packaging, IEEE Transactions on》2005,28(3):413-420
This paper presents a new package design for multichip modules. The developed package has a flip-chip-on-chip structure. Four chips [simulating dynamic random access memory (DRAM) chips for demonstration purpose] are assembled on a silicon chip carrier with eutectic solder joints. The I/Os of the four chips are fanned-in on the silicon chip carrier to form an area array with larger solder balls. A through-silicon via (TSV) hole is made at the center of the silicon chip carrier for optional underfill dispensing. The whole multichip module is mounted on the printed circuit board by the standard surface mount reflow process. After the board level assembly and X-ray inspection, the underfill process is applied to some selected specimens for comparative study purpose. The underfill material is dispensed through the center TSV hole on the silicon chip carrier to encapsulate the solder joints and the four smaller chips. Subsequently, scanning acoustic microscopy (SAM) is performed to inspect the quality of underfill. After the board-level assembly, all specimens are subject to the accelerated temperature cycling (ATC) test. During the ATC test, the electrical resistance of all specimens is monitored. The experimental results show that the packages without underfill encapsulation may fail in less than 100 thermal cycles while those with underfill can last for more than 1200 cycles. From the dye ink analysis and the cross-section inspection, it is identified that the packages without underfill have failure in the silicon chip carrier, instead of solder joints. The features and merits of the present package design are discussed in details in this paper. 相似文献
15.
Bo-In Noh Jeong-Won Yoon Sang-Ok Ha Seung-Boo Jung 《Journal of Electronic Materials》2011,40(2):224-231
The hygrothermal and mechanical reliability of board-level packages with various underfills under sequential temperature and
humidity (TH) testing and drop testing were investigated. Board-level packages with underfill had greater resistance to drop
shock than that without underfill, indicating that underfill protects the package from failure by absorption of the applied
drop shock. The underfill, which was composed of polypropylene glycol epoxy resin and silane, exhibited good reliability for
drop shock because of the improved adhesion of the underfill compared with that without the polypropylene glycol epoxy resin
and silane. In addition, the drop reliability of board-level packages with underfill decreased with increasing TH test duration.
Adhesion between the substrate and underfill or between the solder and underfill was decreased by moisture absorption. Components
positioned at the board center were more susceptible to failure by drop shock than were corner components. 相似文献
16.
Jong-Kai Lin De Silva A. Frear D. Guo Y. Hayes S. Jin-Wook Jang Li L. Mitchell D. Yeung B. Zhang C. 《Electronics Packaging Manufacturing, IEEE Transactions on》2002,25(4):300-307
A variety of Pb-free solders and under bump metallurgies (UBMs) was investigated for flip chip packaging applications. The result shows that the Sn-0.7Cu eutectic alloy has the best fatigue life and it possess the most desirable failure mechanism in both thermal and isothermal mechanical tests regardless of UBM type. Although the electroless Ni-P UBM has a much slower reaction rate with solders than the Cu UBM, room temperature mechanical fatigue is worse than on the Cu UBM when coupled with either Sn-3.8Ag-0.7Cu or Sn-3.5Ag solder. The Sn-37Pb solder consumes less Cu UBM than all other Pb-free solders during reflow. However, Sn-37Pb consumes more Cu after solid state annealing. Studies on aging, tensile, and shear mechanical properties show that the Sn-0.7Cu alloy is the most favorable Pb-free solder for flip chip applications. When coupled with underfill encapsulation in a direct chip attach (DCA) test device, the Sn-0.7Cu bump with Cu UBM exhibits a characteristic life or 5322 cycles under -55/spl deg/C/+150/spl deg/C air-to-air thermal cycling condition. 相似文献
17.
Yaomin Lin Wenning Liu Yifan Guo Shi F.G. 《Advanced Packaging, IEEE Transactions on》2005,28(1):79-88
A significant need exists for the determination of critical stress characteristics within the low-cost overmolded flip-chip (OM-FC) packages. A systematic stress analysis is reported to investigate the OM-FC package for the optimal design of package geometries, materials combinations during the attachment, and thermal testing processes. A parametric study is conducted seeking the best package performance during the identified most stringent process which causes the largest stress within the low-cost substrate. High-stress location is predicted by finite-element analysis, and it was found that mold compound (MC) curing is the most stringent process for the reliability of substrate; higher underfill fillet, thicker die, larger die size without causing edge effect, solder mask defined structure resulted in smaller stresses in substrate. MC with lower coefficient of thermal expansion is a preferable and compliant substance that is good for using as molding and underfill material 相似文献
18.
As a concept to achieve high throughput low cost flip-chip assembly, a process development activity is underway, implementing next generation flip-chip processing based on large area underfill printing/dispensing, IC placement, and simultaneous solder interconnect reflow and underfill cure. The self-alignment of micro-BGA (ball grid array, BGA) package using flux and two types of no-flow underfill is discussed in this paper. A “rapid ramp” temperature profile is optimized for reflow of micro-BGA using no-flow underfill for self-aligning and soldering. The effect of bonding force on the self-alignment is also described. A SOFTEX real time X-ray inspection system was used to inspect samples to ensure the correct misalignment before reflow, and determine the residual displacement of solder joints after reflow. Cross-sections of the micro-BGA samples are taken using scanning electronic microscope. Our experimental results show that the self-alignment of micro-BGA using flux is very good even though the initial misalignment was greater than 50% from the pad center. When using no-flow underfill, the self-alignment is inferior to that of using flux. However, for a misalignment of no larger than 25% from the pad center, the package is also able to self-align with S1 no-flow underfill. However, when the misalignment is 37.5–50% from the pad center, there are 10–14% residual displacement after reflow. The reason is the underfill resistant force inhibiting the self-alignment of the package due to rapid increment of underfill viscosity during reflow. The self-alignment of micro-BGA package using no-flow underfill allows only <25% misalignment prior to the soldering. During assembling, although the bonding force does not influence on the self-alignment of no-flow underfill, a threshold bonding force is necessary to make all solder balls contact with PCB pads, for good soldering. The no-flow underfill is necessary to modify the fluxing/curing chemistry for overcoming the effect of tin metal salt produced during soldering on underfill curing, and for maintaining the low viscosity during soldering to help self-alignment. 相似文献
19.
Zhuqing Zhang Wong C.P. 《Electronics Packaging Manufacturing, IEEE Transactions on》2002,25(2):113-119
Lead-free solder reflow process has presented challenges to no-flow underfill material and assembly. The currently available no-flow underfill materials are mainly designed for eutectic Sn-Pb solders. This paper presents the assembly of lead-free bumped flip-chip with developed no-flow underfill materials. Epoxy resin/HMPA/metal AcAc/Flux G system is developed as no-flow underfills for Sn/Ag/Cu alloy bumped flip-chips. The solder wetting test is conducted to demonstrate the fluxing capability of the underfills for lead-free solders. A 100% solder joint yield has been achieved using Sn/Ag/Cu bumped flip-chips in a no-flow process. A scanning acoustic microscope is used to observe the underfill voiding. The out-gassing of HMPA at high curing temperatures causes severe voiding inside the package. A differential scanning calorimeter (DSC) used to study the curing degree of the underfill after reflow with or without post-cure. The post-curing profiles indicate that the out-gassing of HMPA would destroy the stoichiometric balance between the epoxy and hardener, and result in a need for high temperature post-cure. The material properties of the underfills are characterized and the influence of underfill out-gassing on the assembly and material properties is investigated. The impact of lead-free reflow on the material design and process conditions of no-flow underfill is discussed. 相似文献
20.
As one of the key requirements of the no-flow underfill materials for flip-chip applications, a proper self-fluxing agent must be incorporated in the developed no-flow underfill materials to provide proper fluxing activity during the simultaneous solder reflow and underfill material curing. However, most fluxing agents have some adverse effects on the no-flow underfill material properties and assembly reliability. In this paper, we have extensively investigated the effects of the concentration of the selected fluxing agent on the material properties, interconnect integrity and assembly reliability. Through this work, an optimum concentration window of the fluxing agent is obtained and a routine procedure of evaluating fluxing agents is established 相似文献