A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector

This paper presents a multiphase-output delay-locked loop (MODLL). The proposed phase/frequency detector (PFD) utilizes a new NAND-resettable dynamic D-flip-flop (DFF) circuit to achieve a shorter reset path. Thus, lower power consumption and higher speed can be obtained. The proposed voltage-controlled delay element used in this design can operate at a lower supply voltage and overcome the dead-band issue of the voltage-controlled delay line. An experimental multiphase-output DLL was designed and fabricated using a TSMC 0.35-$mu$m 2P4M CMOS process. The delay-locked loop (DLL) power consumption is 3.4 mW with a 2 V supply and a 100 MHz input. The measured rms and peak-to-peak jitters are 17.575 ps and 145 ps, respectively. In addition, the supply voltage of the experimental multiphase-output DLL can vary from 1.5 V to 2.5 V without causing malfunctions. The active area is 426 $mu$m $times$ 381 $mu$m.      

A Delay-Locked Loop With Statistical Background Calibration

A delay-locked loop (DLL) using a statistical background calibration circuit (SBCC) is presented. This SBCC is utilized to calibrate the charge pump. Eighty identical arbiters with random mismatch effectively measure the phase error between the input and output clocks. Therefore, the static phase error of the DLL is improved. The proposed DLL has been fabricated in 0.18- $mu$m CMOS process. Its active area is 0.078 ${hbox {mm}}^{2}$ . The power dissipation is 35 mW for the supply of 1.8 V and the input clock of 1.2 GHz. This DLL operates from 900 MHz to 1.2 GHz. The measured static phase error is 15.45 and 2.92 ps without and with the SBCC, respectively at 1.2 GHz.      

Analysis of DLL Jitter due to Voltage-Controlled Delay Line

In this paper we analyze jitter in a delay-locked loop (DLL) due to uncertainties in the voltage-controlled delay line (VCDL). To obtain a closed-form equation for jitter in the DLL, time-domain equations of the DLL are used. The jitter at the intermediate stages of the VCDL and the jitter of a conventional delay cell are analyzed. The simulation results show that the jitter of the DLL due to mismatch of the delay cells is zero at the beginning and end of the VCDL and is highest at the middle of the VCDL. Also, a DLL is designed in TSMC 0.18 μm CMOS technology to show the accuracy of the proposed analytical method.     

用于时钟恢复电路的低抖动可变延迟线锁相环电路

文中给出了一个基于压控可变延迟线的电荷泵锁相环电路的设计,用于时钟恢复电路中采样时钟沿的定位,它的工作不受环境和工艺的影响,保证了采集数据的准确性。应用于延迟线中的改进的延迟单元有效地减小了相位抖动,环路滤波电路的设计避免了电荷重新分配引入的影响。电路采用0.35umTSMC的MOS工艺,在3.3V的低电压下工作,模拟得到在最坏情况下,单个延迟模块的相位抖动为20ps,输出静态相位误差仅45ps。     

A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration

A 3–8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitters at 8 GHz are 11.44 and 6.67 ps before and after calibration, respectively. The power dissipation at 8 GHz is 18 mW for a supply voltage of 1.2 V, and the measured output duty cycle variation is less than 3%.      

Wiener's Analysis of the Discrete-Time Phase-Locked Loop With Loop Delay

The discrete-time phase-locked loop (PLL) operating at the steady state is considered in this paper. Phase noise, which always affects oscillators, is modeled as a stationary random waveform and optimization of the loop filter is worked out in the light of Wiener's theory. Delay in the loop, which may affect the numerical implementation of the PLL, is considered. The main results and novelties of this paper are the optimal loop filter and the minimum mean-square error (MSE) that can be achieved for a given spectrum of phase noise and for a given delay in the loop. Closed-form expressions for the loop filter and for the MSE are given for the case where the phase noise is characterized as a second-order disturbance. Application of these results to carrier recovery based on the Costas loop is presented in this paper.     

Statistical Properties of First-Order Bang-Bang PLL With Nonzero Loop Delay

A method to solve the stationary state probability is presented for the first-order bang-bang phase-locked loop (BBPLL) with nonzero loop delay. This is based on a delayed Markov chain model and a state flow diagram for tracing the state history due to the loop delay. As a result, an eigenequation is obtained, and its closed form solutions are derived for some cases. After obtaining the state probability, statistical characteristics such as mean gain of the binary phase detector and timing error variance are calculated and demonstrated.      

Cyclic Delay Diversity with Phase Shift in Low Rate SC-FDMA Uplink

This paper proposes a phase shift scheme in cyclic delay diversity (CDD) for single-carrier frequency division multiple access in Internet of Things (IoT) applications. The proposed scheme is assumed to be applied to the uplink of long term evolution (LTE) systems. Since the transmission rates of IoT applications are small, each uplink connection may occupy less than 12 subcarriers that corresponds to one resource block of the LTE. Since the length of the data sequence in time domain is short so that CDD may provide limited frequency diversity. The proposed scheme shifts the phases of the data symbols in time domain and spreads each subcarrier component over multiple subcarriers. Thus, more diversity gain can be realized with CDD. Numerical results obtained through computer simulation shows that the proposed scheme improves the performance by about 5–7 dB at the bit error rate of 10^?4 for the data sequence length of 4. It is also shown that no increase of peak-to-average power ratio is observed with the proposed scheme.

     

采用可复位延迟链形成无谐波、快速锁定的延迟锁相环

为提高锁定速度,一种带单步复位（RES）延迟链的全数位延迟锁相环（ADDLL）得以发展。随着新的可复位技术的发展,DLL快速锁定和无谐波的特点逐渐显现。主要在常见的DLL电路中加入可复位延迟链,采用SI MC 180 nmCOMS工艺,并采用Synopsys的HSI M仿真器对电路进行仿真。仿真结果显示,改进的DLL工作频率范围可达50～250 MHz,锁定时间明显减小,且无谐波信号。     

Excitation of an Infinite Microstrip Line With a Vertical Coaxial Feed

An efficient method is presented for the analysis of a vertical coaxial probe excitation of an infinite microstrip line. The novel feature of the method is that it uses a semianalytical Green's function that is derived for current sources in the presence of the infinite microstrip line. Hence, in a method of moments approach, unknown currents need only be placed on the conducting probe feed and not on the infinite strip surface. The method also utilizes an attachment mode at the contact point between the probe and line so that the correct Kirchhoff condition is automatically satisfied. Once the surface current density on the probe is known, the surface current density on the strip conductor can be readily obtained using the Green's function of the background grounded substrate. The method is valid even at high frequency, where simple transmission line theory fails to account for effects such as the continuous-spectrum current that is excited on the line. After validating the method with various commercial software simulation packages, results are presented to study the fundamental behavior of the input impedance, probe current, and current launched on the microstrip line, and to examine the high-frequency behavior of these currents.      

一种基于电荷泵锁相环的高精度数字移相方法

移相器是相控阵雷达的核心器件,随着工作频率的逐步提升,传统移相器的插入损耗和相位控制误差恶化严重,导致额外增加的功耗及波束性能变差.本文基于电荷泵锁相环（Charge Pump Phase-Locked Loop,CP-PLL）开展了高精度数字移相方法的研究.在分析CP-PLL相位数学模型与移相机理的基础上,提出了通过数控电流源的方法实现对输出信号相位的精确控制,建立电路模型开展仿真分析,并设计了实验电路模块,通过仿真和实测的对比验证了该方法的有效性和精确性,实现了移相步进优于1°,移相精度优于移相值的10%.该CP-PLL可通过作为本振信号或直接产生发射信号应用于相控阵雷达系统中,具有精度高、功耗低、易集成等特点,从而取代移相器,有效提升相控阵雷达的性能.     

采用倒相换能器结构的宽带SAW延迟线

报道了两种采用倒相换能器（ＰＲＴ）结构设计的声表面波宽带延迟线，一种制作于石英材料之上，另一种制作于ＬｉＴａＯ＿３基片之上，其相对带宽均大于２２％。     

Broadband Self-Compensating Phase Shifter Combining Delay Line and Equal-Length Unequal-Width Phaser

In this paper, a broadband self-compensating phase shifter is presented and developed on the basis of substrate integrated waveguide (SIW) technology. Since the SIW is a dispersive guided-wave structure, the effective bandwidth of SIW phase shifter is usually narrow. Phase shifts generated by two different structures, namely delay line and equal-length unequal-width phase shifter, are discovered in this work to present interesting opposite tendencies versus frequency. Therefore, an appropriate combination of them will make the phase shift almost constant over a very wide band. Design equations and process are given following a mathematical analysis. To demonstrate the interesting and useful features of the proposed technique, a 90 $^{circ}$ and a 45 $^{circ}$ self-compensating phase shifters are designed as showcases with standard printed circuit board process. For the 90$^{circ}$ version, the measured amplitude and phase imbalance between the two paths are within 0.2 dB and 2.5$^{circ}$ , respectively, within the frequency band from 25.11 to 39.75 GHz, or around 49% bandwidth. The return loss is found to be better than 12 dB within the frequency band of interest. The 45 $^{circ}$ one has the similar excellent performance. The measurements demonstrate that this type of SIW phase shifter is superior to all of its counterparts.      

基于声表面波延迟线的相位解调器设计

该文提出了一种基于声表面波延迟线的相位解调器,其原理是利用声表面波延迟线将调相信号转换为调幅信号,并采用“延迟相加”的方法进行解调。该延迟线实现了频率2.695～3.000 GHz内1μs的延迟时间,解调器可以实现调制速率为500 kHz和1 MHz的二进制相移键控(BPSK)调制信号的解调。     

高速率外差式延迟锁定环及其多普勒捕获跟踪性能

分析了高速率外差式延迟锁定环的构成，环路模型、存在多普勒频移的捕获和跟踪性能，介绍了其电路设计和实验结果。     

微波Q值测量中的馈线相移消除方法

 提出了一种实用的测量微波谐振器无载品质因素的方法,在临界点法的基础上,消除了馈线引入的相移.该相移的出现会使谐振器等效阻抗曲线在Smith圆图中发生旋转,进而影响到测量结果.通过在Smith圆图中对测量的输入阻抗曲线进行旋转,根据寻找出的一个目标函数来判断合适的旋转角度,即为馈线引入的相移.对所提出的方法进行了数值模拟,并通过了一组实测数据做了验证.     

Design of a Reflection-Type Phase Shifter With Wide Relative Phase Shift and Constant Insertion Loss

reflection-type phase shifter with constant insertion loss over a wide relative phase-shift range is presented. This important feature is attributed to the salient integration of an impedance-transforming quadrature coupler with equalized series-resonated varactors. The impedance-transforming quadrature coupler is used to increase the maximal relative phase shift for a given varactor with a limited capacitance range. When the phase is tuned, the typical large insertion-loss variation of the phase shifter due to the varactor parasitic effect is minimized by shunting the series-resonated varactor with a resistor R_p. A set of closed-form equations for predicting the relative phase shift, insertion loss, and insertion-loss variation with respect to the quadrature coupler and varactor parameters is derived. Three phase shifters were implemented with a silicon varactor of a restricted capacitance range of C_v,_min = 1.4 pF and C_v,_max = 8 pF, wherein the parasitic resistance is close to 2 Omega. The measured insertion-loss variation is 0.1 dB over the relative phase-shift tuning range of 237deg at 2 GHz and the return losses are better than 20 dB, excellently agreeing with the theoretical and simulated results.     

Microwave Photonic Delay Line With Separate Tuning of the Optical Carrier

Significant performance improvement for photonic delay lines in microwave-photonics based on a new concept of separately tuning the optical carrier is proposed and analyzed. Optical microresonator delay lines using a balanced SCISSOR design with additional resonators to separately tune the carrier phase delay to provide a true-time-delay for the broadband microwave signal are presented. Significant improvements in broadband tunable delay and devices losses are predicted.      

Analysis and Implementation of a 0.9-V Voltage-Controlled Oscillator With Low Phase Noise and Low Power Dissipation

A voltage-controlled oscillator (VCO) with low phase noise and low power dissipation for IEEE 802.11b is proposed. A negative resistance multiple-gated circuit with a bypass capacitor is adopted to improve phase noise. The chip is implemented in 0.18-$mu{hbox {m}}$ CMOS process under a supply voltage of 0.9 V and power consumption of 2.7 mW. Its measured results show that the VCO has a phase noise of $-$122.3 dBc/Hz at 1-MHz offset frequency from the carrier frequency, and the tuning frequency from 2.17 to 2.73 GHz can be obtained under the tuning voltage of $-$0.9 to 0.9 V. The theoretical analysis and design consideration are also conducted in detail to show the benefits of the proposed VCO.      

An Active RC Delay Line for Matched Filters Correlators

For a matched filter correlator (MFC) required in a spread spectrum receiver, an active RC delay line has been developed and its performance evaluated. The building block of the delay line is a low pass type active RC filter with modifications to give desirable magnitude, phase and pulse response. An MFC processor for a bandwidth expansion of 15 in data communication application has been made using the RC delay lines and its experimental performance has been found to be close to the theoretical one.