一种低功耗双重测试数据压缩方案

随着集成电路制造工艺的发展,VLSI（Very Large Scale Integrated）电路测试面临着测试数据量大和测试功耗过高的问题.对此,本文提出一种基于多级压缩的低功耗测试数据压缩方案.该方案先利用输入精简技术对原测试集进行预处理,以减少测试集中的确定位数量,之后再进行第一级压缩,即对测试向量按多扫描划分为子向量并进行相容压缩,压缩后的测试向量可用更短的码字表示;接着再对测试数据进行低功耗填充,先进行捕获功耗填充,使其达到安全阈值以内,然后再对剩余的无关位进行移位功耗填充;最后对填充后的测试数据进行第二级压缩,即改进游程编码压缩.对ISCAS89基准电路的实验结果表明,本文方案能取得比golomb码、FDR码、EFDR码、9C码、BM码等更高的压缩率,同时还能协同优化测试时的捕获功耗和移位功耗.     

动态向量调整的多扫描链测试数据压缩

 由于多扫描链测试方案能够提高测试进度,更适合大规模集成电路的测试,因此提出了一种应用于多扫描链的测试数据压缩方案.该方案引入循环移位处理模式,动态调整向量,能够保留向量中无关位,增加向量的外延,从而提高向量间的相容性和反向相容性;同时,该方案还能够采用一种有效的参考向量更替技术,进一步提高向量间的相关性,减少编码位数.另外,该方案能够利用已有的移位寄存器,减少不必要的硬件开销.实验结果表明所提方案在保持多扫描链测试优势的前提下能够进一步提高测试数据压缩率,满足确定性测试和混合内建自测试.     

一种混合定变长虚拟块游程编码的测试数据压缩方案

 文章提出了一种混合定变长虚拟块游程编码的测试数据压缩方案,该方案将测试向量级联后分块,首先在块内找一位或最大一位表示,再对块内不能一位表示的剩下位进行游程编码,这样减少了游程编码的数据量,从而突破了传统游程编码方法受原始测试数据量的限制.对ISCAS 89部分标准电路的实验结果显示,本文提出的方案在压缩效率明显优于类似的压缩方法,如Golomb码、FDR码、VIHC码、v9C码等.     

双游程编码的无关位填充算法

双游程编码是集成电路测试数据压缩的一种重要方法,可分为无关位填充和游程编码压缩两个步骤.现有文献大都着重在第二步,提出了各种不同的编码压缩算法,但是对于第一步的无关位填充算法都不够重视,损失了一定的潜在压缩率.本文首先分析了无关位填充对于测试数据压缩率的重要性,并提出了一种新颖的双游程编码的无关位填充算法,可以适用于不同的编码方法,从而得到更高的测试数据压缩率.该算法可以与多种双游程编码算法结合使用,对解码器的硬件结构和芯片实现流程没有任何的影响.在ISCAS89的基准电路的实验表明,对于主流的双游程编码算法,结合该无关位填充算法后能提高了6%-9%的测试数据压缩率.     

基于数据相关性的测试数据压缩方法

为了减少测试数据量,提出一种利用数据中大量无关位的特殊相关性进行编码压缩的方法,压缩步骤分两步,先选定参考数据,然后利用相关性将与参考数据兼容的数据块编码为"11",数据互补的数据块编码为"10",弥补了FDR码单一编码的不足.解压结构包括一个与参考数据等长的循环移位寄存器和一个有限状态机,结构简单,与Golomb码和FDR码中需要一个与测试向量等长的循环移位寄存器相比,消耗的硬件资源小.针时ISCAS-89标准电路测试向量集的压缩实验结果表明,该方法可以有效地压缩测试数据.且效果比Golomb码和FDR码更好,硬件开销更小.     

基于变游程编码的测试数据压缩算法

基于IP核的设计思想推动了SOC设计技术的发展,却使SOC的测试数据成几何级数增长.针对这一问题,本文提出了一种有效的测试数据压缩算法——变游程(Variable-Run-Length)编码算法来减少测试数据量、降低测试成本.该算法编码时同时考虑游程0和游程1两种游程,大大减小了测试数据中长度较短游程的数量,提高了编码效率.理论分析和实验数据表明,变游程编码能取得较同类编码算法更高的压缩效率,能够显著减少测试时间、降低测试功耗和测试成本.     

一种基于测试集分组的广义交替码

测试数据编码压缩是一类重要、经典的测试源划分（TRP）方法。本文提出了一种广义交替码,将FDR码、交替码都看作它的特例;又扩展了两步压缩方法,将原测试集划分成多组,每组采用不同的比值进行交替编码,综合了交替码与两步编码各自的优势,弥补了FDR码,交替码对某些电路测试集压缩的缺陷,得到了较好的压缩率。实验结果表明,与同类型的编码压缩方法相比,该方案具有更高的测试数据压缩率和较好的综合测试性能。     

基于镜像对称参考切片的多扫描链测试数据压缩方法

为了减少测试数据和测试时间,该文提出一种基于镜像对称参考切片的多扫描链测试数据压缩方法。采用两个相互镜像对称的参考切片与扫描切片做相容性比较,提高了相容概率。若扫描切片与参考切片相容,只需要很少的几位编码就可以表示这个扫描切片,并且可以并行载入多扫描链;若不相容,参考切片被该扫描切片替换。提出一种最长相容策略,用来处理扫描切片与参考切片同时满足多种相容关系时的选取问题。根据Huffman编码原理确定不同相容情况的编码码字,可以进一步提高测试数据的压缩率。实验结果表明所提方法的平均测试数据压缩率达到了69.13%。     

一种基于编码的低硬件开销的测试数据压缩方法

提出了一种新的测试数据压缩/解压缩的算法,称为混合游程编码,它充分考虑了测试数据的压缩率、相应硬件解码电路的开销以及总的测试时间.该算法是基于变长-变长的编码方式,即把不同游程长度的字串映射成不同长度的代码字,可以得到一个很好的压缩率.同时为了进一步提高压缩率,还提出了一种不确定位填充方法和测试向量的排序算法,在编码压缩前对测试数据进行相应的预处理.另外,混合游程编码的研究过程中充分考虑到了硬件解码电路的设计,可以使硬件开销尽可能小,并减少总的测试时间.最后,ISCAS 89 benchmark电路的实验结果证明了所提算法的有效性.     

应用混合游程编码的SOC测试数据压缩方法

本文提出了一种有效的基于游程编码的测试数据压缩/解压缩的算法:混合游程编码,它具有压缩率高和相应解码电路硬件开销小的突出特点.另外,由于编码算法的压缩率和测试数据中不确定位的填充策略有很大的关系,所以为了进一步提高测试压缩编码效率,本文还提出一种不确定位的迭代排序填充算法.理论分析和对部分ISCAS 89 benchmark电路的实验结果证明了混合游程编码和迭代排序填充算法的有效性.     

Capture-power-aware test data compression using selective encoding

Ever-increasing test data volume and excessive test power are two of the main concerns of VLSI testing. The “don’t-care” bits (also known as X-bits) in given test cube can be exploited for test data compression and/or test power reduction, and these techniques may contradict to each other because the very same X-bits are likely to be used for different optimization objectives. This paper proposes a capture-power-aware test compression scheme that is able to keep capture-power under a safe limit with low test compression ratio loss. Experimental results on benchmark circuits validate the effectiveness of the proposed solution.     

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don’t-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS’89 and ITC’99 benchmark circuits and on a number of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.

Test data compression using alternating variable run-length code

This paper presents a unified test data compression approach, which simultaneously reduces test data volume, scan power consumption and test application time for a system-on-a-chip (SoC). The proposed approach is based on the use of alternating variable run-length (AVR) codes for test data compression. A formal analysis of scan power consumption and test application time is presented. The analysis showed that a careful mapping of the don’t-cares in pre-computed test sets to 1s and 0s led to significant savings in peak and average power consumption, without requiring slower scan clocks. The proposed technique also reduced testing time compared to a conventional scan-based scheme. The alternating variable run-length codes can efficiently compress the data streams that are composed of both runs 0s and 1s. The decompression architecture was also presented in this paper. Experimental results for ISCAS'89 benchmark circuits and a production circuit showed that the proposed approach greatly reduced test data volume and scan power consumption for all cases.     

LZW压缩数据的不均一两分段误码保护编码

由T.A.Welch提出的LZW数据压缩方法已经被广泛地应用于文字压缩。然而，因为误码对压缩数据的危害很大，所以对压缩数据的纠错编码是十分重要且必不可少的。本文分析了误码对LZW压缩数据的影响，指出同样的误码对用于重建辞书的前一部分压缩数据的危害比对后面的其它数据的危害要严重得多，提出用一种不均一两分段误码保护编码方法，对用于重建辞书的前一部分压缩数据进行更好地保护。计算机模拟显示，该方法比传统的误码保护方法更有效。     

Enhancement of test data compression with multistage encoding

In this paper, we present two multistage compression techniques to reduce the test data volume in scan test applications. We have proposed two encoding schemes namely alternating frequency-directed equal-run-length (AFDER) coding and run-length based Huffman coding (RLHC). These encoding schemes together with the nine-coded compression technique enhance the test data compression ratio. In the first stage, the pre-generated test cubes with unspecified bits are encoded using the nine-coded compression scheme. Later, the proposed encoding schemes exploit the properties of compressed data to enhance the test data compression. This multistage compression is effective especially when the percentage of do not cares in a test set is very high. We also present the simple decoder architecture to decode the original data. The experimental results obtained from ISCAS'89 benchmark circuits confirm the average compression ratio of 74.2% and 77.5% with the proposed 9C-AFDER and 9C-RLHC schemes respectively.     

Test Data Compression for System-on-a-Chip using Count Compatible Pattern Run-Length Coding

The Count Compatible Pattern Run-Length (CCPRL) coding compression method is proposed to further improve the compression ratio. Firstly, a segment of pattern in the test set is retained. Secondly, don’t-care bits are filled so as to make subsequent patterns compatible with the retained pattern for as many times as possible until it can no longer be made compatible. Thirdly, the compatible patterns are represented by symbol “0” (equal) and symbol “1” (contrary) in the codeword. In addition, the number of consecutive compatible patterns is counted and expanded into binary which indicates when the codeword ends. At last, the six largest ISCAS’89 benchmark circuits verify the proposed method, the experimental results show that the average compression ratio achieved is up to 71.73 %.     

A new scheme of test data compression based on equal-run-length coding (ERLC)

A new scheme of test data compression based on run-length, namely equal-run-length coding (ERLC) is presented. It is based on both types of runs of 0's and 1's and explores the relationship between two consecutive runs. It uses a shorter codeword to represent the whole second run of two equal length consecutive runs. A scheme for filling the don't-care bits is proposed to maximize the number of consecutive equal-length runs. Compared with other already known schemes, the proposed scheme achieves higher compression ratio with low area overhead. The merits of the proposed algorithm are experimentally verified on the larger examples of the ISCAS89 benchmark circuits.     

A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding

A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing.