Embedded epitaxial growth of 4H-SiC on trenched substrates and pn junction characteristics

Embedded epitaxial growth has been carried out on 4H-SiC substrates with very narrow and deep trenches. The growth behavior near trenches is investigated under various growth conditions. Epitaxial growth on the sidewalls and at the bottom of trenches was enhanced under a low C/Si ratio which may bring a larger surface diffusion length of reactant species. Pn diodes were fabricated by embedded epitaxial growth on trenched substrates. The crystallographic orientation of the trenches has been found to be important for device fabrication.     

4H-SiC avalanche photodiode with multistep junction extensiontermination

4H-SiC avalanche photodiodes (APDs) are fabricated with a multistep junction termination extension. The leakage current density has been dramatically reduced to as low as 1 μA/cm² and photo-responsivity up to 10⁵ A/W has been achieved. The 4H-SiC APDs can run very stably at power densities up to 10⁴ W/cm²     

Positive temperature coefficient of breakdown voltage in 4H-SiC pnjunction rectifiers

It has been suggested that once silicon carbide (SiC) technology overcomes some crystal growth obstacles, superior SiC semiconductor devices would supplant silicon in many high-power applications. However, the property of positive temperature coefficient of breakdown voltage, a behavior crucial to realizing excellent power device reliability, has not been observed in 4H-SiC, which is presently the best-suited SiC polytype for power device implementation. This paper reports the first experimental measurements of stable positive temperature coefficient behavior observed in 4H-SiC pn junction rectifiers. This research indicates that robust 4H-SiC power devices with high breakdown reliability should be achievable after SiC foundries reduce material defects such as micropipes, dislocations, and deep level impurities     

Electrical characteristics of 4.5 kV implanted anode 4H-SiC p-i-njunction rectifiers

4500 V 4H-SiC p-i-n junction rectifiers with low on-state voltage drop (3.3-4.2 V), low reverse leakage current (3×10^-6 A/cm²), and fast switching (30-70 ns) have been fabricated and characterized. Forward current-voltage measurements indicate a minimum ideality factor of 1.2 which confirms a recombination process involving multiple energy levels. Reverse leakage current exhibits a square root dependence on voltage below the punchthrough voltage where leakage currents of less than 3×10^-6 A/cm² are measured. Reverse recovery measurements are presented which indicate the presence of recombination at the junction perimeter where a surface recombination velocity of 2-8×10⁵ cm/s is found. These measurements also indicate drift layer bulk carrier lifetimes ranging from 74 ns at room temperature to 580 ns at 250°C     

Partial dislocations and stacking faults in 4H-SiC PiN diodes

Using plan-view transmission electron microscopy (TEM), we have identified stacking faults (SFs) in 4H-SiC PiN diodes subjected to both light and heavy electrical bias. Our observations suggest that the widely expanded SFs seen after heavy bias are faulted dislocation loops that have expanded in response to strain of the 4H-SiC film, while faulted screw or 60° threading dislocations do not give rise to widely expanded SFs. Theoretical calculations show that the expansion of SFs depends on the Peach-Koehler (PK) forces on the partial dislocations bounding the SFs, indicating that strain plays a critical role in SF expansion.     

4 kV 4H-SiC epitaxial emitter bipolar junction transistors

In this paper, we present 4H-SiC bipolar junction transistors (BJTs) with open-base blocking voltage (BV/sub CEO/) of 4000 V, specific on-resistance (R/sub on,sp/) of 56 m/spl Omega/-cm/sup 2/, and common-emitter current gain /spl beta//spl sim/9. These devices are designed with interdigitated base and emitter fingers with multiple emitter stripes. We assess the impact of design (emitter stripe width and contact spacing) on device performance and also examine the effect of emitter contact resistance on the device forward conduction characteristics.     

Al+ and B+ implantations into 6H-SiC epilayers and application to pn junction diodes

Aluminum (Al) and boron (B) ion implantations at room temperature into n-type 6H-SiC epilayers have been investigated. Rutherford backscattering spectroscopy (RBS) channeling measurements revealed larger lattice damage in Al⁺ implantation at a given total implantation dose. A nearly perfect electrical activation ratio (>90%) could be attained by high-temperature annealing at 1600°C for Al⁺ and 1700°C for B⁺ implantations. Mesa pn junction diodes formed by either Al⁺ or B⁺ implantation with a 1×10¹⁴ cm⁻² dose exhibited high blocking voltages of 950∼1070 V, which are 80∼90% of the ideal value predicted for the diode structure. The forward current can clearly be divided into two components of diffusion and recombination currents. B⁺-implanted diodes showed higher breakdown voltage on average but poor forward conduction. Comparison of the performance of Al⁺ and B⁺-implanted diodes is discussed.     

1800 V NPN bipolar junction transistors in 4H-SiC

The first high voltage npn bipolar junction transistors (BJTs) in 4H-SiC have been demonstrated. The BJTs were able to block 1800 V in common emitter mode and showed a peak current gain of 20 and an on-resistance of 10.8 mΩ·cm² at room temperature (I_C=2.7 A @ V_CE=2 V for a 1 mm×1.4 mm active area), which outperforms all SiC power switching devices reported to date. Temperature-stable current gain was observed for these devices. This is due to the higher percent ionization of the deep level acceptor atoms in the base region at elevated temperatures, which offsets the effects of increased minority carrier lifetime at high temperatures. These transistors show a positive temperature coefficient in the on-resistance characteristics, which will enable easy paralleling of the devices     

4H-SiC normally-off vertical junction field-effect transistor with high current density

4H-silicon carbide (SiC) normally-off vertical junction field-effect transistor (JFET) is developed in a purely vertical configuration without internal lateral JFET gates. The 2.1-/spl mu/m vertical p/sup +/n junction gates are created on the side walls of deep trenches by tilted aluminum (Al) implantation. Normally-off operation with blocking voltage V/sub bl/ of 1 726 V is demonstrated with an on-state current density of 300 A/cm/sup 2/ at a drain voltage of 3 V. The low specific on-resistance R/sub on-sp/ of 3.6 m/spl Omega/cm/sup 2/ gives the V/sub bl//sup 2//R/sub on-sp/ value of 830 MW/cm/sup 2/, surpassing the past records of both unipolar and bipolar 4H-SiC power switches.     

Hollow-core screw dislocations in 6H-SiC single crystals: A test of Frank’s theory

Hollow-core screw dislocations, also known as “micropipes”, along the [0001] axis in 6H-SiC single crystals, have been studied by synchrotron white beam x-ray topography (SWBXT), scanning electron microscopy (SEM), and Nomarski optical microscopy (NOM). Using SWBXT, the magnitude of the Burgers vector of screw dislocations has been determined by measuring the following four parameters: (1) the diameter of dislocation images in back-reflection topographs; (2) the width of bimodal dislocation images in transmission topographs; (3) the magnitude of the tilt of lattice planes on both sides of dislocation core in projection topographs; and (4) the magnitude of the tilt of lattice planes in section topographs. The four methods show good agreement. SEM results reveal that micropipes emerge as holes on the as-grown surface, with their diameters ranging from about 0.1 to a few micrometers. Correlation between topographic images and SEM micrographs shows that micropipes are hollow-core screw dislocations with Burgers vector magnitudes from 2c to 7c (c is the lattice parameter along the [0001] axis). There is no empirical evidence that 1c dislocations have hollow cores. The Burgers vector magnitude of screw disloca-tions, b, and the diameter of associated micropipes, D, were fitted to Frank’s prediction for hollow-core screw dislocations: D = μb²/4π²γ, where μ is shear modulus, and γ is specific surface energy. Statistical analysis of the relationship between D and b² shows that it is approximately linear, and the constant γ/μ ranges from 1.1 × 10⁻³ to 1.6 × l0⁻³ nm.     

Time-Dependent Dielectric Breakdown of 4H-SiC MOS Capacitors and DMOSFETs

Time-dependent dielectric breakdown measurements were performed at 200 $^{ circ}hbox{C}$ on 4H-SiC MOS capacitors and vertical DMOSFETs with 50-nm-thick nitrided oxides in order to better understand the physical mechanisms of failure and to predict the component reliability. Oxide breakdown locations are shown to have no correlation to defects in the SiC epitaxial layer. Characterization of the electric-field acceleration of failures indicates that failure modes differ at low and high electric fields. Specifically, extrapolations from measurements at electric fields greater than 8.5 MV/cm predict anomalously high reliability at normal operating fields. Thus, we have shown that SiC MOS reliability characterization must ensure that electric field stresses be performed at low electric fields in order to accurately predict failure times.      

High current gain 4H-SiC npn bipolar junction transistors

The authors report a common emitter current gain /spl beta/ of 55 in npn epitaxial-emitter 4H-SiC bipolar junction transistors. The spacing between the p+ base contact implant and the edge of the emitter finger is critical in obtaining high-current gain. V/sub CEO/ of these devices is 500 V, and V/sub CBO/ is 700 V.     

Pulsed breakdown of 4H-SiC Schottky diodes terminated with a boron-implanted p-n junction

Pulsed reverse current-voltage characteristics have been measured in the breakdown region for 1-kV 4H-SiC Schottky diodes terminated with a boron-implanted p-n junction. It was shown that the dynamic breakdown voltage of the diodes increases as the pulses become shorter. Owing to the homogeneous avalanche formation at the edge of the guard p-n junction and to the high differential resistance in the breakdown region, the diodes sustain without degradation a pulsed reverse voltage substantially exceeding the static breakdown threshold. Characteristic features of the pulsed breakdown are considered in relation to the specific properties of the boron-implanted guard p-n junction.     

Long-term charge storage in GaP pn junction capacitors

pn junction storage capacitors are fabricated in GaP grown by gas source MBE. Storage times are thermally activated with activation energies between 1.10 and 1.38 eV. At 125 degrees C, the GaP recovery times are approximately 50 times longer than the best GaAs devices.<>     

Effect of basal plane dislocations on characteristics of diffused 4H-SiC p-i-n diodes

The effect of basal plane dislocations (BPDs) on the characteristics of diffused 4H-SiC p-i-n diodes was investigated. BPDs were intentionally introduced in the active regions of the device by means of epi-layer surface damage followed by high temperature annealing. Secondary electron microscopy images of the fabricated diodes clearly show the presence of the deliberately introduced BPDs. The current-voltage and electroluminescence spectra measurements did not reveal any noticeable effect of the BPDs on the electrical and optical properties of the diodes. All tested diodes with and without BPDs have no forward voltage drift during long-term on-state operation. A possible reason for stable device performance may be the immobilization of defects responsible for forward voltage drift due to interaction with the diffused dopants.     

Fabrication of self-aligned graded junction termination extensions with applications to 4H-SiC P-N diodes

The properties of SiC make this wide band-gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices, such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc., all of which require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power-handling capabilities. In this paper, we describe a technique for fabricating a graded junction termination extension (GJTE) that is effective and self-aligned, a feature that simplifies the implantation process during fabrication and, therefore, has the potential to reduce production costs. Implanted anode p-n diodes fabricated using this technique on 10-μm thick n⁻ epitaxial layer had a maximum breakdown voltage of 1830 V. This was comparable to the ideal parallel-plane breakdown of 1900 V predicted by numerical simulation.     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

Characteristics of planar n-p junction diodes made bydouble-implantations into 4H-SiC

Double implantation technology consisting of deep-range acceptor followed by shallow-range donor implantation was used to fabricate planar n⁺-p junction diodes in 4H-SiC. Either Al or B was used as the acceptor species and N as the donor species with all implants performed at 700°C and annealed at 1650°C with an AlN encapsulant. The diodes were characterized for their current-voltage (I-V) and capacitance-voltage (C-V) behavior over the temperature range 25°C-400°C, and reverse recovery transient behavior over the temperature range 25°C-200°C. At room temperature, the B-implanted diodes exhibited a reverse leakage current of 5×10^-8 A/cm² at a reverse bias of -20 V and a carrier lifetime of 7.4 ns     

Stability and 2-D Simulation Studies of Avalanche Breakdown in 4H-SiC DMOSFETs With JTE

In this paper, the stability of n-channel 4H-silicon carbide (SiC) DMOSFETs with junction termination extension (JTE) was assessed by measuring the breakdown voltage (BV) of these devices before and after bias stress at a high temperature. The BV slumped after the DMOSFET was bias stressed at 1200 V for 2 h at 175degC, and the slumped BV dynamically recovered to the prestress value during the poststress period. Computer simulation suggests that the BV slump and its recovery are dominated by the positive charge trapping/detrapping phenomena at the SiC/fleld oxide interface in the JTE structure, rather than the trapping/detrapping at the SiC/gate oxide interface in the cell structure. A positive interface charge of approximately one-third of the sheet dopant concentration of the JTE region, lowers BV by 150 V, which is the typical measured BV slump of the DMOSFETs of this paper.     

Physical phenomena affecting performance and reliability of 4H-SiC bipolar junction transistors

The silicon carbide bipolar junction transistor (BJT) is attractive for use in high-voltage switching applications offering high-voltage blocking characteristics, low switching losses, and is capable of operating at current densities exceeding 300 A/cm². However, performance reliability issues such as degradation of current gain and on-resistance currently prohibit commercial production of 4H-SiC BJTs. This paper examines the physical mechanisms responsible for this degradation as well as the impact that these physical phenomena have on device performance. Results were obtained through the examination of several types of N-P-N BJT structures using various fabrication methodologies. Electron-beam induced current (EBIC) and potassium hydroxide (KOH) etching were used to characterize defect content in the material, before and after device current stress, when possible. It was found that Shockley stacking faults (stress-induced structures) associated with the forward voltage drift phenomenon in SiC bipolar diodes, also play a major role in the reduction of gain and an increase of on-resistance of the BJTs. However, results from some devices suggest that additional processes at the device periphery (edge of the emitter) may also contribute to degradation in electrical performance. Hence, it is essential that the sources of electrical degradation, identified in this paper, be eliminated for SiC BJTs to be viable for commercial scale production.