Suppression of high-resistance phases of Ni silicide by Se passivation of Si(100)

High-resistance phases of Ni-rich Ni silicide are formed on Si(100) below 400/spl deg/C, while high-resistance phases of Si-rich Ni silicide are formed above 600/spl deg/C. The desired low-resistance NiSi is formed between 400/spl deg/C and 600/spl deg/C. In this paper, the authors report the suppression of high-resistance phases of Ni silicide by passivating the Si(100) surface with a monolayer of Se. A 500-/spl Aring/ Ni on n-type low 10/sup 15/ cm/sup -3/ doped Si(100) wafers, passivated with Se, shows a sheet resistance of /spl sim/2.55 /spl Omega//square upon annealing between 200/spl deg/C and 500/spl deg/C, while the sheet resistance of the 500-/spl Aring/ Ni on identical wafers without Se-passivation jumps to /spl sim/7.92 /spl Omega//square between 300/spl deg/C and 350/spl deg/C. Between 600/spl deg/C and 700/spl deg/C, the sheet resistance of the Se-passivated samples is /spl sim/ 10% lower than that of the control samples. Transmission electron microscopy, X-ray diffraction, and X-ray photoelectron spectroscopy all confirm that the suppression of high-resistance Ni silicides below 500/spl deg/C is attributed to the suppression of silicidation and above 600/spl deg/C to the delay in Si-rich Ni silicide formation at the Ni/Se-passivated Si(100) interface.     

Very large temperature-induced absorptive loss in high Te-containing chalcogenide fibers

The change in the absorption loss relative to room temperature of the infrared (IR)-transmitting Ge/sub 15/As/sub 35/Se/sub (50-x)/Te/sub x/ glass fibers in the temperature range of -110/spl deg/C/spl les/T/spl les/110/spl deg/C was investigated. The attenuation increased significantly at T/spl ges/40/spl deg/C. This is mainly attributed to thermally activated free carriers associated with the semimetallic character of the Te atom. For /spl lambda//spl les/4.2 /spl mu/m, the loss due to electronic and free-carrier absorption was strongly affected by temperature. In the wavelength region of 5-11 /spl mu/m, the loss was mainly due to free-carrier absorption. Beyond /spl lambda//spl ges/11 /spl mu/m, multiphonon absorption dominated the loss spectrum at T/spl les/60/spl deg/C while free-carrier absorption contributed mainly to the total loss at T/spl ges/80/spl deg/C.     

Microwave Characterization of Partially Magnetized Ferrites

In order to assist the microwave engineer in predicting the performance of partially magnetized devices, we have characterized the microwave permeability of partially magnetized materials. The real part of the tensor permeability elements, /spl mu/, /spl kappa/, and /spl mu//sub z/, depends primarily on the parameters /spl gamma/4/spl pi/M//spl omega/ and /spl gamma/4/spl pi/M/sub s/ / /spl omega/. Empirical formulas have been developed which show the dependence. At frequencies sufficiently below /spl omega/ = /spl pi/4/spl pi/M/sub s/, the loss can be characterized by the value of /spl mu/' at 4/spl pi/M = 0./spl mu/, /spl kappa/, and /spl mu//sub z/ depend weakly on composition, whereas /spl mu/' (4/spl pi/M = 0) does depend upon the chemical composition.     

Electrical characteristics and lifetimes of microdischarge devices having thin dielectric films of aluminum oxide,boron nitride, or barium titanate

The electrical (V-I) characteristics, radiative efficiencies, and lifetimes of Ni screen/dielectric/Ni microdischarge devices, having overall thicknesses as small as <100 /spl mu/m and cylindrical microchannels 50-150 /spl mu/m in diameter, are investigated for Al/sub 2/O/sub 3/, BN, and BaTiO/sub 3/ dielectric films that are 120 or 200 /spl mu/m, 30 /spl mu/m, and 5 /spl mu/m in thickness, respectively. Having dielectrics fabricated by sol-gel processes or colloidal deposition and operated with Ne gas pressures between 300 and 1200 Torr (300K), these devices operate at voltages as low as /spl sim/93 V (100 /spl mu/m dia. BaTiO/sub 3/ device), and exhibit exceptional stability and lifetimes. After 100 h of continuous operation, a Ni screen/30 /spl mu/m BN/Ni device operating in 700 Torr Ne (static gas fill) at 100 V produces /spl sim/98% of its initial radiant output.     

Improved-performance, InGaAs/InGaAsP (/spl lambda/=980 nm) asymmetric broad-waveguide diode lasers via waveguide-core doping

Doping the waveguide core (p=2/spl times/10/sup 17/ cm/sup -1/) in asymmetric-waveguide InGaAs/InGaAsP, two-quantum-well diode lasers (/spl lambda/=980 nm) raises the injection efficiency to 90% and decreases the threshold-current density, J/sub th/. For 2 mm long, 100 /spl mu/m wide stripe, uncoated chips J/sub th/ decreases from /spl sim/188 A/cm/sup 2/ to /spl sim/150 A/cm/sup 2/. High characteristic temperatures for J/sub th/ and the slope efficiency are obtained: T/sub 0/=215K and T/sub 1/=600K.     

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

High-temperature thermal stability performance in /spl delta/-doped In/sub 0.425/Al/sub 0.575/As--In/sub 0.65/Ga/sub 0.35/As metamorphic HEMT

We report, to our knowledge, the best high-temperature characteristics and thermal stability of a novel /spl delta/-doped In/sub 0.425/Al/sub 0.575/As--In/sub 0.65/Ga/sub 0.35/As--GaAs metamorphic high-electron mobility transistor. High-temperature device characteristics, including extrinsic transconductance (g/sub m/), drain saturation current density (I/sub DSS/), on/off-state breakdown voltages (BV/sub on//BV/sub GD/), turn-on voltage (V/sub on/), and the gate-voltage swing have been extensively investigated for the gate dimensions of 0.65/spl times/200 /spl mu/m/sup 2/. The cutoff frequency (f/sub T/) and maximum oscillation frequency (f/sub max/), at 300 K, are 55.4 and 77.5 GHz at V/sub DS/=2 V, respectively. Moreover, the distinguished positive thermal threshold coefficient (/spl part/V/sub th///spl part/T) is superiorly as low as to 0.45 mV/K.     

ScN/sub x/ gate on atomic layer deposited HfO/sub 2/ and effect of high-pressure wet post deposition annealing

For nMOS devices with HfO/sub 2/, a metal gate with a very low workfunction is necessary. In this letter, the effective workfunction (/spl Phi//sub m,eff/) values of ScN/sub x/ gates on both SiO/sub 2/ and atomic layer deposited (ALD) HfO/sub 2/ are evaluated. The ScN/sub x//SiO/sub 2/ samples have a wide range of /spl Phi//sub m,eff/ values from /spl sim/ 3.9 to /spl sim/ 4.7 eV, and nMOS-compatible /spl Phi//sub m,eff/ values can be obtained. However, the ScN/sub x/ gates on conventional post deposition-annealed HfO/sub 2/ show a relatively narrow range of /spl Phi//sub m,eff/ values from /spl sim/ 4.5 to /spl sim/ 4.8 eV, and nMOS-compatible /spl Phi//sub m,eff/ values cannot be obtained due to the Fermi-level pinning (FLP) effect. Using high-pressure wet post deposition annealing, we could dramatically reduce the extrinsic FLP. The /spl Phi//sub m,eff/ value of /spl sim/ 4.2 eV was obtained for the ScN/sub x/ gate on the wet-treated HfO/sub 2/. Therefore, ScN/sub x/ metal gate is a good candidate for nMOS devices with ALD HfO/sub 2/.     

Design optimization of stacked layer dielectrics for minimum gate leakage currents

An effective model to evaluate the leakage currents for different stacked gates deep submicron MOS transistors is presented. For a given equivalent oxide thickness of a stacked gate, the gate leakage current decreases with an increase of high-k dielectric thickness or a decrease of interlayer thickness. Turning points at high gate biases of the I–V curves are observed for Si₃N₄/SiO₂, Ta₂O₅/SiO₂, Ta₂O₅/SiO_2−yN_y, Ta₂O₅/Si₃N₄, and TiO₂/SiO₂ stacked gates except for Al₂O₃/SiO₂ structure. Design optimization for the stacked gate architecture to obtain the minimum gate leakage current is evaluated.     

An efficient numerical approach, for determining the dispersioncharacteristics of dual-mode elliptical-core optical fibers

Based on vectorial formulations which combine the surface integral equation method and the finite-element method, a novel numerical approach is proposed for calculating the dispersion coefficients of dual-mode elliptical-core fibers with arbitrary refractive index profiles. By differentiating the original formulations involving the propagation constant β and the guided mode fields H_x and H_y once and twice with respect to the normalized frequency V, the new formulations for {dβ/dV, dH_x/dV, dH_y/dV} and for {d²β/dV², d² H_x/dV², d²H_y/dV² } are obtained respectively. Once {β, H_x, H_y } is solved through the eigenvalue procedure which dominates the computing time, only a few matrix manipulations are required to obtain {dβ/dV, dH_x/dV, dH_y/dV} and {d²β/dV², d²H_x/dV² , d²H_y/dV²}. Some numerical examples are examined to see the influence of different refractive index distributions with dips on the dispersions of the four nondegenerate LP ₁₁ modes for elliptical-core fibers     

On the filtering problem for stationary random /spl Zopf//sup 2/-fields

It is shown that whenever a stationary random field (Z/sub n,m/)/sub n,m/spl isin/z/ is given by a Borel function f:/spl Ropf//sup z/ /spl times/ /spl Ropf//sup z/ /spl rarr/ /spl Ropf/ of two stationary processes (X/sub n/)/sub n/spl isin/z/ and (Y/sub m/)/sub m/spl isin/z/ i.e., then (Z/sub n, m/) = (f((X/sub n+k/)/sub k/spl epsi/z/, (Y/sub m + /spl lscr// )/sub /spl lscr/ /spl epsi/z/)) under a mild first coordinate univalence assumption on f, the process (X/sub n/)/sub n/spl isin/z/ is measurable with respect to (Z/sub n,m/)/sub n,m/spl epsi/z/ whenever the process (Y/sub m/)/sub m/spl isin/z/ is ergodic. The notion of universal filtering property of an ergodic stationary process is introduced, and then using ergodic theory methods it is shown that an ergodic stationary process has this property if and only if the centralizer of the dynamical system canonically associated with the process does not contain a nontrivial compact subgroup.     

交换超立方网络的(t, k)故障诊断度研究

故障诊断是网络系统修复的一个重要环节,PMC诊断模型是一种简单、易于理解的故障诊断模型。通过对以交换超立方网 为拓扑模型的多处理器系统进行结构分析,给出了该网络系统的一般化的故障诊断方法——(t,k)诊断方法,证明了在PMC模型下交换超立方网络 是 可诊断的,且是条件 可诊断的。结果表明,交换超立方网的(t,k)诊断度 大于其传统诊断度s+1,条件(t,k)诊断度 大于其传统条件诊断度4s?3。这些结果为交换超立方网络的故障诊断提供了重要的理论依据。     

Evidence and understanding of ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors outperforming sandwich counterparts

Metal-insulator-metal capacitors with atomic-layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminated and sandwiched dielectrics have been compared, for the first time, for analog circuit applications. The experimental results indicate that significant improvements can be obtained using the laminated dielectrics, including an extremely low leakage current of 1/spl times/10/sup -9/ A/cm/sup 2/ at 3.3V and 125/spl deg/C, a high breakdown electric field of /spl sim/3.3MV/cm at 125/spl deg/C, good polarity-independent electrical characteristics, while retaining relatively high capacitance density of 3.13 fF//spl mu/m/sup 2/ as well as voltage coefficients of capacitance as low as -80 ppm/V and 100 ppm/V/sup 2/ at 100 kHz. The underlying mechanism is likely due to alternate insertions of Al/sub 2/O/sub 3/ layers that reduce the thickness of each HfO/sub 2/ layer, hereby efficiently inhibiting HfO/sub 2/ crystallization, and blocking extensions of grain boundary channels from top to bottom as well as to achieve good interfacial quality.     

Equivalent Circuit of the Bolometer Detector

A small-signal dynamic equivalent circuit is established for the output voltage of a dc-biased bolometer (barretter) detector. The circuit consists of a voltage generator /spl upsi//sub g/, whose output is an undistorted replica of the incident RF-power modulation envelope, followed by a series resistor R/sub 1/ of dynamic origin, a shunt capacitor C that represents heat storage in the bolometer wire, and a series resistor R/sub 0/ equal to the dc resistance, usually 200 ohms. The resistance R/sub 1/ is independent of signal level, and is typically about 220 ohms for an 8.75-mA bolometer and about 120 ohms for a 4.5-mA bolometer. At a modulation frequency f/sub m/ near 0 Hz, the equivalent audio source impedance of the bolometer is R/sub 1/ +R/sub 0/. The common belief that the source impedance is R/sub 0/ in the weak-signal case is, therefore, refuted. Formulas are derived giving v/sub g/ / /P/sub RF/ and R/sub 1/ as functions of basic, easily determined bolometer parameters. The time constant for open-circuit load is /spl tau//sub oc/= R/sub 1/C, where /spl tau//sub oc/ is determined best by measurement, since catalog values of /spl tau//sub oc/ often are seriously in error. The capacitance is C=/spl tau//sub oc/ / /R/sub 1/. With one type of bolometer /spl tau//sub oc/ measures about 110 /spl mu/s, while various catalogs state values of 250 to 350 /spl mu/s. The equivalent circuit is confirmed quantitatively by measurements of output voltage and source impedance versus modulation frequency.     

High-performance InGaP/GaAs HBTs with compositionally graded bases grown by solid-source MBE

N-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with compositionally graded In/sub x/Ga/sub 1-x/As (Be doped) bases have been successfully grown by solid-source molecular beam Epitaxy (SSMBE) using a gallium phosphide (GaP) decomposition source. In this paper, the dc and RF characteristics of HBTs with different indium mole fractions in the graded In/sub x/Ga/sub 1-x/As base (x:0 /spl rarr/ ;0.1 and x:0 /spl rarr/ 0.05) are measured to investigate optimum-grading profiles. The measured average current gains, /spl beta/s of a control sample, a 10% graded-base sample and a 5% graded-base sample, are 162, 397 and 362, respectively. To our knowledge, these current gains are the highest values ever reported in compositionally graded-base InGaP/GaAs HBTs with a base sheet resistance R/sub sh/ of /spl sim/200 /spl Omega//sq establishing a new benchmark for InGaP/GaAs HBTs. Furthermore, these compositionally graded-base HBTs show higher unity current/gain cutoff frequency, f/sub T/ and maximum oscillation frequency, f/sub max/. Compared to the control sample with the same base thickness, the base transit time /spl tau//sub B/ of the graded sample is reduced by /spl sim/15% to /spl sim/20% by the induced built-in potential, resulting in an increase of f/sub max/ from 16 to 18.5 GHz in a device with an emitter size of 10/spl times/10 /spl mu/m/sup 2/. Additionally, for the 5% graded-base sample, with a 5/spl times/5 /spl mu/m/sup 2/ emitter region, f/sub T/ and f/sub max/ are 16.3 and 33.8 GHz, respectively, under low-level collector current. These results demonstrate that InGaP/GaAs HBTs with In/sub x/Ga/sub 1-x/As graded-base layers (x:0 /spl rarr/ 0.05) have the potential for high-speed analogue to digital converters.     

Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO/sub 2/-SiO/sub 2/) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO/sub 2/ into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5 V operation/tolerance). Results show that CVD HfO/sub 2/-SiO/sub 2/ stacked gate dielectric (EOT =6.2 nm) exhibits lower leakage current than that of SiO/sub 2/ (EOT =5.7 nm) by a factor of /spl sim/10/sup 2/, with comparable interface quality (D/sub it//spl sim/1/spl times/10/sup 10/ cm/sup -2/eV/sup -1/). The presence of negative fixed charge is observed in the HfO/sub 2/-SiO/sub 2/ gate stack. In addition, the addition of HfO/sub 2/ on SiO/sub 2/ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in the HfO/sub 2/-SiO/sub 2/ gate stack. Furthermore, the HfO/sub 2/-SiO/sub 2/ gate stack shows longer time to breakdown T/sub BD/ than SiO/sub 2/ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V/sub t/ stability (charge trapping under stress) can be met and the negative fixed charge eliminated.     

SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

Low-frequency noise in TaSiN/HfO/sub 2/ nMOSFETs and the effect of stress-relieved preoxide interfacial layer

Low-frequency noise characteristics are reported for TaSiN-gated n-channel MOSFETs with atomic-layer deposited HfO/sub 2/ on thermal SiO/sub 2/ with stress-relieved preoxide (SRPO) pretreatment. For comparison, control devices were also included with chemical SiO/sub 2/ resulting from standard Radio Corporation of America clean process. The normalized noise spectral density values for these devices are found to be lower when compared to reference poly Si gate stack with similar HfO/sub 2/ dielectric. Consequently, a lower oxide trap density of /spl sim/4/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ is extracted compared to over 3/spl times/10/sup 18/ cm/sup -3/eV/sup -1/ values reported for poly Si devices indicating an improvement in the high-/spl kappa/ and interfacial layer quality. In fact, this represents the lowest trap density values reported to date on HfO/sub 2/ MOSFETs. The peak electron mobility measured on the SRPO devices is over 330 cm/sup 2//V/spl middot/s, much higher than those for equivalent poly Si or metal gate stacks. In addition, the devices with SRPO SiO/sub 2/ are found to exhibit at least /spl sim/10% higher effective mobility than RCA devices, notwithstanding the differences in the high-/spl kappa/ and interfacial layer thicknesses. The lower Coulomb scattering coefficient obtained from the noise data for the SRPO devices imply that channel carriers are better screened due to the presence of SRPO SiO/sub 2/, which, in part, contributes to the mobility improvement.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.