Multi-Channel Field-Effect Transistor (MCFET)—Part I: Electrical Performance and Current Gain Analysis

Multi-Channel Field-Effect Transistor (MCFET) structures with ultralow $I_{ rm OFF}$ (16 $hbox{pA}/muhbox{m}$) and high $I_{rm ON}$ (N: 2.27 $ hbox{mA}/muhbox{m}$ and P: 1.32 $hbox{mA}/muhbox{m}$ ) currents are obtained on silicon on insulator (SOI) with a high-$ kappa$/metal gate stack, satisfying both low-standby-power and high-performance requirements. The experimental current gain of the MCFET structure is compared with that of an optimized planar FD-SOI reference with the same high-$kappa$/metal gate stack and is quantitatively explained by an analytical model. Transport properties are investigated, and the specific MCFET electrostatic properties are evidenced, in particular a higher $V_{rm Dsat}$ for MCFETs compared with the planar reference. Finally, through 3-D numerical simulations correlated with specific characterizations, the influence of the channel width on the electrical performance is analyzed. For narrow devices, the parasitic bottom channel increases the total drain current of the MCFET structure without degrading the electrostatic integrity.      

High-Density and Low-Leakage-Current MIM Capacitor Using Stacked $hbox{TiO}_{2}/hbox{ZrO}_{2}$ Insulators

We have fabricated high-$kappa hbox{Ni}/hbox{TiO}_{2}/hbox{ZrO}_{2}/ hbox{TiN}$ metal–insulator–metal (MIM) capacitors. A low leakage current of $hbox{8} times hbox{10}^{-8} hbox{A/cm}^{2}$ at 125 $^{circ}hbox{C}$ was obtained with a high 38- $hbox{fF}/muhbox{m}^{2}$ capacitance density and better than the $hbox{ZrO}_{2}$ MIM capacitors. The excellent device performance is due to the lower electric field in 9.5-nm-thick $hbox{TiO}_{2}/ hbox{ZrO}_{2}$ devices to decrease the leakage current and to a higher $kappa$ value of 58 for $ hbox{TiO}_{2}$ as compared with that of $hbox{ZrO}_{2}$ to preserve the high capacitance density.      

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

Electrical Properties of $hbox{Bi}_{5}hbox{Nb}_{3} hbox{O}_{15}$ Thin Film Grown on $hbox{TiN}/hbox{SiO}_{2}/ hbox{Si}$ at Room Temperature for Metal–Insulator–Metal Capacitors

Buckling was observed in $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}$ (BiNbO) films grown on $hbox{TiN}/hbox{SiO}_{2}/hbox{Si}$ at 300 $^{circ}hbox{C}$ but not in films grown at room temperature and annealed at 350 $^{circ}hbox{C}$. The 45-nm-thick films showed a high capacitance density and a low dissipation factor of 8.81 $hbox{fF}/muhbox{m}^{2}$ and 0.97% at 100 kHz, respectively, with a low leakage current density of 3.46 $hbox{nA}/hbox{cm}^{2}$ at 2 V. The quadratic and linear voltage coefficients of capacitance of this film were 846 $hbox{ppm}/hbox{V}^{2}$ and 137 ppm/V, respectively, with a low temperature coefficient of capacitance of 226 $hbox{ppm}/^{circ}hbox{C}$ at 100 kHz. This suggests that a BiNbO film grown on a $hbox{TiN}/ hbox{SiO}_{2}/hbox{Si}$ substrate is a good candidate material for high-performance metal–insulator–metal capacitors.      

0.8-V Supply Voltage Deep-Submicrometer Inversion-Mode $hbox{In}_{0.75}hbox{Ga}_{0.25}hbox{As}$ MOSFET

We report the experimental demonstration of deep-submicrometer inversion-mode $hbox{In}_{0.75}hbox{Ga}_{0.25}hbox{As}$ MOSFETs with ALD high- $k$ $hbox{Al}_{2}hbox{O}_{3}$ as gate dielectric. In this letter, n-channel MOSFETs with 100–200-nm-long gates have been fabricated. At a supply voltage of 0.8 V, the fabricated devices with 200–130-nm-long gates exhibit drain currents of 232–440 $muhbox{A}/muhbox{m}$ and transconductances of 538–705 $muhbox{S}/muhbox{m}$. The 100-nm device has a drain current of 801 $muhbox{A}/muhbox{m}$ and a transconductance of 940 $muhbox{S}/muhbox{m}$. However, the device cannot be pinched off due to severe short-channel effect. Important scaling metrics, such as on/off current ratio, subthreshold swing, and drain-induced barrier lowering, are presented, and their relations to the short-channel effect are discussed.      

A Center-Offset Polycrystalline-Silicon Thin-Film Transistor With ${rm n}^{+}$ Amorphous-Silicon Contacts

We have studied a bottom-gate polycrystalline-silicon thin-film transistor (poly-Si TFT) with amorphous-silicon (a-Si) ${rm n}^{+}$ contacts and center-offset gated structure, where intrinsic poly-Si is used in the center-offset region. The fabrication process is compatible with the conventional a-Si TFT with addition of thermal annealing for crystallization of a-Si. The bottom-gate poly-Si TFT with a 5-$muhbox{m}$ offset length exhibited a field-effect mobility of 18.3 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ and minimum OFF-state current of $hbox{2.79} times hbox{10}^{-12} hbox{A}/muhbox{m}$ at $V_{rm ds} = hbox{5} hbox{V}$. The leakage currents are two orders of magnitude lower than those of a nonoffset TFT with mobility drop from 23.8 to 18.3 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$.      

A Comparative NBTI Study of $hbox{HfO}_{2}$, $hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{rm DLIN}$ Technique

The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in $hbox{HfO}_{2}/hbox{TiN}$, $ hbox{HfSiO}_{x}/hbox{TiN}$, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly $I_{rm DLIN}$ technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, $hbox{HfO}_{2}$ devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and $hbox{HfSiO}_{x}$ devices. $hbox{HfSiO}_{x}$ shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to $hbox{HfO}_{2}$, which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between $ hbox{HfSiO}_{x}$ and $hbox{HfO}_{2}$ can be attributed to differences in N density in the $hbox{SiO}_{2}$ IL of these devices.      

1580-V–40-$hbox{m}Omegacdot hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC $(hbox{000}bar{hbox{1}})$

Double-reduced-surface-field (RESURF) MOSFETs with $hbox{N}_{2}hbox{O}$ -grown oxides have been fabricated on the 4H-SiC $(hbox{000} bar{hbox{1}})$ face. The double-RESURF structure is effective in reducing the drift resistance, as well as in increasing the breakdown voltage. In addition, by utilizing the 4H-SiC $(hbox{000}bar{hbox{1}})$ face, the channel mobility can be increased to over 30 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, and hence, the channel resistance is decreased. As a result, the fabricated MOSFETs on 4H-SiC $( hbox{000}bar{hbox{1}})$ have demonstrated a high breakdown voltage $(V_{B})$ of 1580 V and a low on-resistance $(R_{rm ON})$ of 40 $hbox{m}Omega cdothbox{cm}^{2}$. The figure-of-merit $(V_{B}^{2}/R_{rm ON})$ of the fabricated device has reached 62 $hbox{MW/cm}^{2}$, which is the highest value among any lateral MOSFETs and is more than ten times higher than the “Si limit.”      

Strain Enhanced nMOS Using In Situ Doped Embedded $hbox{Si}_{1 - x}hbox{C}_{x}$ S/D Stressors With up to 1.5% Substitutional Carbon Content Grown Using a Novel Deposition Process

This letter reports on the implementation of high carbon content and high phosphorous content $hbox{Si}_{1 - x}hbox{C}_{x}$ layers in the source and drain regions of n-type MOSFET in a 65-nm-node integration scheme. The layers were grown using a novel epitaxial process. It is shown that by implementing stressors with $x approx hbox{0.01}$ , nMOSFET device performance is enhanced by up to 10%, driving 880 $mu hbox{A}/muhbox{m}$ at 1-V $V_{rm DD}$. It is also demonstrated that the successful implementation of $hbox{Si}_{1 - x} hbox{C}_{x}$ relies on the careful choice of integration and epitaxial layer parameters. There is a clear impact of the postepitaxial implantation and thermal treatment on the retained substitutional C content $([C_{rm sub}])$. Furthermore, adding a Si capping layer on top of the $hbox{Si}_{1 - x}hbox{C}_{x}$, greatly improves upon the stressors' stability during the downstream processing and the silicide sheet resistance.      

Extraction of the Effective Mobility of $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs

The extraction of the effective mobility on $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ metal–oxide–semiconductor field-effect transistors (MOSFETs) is studied and shown to be greater than 3600 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$. The removal of $C_{rm it}$ response in the split $C$–$V$ measurement of these devices is crucial to the accurate analysis of these devices. Low-temperature split $C$–$V$ can be used to freeze out the $D_{rm it}$ response to the ac signal but maintain its effect on the free carrier density through the substrate potential. Simulations that match this low-temperature data can then be “warmed up” to room temperature and an accurate measure of $Q_{rm inv}$ is achieved. These results confirm the fundamental performance advantages of $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs.      

Comparative Study of the Low-Frequency-Noise Behaviors in a-IGZO Thin-Film Transistors With $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ Gate Dielectrics

A comparative study is made of the low-frequency noise (LFN) in amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ gate dielectrics. The LFN is proportional to $hbox{1}/f^{gamma}$, with $gamma sim hbox{1}$ for both devices, but the normalized noise for the $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ device is two to three orders of magnitude lower than that for the $hbox{Al}_{2} hbox{O}_{3}$ device. The mobility fluctuation is the dominant LFN mechanism in both devices, but the noise from the source/drain contacts becomes comparable to the intrinsic channel noise as the gate overdrive voltage increases in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices. The $hbox{SiN}_{x}$ interfacial layer is considered to be very effective in reducing LFN by suppressing the remote phonon scattering from the $hbox{Al}_{2}hbox{O}_{3}$ dielectric. Hooge's parameter is extracted to $sim !!hbox{6.0} times hbox{10}^{-3}$ in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices.      

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

Effective Modulation of Quadratic Voltage Coefficient of Capacitance in MIM Capacitors Using $hbox{Sm}_{2}hbox{O}_{3}/hbox{SiO}_{2}$ Dielectric Stack

We report the first demonstration of metal–insulator–metal (MIM) capacitors with $hbox{Sm}_{2}hbox{O}_{3}/hbox{SiO}_{2}$ stacked dielectrics for precision analog circuit applications. By using the “canceling effect” of the positive quadratic voltage coefficient of capacitance (VCC) of $hbox{Sm}_{2}hbox{O}_{3}$ and the negative quadratic VCC of $hbox{SiO}_{2}$, MIM capacitors with capacitance density exceeding 7.3 $hbox{fF}/muhbox{m}^{2}$ , quadratic VCC of around $-hbox{50} hbox{ppm/V}^{2}$ , and leakage current density of $hbox{1} times hbox{10}^{-7} hbox{A/cm}^{2}$ at $+$3.3 V are successfully demonstrated. The obtained capacitance density and quadratic VCC satisfy the technical requirements specified in the International Technology Roadmap for Semiconductors through the year 2013 for MIM capacitors to be used in precision analog circuit applications.      

Low Turn-On Voltage and High-Current $hbox{InP}/ hbox{In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}/hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Double Heterojunction Bipolar Transistors

We report on the dc and microwave characteristics of an $ hbox{InP/In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}/hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ double heterojunction bipolar transistor grown by solid-source molecular beam epitaxy. The pseudomorphic $hbox{In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}$ base reduces the conduction band offset $Delta E_{C}$ at the emitter/base junction and the base band gap, which leads to a very low $V_{rm BE}$ turn-on voltage of 0.35 V at 1 $hbox{A/cm}^{2}$ . A current gain of 125 and a peak $f_{T}$ of 238 GHz have been obtained on the devices with an emitter size of $hbox{1}times hbox{10} muhbox{m}^{2}$, suggesting that a high collector average velocity and a high current capability are achieved due to the type-II lineup at the InGaAsSb/InGaAs base/collector junction.      

Positive Bias Temperature Instability (PBTI) Characteristics of Contact-Etch-Stop-Layer-Induced Local-Tensile-Strained $hbox{HfO}_{2}$ nMOSFET

The positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer (CESL)-strained $hbox{HfO}_{2}$ nMOSFET are thoroughly investigated. For the first time, the effects of CESL on an $hbox{HfO}_{2}$ dielectric are investigated for PBTI characteristics. A roughly 50% reduction of $V_{rm TH}$ shift can be achieved for the 300-nm CESL $hbox{HfO}_{2}$ nMOSFET after 1000-s PBTI stressing without obvious $ hbox{HfO}_{2}/hbox{Si}$ interface degradation, as demonstrated by the negligible charge pumping current increase ($≪$ 4%). In addition, the $hbox{HfO}_{2}$ film of CESL devices has a deeper trapping level (0.83 eV), indicating that most of the shallow traps (0.75 eV) in as-deposited $ hbox{HfO}_{2}$ film can be eliminated for CESL devices.      

0.13 $mu$ m SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications

This paper presents a complete 0.13$,muhbox{m}$ SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz ${rm f}_{rm T}/{rm f}_{rm MAX}$) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 $hbox{fF}/muhbox{m}^{2}$ high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models.      

High-Performance Poly-Silicon TFTs Using a High-$k$ $hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is proposed for the first time. Compared to TFTs with a $hbox{Pr}_{2}hbox{O}_{3}$ gate dielectric, the electrical characteristics of poly-Si TFTs with a $hbox{PrTiO}_{3}$ gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher $I_{rm on}/I_{rm off}$ current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.      

Improved Stress Reliability of Analog Metal–Insulator–Metal Capacitors Using $hbox{TiO}_{2}/hbox{ZrO}_{2}$ Dielectrics

We have studied the stress reliability of high-$kappa$ $hbox{Ni/TiO}_{2}/hbox{ZrO}_{2}/hbox{TiN}$ metal–insulator–metal capacitors under constant-voltage stress. The increasing $hbox{TiO}_{2}$ thickness on $hbox{ZrO}_{2}$ improves the 125-$^{circ}hbox{C}$ leakage current, capacitance variation $(Delta C/C)$, and long-term reliability. For a high density of 26 $hbox{fF}/mu hbox{m}^{2}$ , good extrapolated ten-year reliability of small $Delta C/ break C sim hbox{0.71}%$ is obtained for the $ hbox{Ni/10-nm-}hbox{TiO}_{2}/hbox{6.5-nm-} hbox{ZrO}_{2}/break hbox{TiN}$ device at 2.5-V operation.      

Effect of Oxygen Pressure on the Electrical Properties of $hbox{Bi}_{5} hbox{Nb}_{3}hbox{O}_{15}$ Films Grown by RF Magnetron Sputtering

$hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15} (hbox{B}_{5}hbox{N}_{3})$ films grown under a low oxygen partial pressure (OP) of 1.7 mtorr showed a high leakage current density of 0.1 $hbox{A/cm}^{2}$ at 1.0 MV/cm. However, the leakage current density decreased with increasing OP to a minimum of $hbox{5.8} times hbox{10}^{-9} hbox{A/cm}^{2}$ for the film grown under 5.1 mtorr due to the decreased number of oxygen vacancies. This film also showed an improved breakdown field of 2.2 MV/cm and a large capacitance density of 24.9 $hbox{fF}/muhbox{m}^{2}$. The electrical properties of the film, however, deteriorated with a further increase in OP, which is probably due to the formation of oxygen interstitial ions. Therefore, superior electrical properties for the $ hbox{B}_{5}hbox{N}_{3}$ film can be obtained by careful control of OP.