New approach to model nonquasi-static (NQS) effects for MOSFETs. Part I: Large-signal analysis

This paper presents a new nonquasi-static (NQS) model for the MOSFET. The model is derived from physics and only relies on the very basic approximation needed for a charge-based model. To derive the model, a popular variational technique named Galerkin's Method has been used. The model proves to be very accurate even for extremely fast changes in the bias voltages. Simulation results show a very good match even when the rise time of the applied signal is smaller than the transit time of the device.     

A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect

In analog circuit design an important parameter,from the perspective of superior device performance,is linearity.The DG MOSFET in asymmetric mode operation has been found to present a better linearity.In addition to that it provides,at the discretion of analog circuit designer,an additional degree of freedom,by providing independent bias control for the front and the back gates.Here a non-quasi-static(NQS)small signal model for DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD simulations.The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance,Cgd1and Cgd2,the intrinsic front and back distributed channel resistance,Rgd1and Rgd2respectively,the transport delay,m,and the inductance,Lsd.The parameter extraction model for an asymmetric DG MOSFET is validated with pre-established extracted parameter data,for symmetric DG MOSFET devices,from the available literature.The device simulation is performed with respect to frequency up to 100 GHz.     

A nonquasi-static MOSFET model for SPICE-transient analysis

The long-channel MOSFET model is based on an approximate solution to the nonlinear current-continuity equation in the channel. The model includes the large-signal transient and the small-signal AC analyses, although only the transient model is reported here. Comparisons have been made between this model and the 1-D numerical solution to the current-continuity equation, 2-D device simulation (PISCES), and the quasistatic (QS) results. The channel-charge partitioning scheme in the charge-based QS models is shown to be inadequate for the fast transient. This model does not use a charge-partitioning scheme and the currents are dependent on the history of the terminal voltages, not just the instantaneous voltages and their derivatives. For the slow signals (compared to the channel transit time), the nonquasistatic (NQS) model is reduced to the quasistatic 40/60 channel-charge partitioning scheme. The CPU time required for this model is about two to three times longer than that of conventional MOSFET models in SPICE     

A charge sheet model for MOSFETs with an abrupt retrograde channel: Part II. Charges and intrinsic capacitances

The 16 intrinsic capacitance components related to the gate, source, drain and depletion charges are examined for MOSFETs with an ideally abrupt retrograde doping profile in the channel, based on the analytical solutions for the drain current and body charge in the preceding paper. Though lengthy and complex in their final mathematical expressions, analytical solutions for the capacitances can be obtained. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations. The inclusion of an intrinsic surface layer in the channel merely causes a simple voltage shift for the capacitances that are not associated with the depletion charge or body bias, similarly to the variation of the drain current shown in the preceding paper. For the capacitances that are related to the depletion charge or body bias, there is not only a parallel voltage shift with an amount commensurate to the shift in drain current as well as in the other capacitances, but also a decrease in their values. This decrease depends on the thickness of the intrinsic surface layer and it amounts to 25% for a surface layer of 30 nm thickness.     

A new drain current model for short-channel MOSFETs

Reduction of channel length makes the channel current to be less than that of drain current. In this paper, by using multiplication factor model [Proc. IEEE IRPS. (1996) 318, Proc. IEEE IRPS (1999) 167] and a simple approximation of the collector current of PBT the drain current in short-channel MOSFETs is modeled and simulated. This model makes use of four parameters, which by extracting them for each device, it is possible to calculate total drain current. The simulation results from this model are compared with the results obtained from MINIMOS, in which match observed between them.     

A new threshold-voltage model for small-geometry buried-channel MOSFETs

This paper presents an analytic model for the threshold voltage of small-geometry buried-channel MOSFETs, in which the implanted buried-channel profile is approximated by a step profile. Based on the energy-band diagram, the threshold voltage of a buried-channel MOSFET is derived, in which the flatband voltage is physically defined. Using a new charge-sharing scheme, the threshold-voltage model considering the short-channel effect is calculated analytically. Similarly, based on the charge-sharing scheme, the narrow-width effect considering the field implant encroachment under the bird's beak is calculated. Combining both short-channel and narrow-width effects, the threshold-voltage model for small-geometry buried-channel MOSFETs is developed. In order to test the validity of the model, the buried-channel MOSFETs were fabricated in a production line and the threshold voltages were measured. Comparisons between the measured threshold voltage and the present model have been made. It is shown that satisfactory agreement has been obtained for wide ranges of channel lengths, channel widths and applied back-gate biases.     

A high-frequency nonquasi-static analytical model including gate leakage effects for on-chip decoupling capacitors

This paper presents a compact model for on-chip decoupling capacitors (decaps) including gate-oxide leakage. The model makes use of only four parameters, namely, channel resistance, gate-oxide capacitance, and two parameters to quantify gate-oxide leakage, to predict the static and dynamic response of decaps. Quality indices have been defined to enable development of decap design guidelines and evaluation of performance of such capacitors. The model shows how the gate leakage and longer channel lengths severely affect the performance of on-chip decaps for both low and high frequencies. The model also shows that lumped models of decaps at high frequencies fail and have to be substituted by a distributed model. Application of the model uncovers tradeoffs for thin- and thick-oxide capacitors in an available 90-nm CMOS technology. For a general-purpose technology, a reference capacitance value has been realized using decaps with a discrete width and length. Our model predicts that thick-oxide n-channel (p-channel) capacitors require /spl sim/3.37x (/spl sim/3.31x) more silicon area and /spl sim/1.70x (/spl sim/1.17x) degraded time response as compared to their thin-oxide versions. The time response is even more degraded (/spl prop/L/sup 2/) when longer channel decaps are used. This paper contributes by defining performance benchmarks for decaps.     

A new approach to extract the threshold voltage of MOSFETs

A new method is presented to extract the threshold voltage of MOSFETs. It is developed based on an integral function which is insensitive to the drain and source series resistances of the MOSFETs. The method is tested in the environments of circuit simulator (SPICE), device simulation (MEDICI), and measurements     

A new two-dimensional threshold voltage model for cylindrical, fully-depleted, surrounding-gate (SG) MOSFETs

Based on two-dimensional (2D) Poisson potential solution, a compact, analytical model for threshold voltage in cylindrical, fully-depleted, surrounding-gate (SG) MOSFETs is successfully derived. The minimum surface potential _min,surface is used to develop the threshold voltage model. Besides decreasing the characteristic factor, both the thin silicon body and gate oxide can reduce the threshold voltage roll-off simultaneously. It is also found that the threshold voltage shift is dependent on the scaling factor of λ₁L. The high scaling factor is preferred to alleviate threshold voltage degradation.     

A new approach to diffraction analysis of conductor grids. II.Perpendicular-polarized incident plane waves

For pt.I see ibid., vol.37, no.1, p.84-88 (1988). Diffraction analysis is given for infinite planar conducting-strip grids illuminated by normally incident (perpendicular-polarized) plane waves, the electric fields of which are perpendicular to the strip axes. Iris-surface electric field integral equations are used which are based on the equivalent waveguide theory, and then the electric field is solved for using the moment method. This is a universal approach applicable to infinite planar grids made of conducting strips of rectangular cross section, uniform or periodic, dense or sparse, single layer or multilayer     

A comprehensive analytical subthreshold swing (S) model fordouble-gate MOSFETs

A general analytical subthreshold swing (S) model for symmetric DG MOSFETs is derived using evanescent-mode analysis. Through a concept of effective conducting path, it explains a unique doping concentration (N _A) dependence of S, providing a unified understanding of previous S models and leading to a new improved S model for undoped DG MOSFETs. Compact, explicit expressions of a scale length are derived, which expedite projections of scalability of DG MOSFETs and its requirement     

A new threshold voltage model for deep-submicron MOSFETs with nonuniform substrate dopings

A simple but accurate threshold voltage model for deep-submicron MOSFETs with nonuniform dopings is described in this paper. In this model, a simplified quasi-delta substrate doping profile is used to approximate the nonuniformity. We apply a hyperbola function to avoid the discontinuous problem at the boundary between different doping regions. By adjusting the parameter δ, the actual gradual doping profile can be obtained. A substrate-bias dependent model of short channel effect is also introduced which describes the reduction of substrate-bias effect in deep-submicron devices. The model developed is in good agreement with two-dimensional numerical simulation.     

A new approach to model CMOS latchup

Based upon the concept of the λ-typeI-Vcharacteristics, CMOS latchup is modeled and latchup criteria are constructed. According to the model and the criteria, conditions which lead to latchup can be expressed in terms of triggering currents, parasitic resistances, and device parameters. Therefore, latchup initiation can be predicted. Both transient simulation results and experimental results coincide with theoretical predictions and calculations. This substantiates the correctness of the proposed model.     

A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-/spl kappa/ gate-dielectric MOSFETs

A grounded lamination gate (GLG) structure for high-/spl kappa/ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.     

A charge sheet model for MOSFETs with an abrupt retrograde channel Part I. Drain current and body charge

Analytical solutions to drain current, depletion and inversion charges for MOSFETs with an ideally abrupt retrograde doping profile in the channel are derived based on the charge sheet model. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations; the modeling and simulation results are in excellent agreement. It is shown that the inclusion of an intrinsic surface layer in the channel causes a voltage shift in the drain current, in accordance with experimental observations. For the depletion charge, an analytical expression principally identical to that for the uniformly doped body case is found with a simple replacement of the surface potential, ψ_s, by the potential at the interface between the intrinsic surface layer and the doped substrate, ψ_ξ.     

Adaptive arrays: A new approach to the steady-state analysis

Our main goal is a closed-form expression for the steady-state output signal-to-noise ratio (SNR) of ann-element adaptive array excited by one desired narrow-band signal andK - 1narrowband jammers. This is facilitated by representing each excitation by a complexn-dimensional vector-the excitation vector. We show that the important system parameters are functions of scalar products of pairs of these exctiation vectors. In particular, the normalized output SNR of the array is shown to be the ratio of determinants whose elements involve these scaler products. Such determinants are also shown to be involved in the expressions for the optimal array weights.     

A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs)

In this paper, a 2D compact model for potential and threshold voltage for lightly doped symmetrical double gate (DG) p-channel MOSFETs (PMOS) including negative bias temperature instability (NBTI) and short channel effects (SCEs) is presented. The model is dedicated to nano scale MOSFETs below 30 nm. In this model, both effects of interface state generation and hole-trapping are considered. Moreover, the effects of scaling down the oxide thickness and the channel thickness on NBTI are discussed. Our model is matched very well with numerical simulations obtained from COMSOL multi-physics at different drain voltages (V_d). A 4% shift in threshold voltage roll-off and 47% shift in drain induced barrier lowering (DIBL) is achieved at a gate length of 10 nm after 10 years of operation at a frequency of 1 GHz.     

Rate of decarburization of iron-carbon melts: Part II. A mixed-control model

The observed retarding effect of sulfur on the decarburization of Fe-C melts has been interpreted by means of a mixed-control mechanism involving gas-phase mass transfer and dissociative adsorption of CO₂. A mathematical model formulated on the basis of the proposed mechanism gave an excellent fit to the experimental data. The application of the model to the data provided a value of 4.42 × 10^-3 mole · cm^-2 · s^-1 · arm^-1 for the dissociative adsorption rate constant for CO₂ on liquid iron at 1973 K; the fraction of surface sites that cannot be occupied by sulfur, even at apparent surface-saturation, was found to be 0.085. The model predicts a residual rate of decarburization at high sulfur concentrations; this prediction is borne out by the experiment. The effect of convective motion within the levitated melt on the rate of decarburization below a characteristic carbon concentration was quantified. The liquid-phase mass transfer was greatly enhanced by the stirring effect of the electromagnetic field. The effective diffusivity of carbon in Fe-C melts under levitation conditions has been found to be 3.24 × 10^-3 cm² · s^-1, a value ten times as large as that under stationary conditions.     

Drain current model for undoped Gate Stack Double Gate (GSDG) MOSFETs including the hot-carrier degradation effects

In this paper, analytical models of drain current and small signal parameters for undoped symmetric Gate Stack Double Gate (GSDG) MOSFETs including the interfacial hot-carrier degradation effects are presented. The models are used to study the device behavior with the interfacial traps densities. The proposed model has been implemented in the SPICE circuit simulator and the capabilities of the model have been explored by circuit simulation example. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. GSDG MOSFET design and the accurate proposed model can alleviate the critical problem and further improve the immunity of hot-carrier effects of DG MOSFET-based circuits after hot-carrier damage.