无尺度网络中集散节点的抗脆弱性策略

回顾了无尺度网络的发现历程,论述了复杂网络的无尺度特性,并在此基础上提出了集散节点的抗脆弱性策略。提出了对集散节点加以控制后形成的层次和由虚拟节点组成的超立方体。与原集散节点相比较,层次结构具有较高的灵活性和容错性,超立方体结构具有高度自治性与故障重构性。仿真实验表明两者都具有较强的鲁棒性、稳健性。     

一种多模冗余结构存储器系统的容错设计研究

某型飞机代码转换器存储器用于存储ARINC419总线数据的地址,针对存储器数据易丢失影响数据传输的故障,提出了采用多模冗余结构的存储器系统容错设计方案;首先研究了三模冗余结构的可靠性,分析了存储器采用冗余结构设计的可行性,在此基础上,给出了多模冗余结构存储器实现方法和逻辑电路,并对其容错性进行了分析;实际工程应用表明,采用多模冗余结构存储器设计提高了国产化代码转换器的可靠性,降低了该设备的故障率。     

双微机型调速器电液控制系统的容错技术研究

研究了双微机型调速器电液控制系统的容错控制技术，分析了硬件重组、控制律重构和信号重构3种容错方法，理论分析和试验结果表明；容错控制可以进一步提高系统的可靠性。     

基于JBits的一种可重构数据处理系统可靠性研究

空间太阳望远镜(SST)是一颗对太阳进行观测的科学卫星,它使用FPGA芯片对每天采集的大量数据进行预处理.高昂的建造费用和恶劣的工作环境,确保SST数据的高可靠性成为一项艰巨任务.改进了常规TMR结构,提出一种基于配置数据的可重构硬件故障检测和修复方法,使用JBits工具简化对配置数据的各种操作.此结构和方法能及时检测到故障,通过硬件重构消除故障,提高系统可靠性.采用Markov过程理论对系统可靠性进行分析,结果表明可靠性可得到显著提高.     

基于eFPGA 的通信基带加速器的逻辑重构设计

为解决CMOS器件特征尺寸缩小带来的SoC(System on Chip,片上系统)芯片可靠性失效的问题,提出了一种基于eFPGA(embedded FPGA,嵌入式FPGA)的在线编程功能实现故障电路逻辑重构的方法。对eFPGA技术优势、JTAG(Joint TestAction Group,联合测试工作组协议)工作原理进行了分析,选取通信基带信号处理的典型算法：FFT(Fast Fourier Transform,快速傅里叶变换)、FIR(Finite Impulse Response,有限脉冲响应)滤波算法为例,模拟通信基带加速器功能失效时,借助JTAG技术配置新的互连关系,利用eFPGA进行逻辑重构,替代通信基带加速器结构实现功能自愈。仿真及验证结果显示eFPGA在面积与功耗方面具备优势,此方案可以实现预期逻辑重构的功能,能有效提高系统可靠性与灵活性。     

生成树协议的研究和实现

生成树协议因为能在局域网中构建无环路的逻辑拓扑结构和提供较强的网络容错功能,而在局域网的可靠性设计中得到广泛应用。论文简要介绍了局域网可靠性设计的思想和生成树协议的工作原理,重点描述了STP在交换机中的实现。     

Formal approach to agent-based dynamic reconfiguration in Networks-On-Chip

A Network-On-Chip (NoC) platform is an emerging topology for large-scale applications. It provides a required number of resources for critical and excessive computations. However, the computations may be interrupted by faults occurring at run-time. Hence, reliability of computations as well as efficient resource management at run-time are crucial for such many-core NoC systems. To achieve this, we utilize an agent-based management system where agents are organized in a three-level hierarchy. We propose to incorporate reallocation and reconfiguration procedures into agents hierarchy such that fault-tolerance mechanisms can be executed at run-time. Task reallocation enables local reconfiguration of a core allowing it to be eventually reused in order to restore the original performance of communication and computations. The contributions of this paper are: (i) an algorithm for initial application mapping with spare cores, (ii) a multi-objective algorithm for efficient utilization of spare cores at run-time in order to enhance fault-tolerance while maintaining efficiency of communication and computations at an adequate level, (iii) an algorithm integrating the local reconfiguration procedure and (iv) formal modeling and verification of the dynamic agent-based NoC management architecture incorporating these algorithms within the Event-B framework.     

飞机负载自动管理系统软件的容错设计

介绍了先进色机供电系统及其控制系统的组成,并对数据通信总线的容错设计进行论述。在此基础上提出了双模式运行的应用软件系统,针对系统通信故障的问题,将系统划分为正常模式和应急模式。出现通信故障后,系统由正常模式平滑切换到应急模式,刘故障进行隔离并完成系统的重构,完成应急模式下关键负载的正常供电。能够满足匕机测控系统的要求,并在试验样机中成功引用。     

高可靠性可重构单板双机系统设计

为了提高某高原无人值守雷达中波控系统的可靠性,必须对波控计算机进行双机热备份设计。介绍了利用两块嵌入式PCI04模块设计的可用于恶劣环境下的双机控制系统,并就双机之间如何实现故障检测、自动切换、系统重构进行了详细的分析,同时对单板双机的可靠性进行了研究分析。     

Design of a fault tolerant control system incorporating reliability analysis and dynamic behaviour constraints

In highly automated aerospace and industrial systems where maintenance and repair cannot be carried out immediately, it is crucial to design control systems capable of ensuring desired performance when taking into account the occurrence of faults/failures on a plant/process; such a control technique is referred to as fault tolerant control (FTC). The control system processing such fault tolerance capability is referred to as a fault tolerant control system (FTCS). The objective of FTC is to maintain system stability and current performance of the system close to the desired performance in the presence of system component and/or instrument faults; in certain circumstances a reduced performance may be acceptable. Various control design methods have been developed in the literature with the target to modify or accommodate baseline controllers which were originally designed for systems operating under fault-free conditions. The main objective of this article is to develop a novel FTCS design method, which incorporates both reliability and dynamic performance of the faulty system in the design of a FTCS. Once a fault has been detected and isolated, the reconfiguration strategy proposed in this article will find possible structures of the faulty system that best preserve pre-specified performances based on on-line calculated system reliability and associated costs. The new reconfigured controller gains will also be synthesised and finally the optimal structure that has the ‘best’ control performance with the highest reliability will be chosen for control reconfiguration. The effectiveness of this work is illustrated by a heating system benchmark used in a European project entitled intelligent Fault Tolerant Control in Integrated Systems (IFATIS EU-IST-2001-32122).     

容错多Transputer体系结构

本文提出了一种容错的多Ｔｒａｎｓｐｕｔｅｒ的体系结构。该体系结构采用并行处理芯片Ｔｒａｎｓｐｕｔｅｒ作为基本处理单元，利用多Ｔｒａｎｓｐｕｔｅｒ并行处理系统的并行性、可拓扑性，用软件实现了带一个后援备份的三倍任务仿作的动态混合冗余，达到了高可靠性的目标。在保证高可靠性的前提下，该体系结构还使资源的消耗最少。该体系结构能连续容忍系统处理单元的单故障，并自动地启动后援备份进行重构，具有很高的可靠性、实     

Biologically inspired fault-tolerant architectures for real-time control applications

Real-time control applications involve the interaction of multiple components. As systems become more complex their reliability tends to decrease, hence, fault tolerance must be incorporated to keep reliability within specified levels. A novel reconfiguration mechanism inspired by mechanisms that take place during the embryonic development of living beings is proposed in this paper. It is illustrated using an example that the rapid low-level fault-recovery characteristic of the embryonic system makes it a promising approach for real-time control applications.     

可重构阵列自主容错方法研究

设计了一种具有故障自诊断和自修复能力的可重构阵列单元结构。在功能细胞单元内部实现分布式的故障自诊断,在测试到故障后,可以自主地将距故障单元最近的空闲单元进行替换,接着自动取消受故障影响的线网,并在新的布线端点间对这些线网重新布线。以4位并行乘法器为例,实验结果证明了可重构单元阵列的故障自修复能力,并验证其重构时间较短且可靠性较高。     

Reconfiguration and analysis of a fault-tolerant circular butterflyparallel system

The butterfly parallel system has a regular and simple interconnection pattern, making it suitable for VLSI or WSI implementation. The authors propose an effective fault-tolerant technique for the circular butterfly parallel system to ensure its rigid full butterfly structure even in the presence of failures, addressing reconfiguration in detail. The resulting butterfly system has L levels, involves (1/log₂ L)% spare processing elements (PEs), and approximately 50% additional links. The reconfiguration process of the design in response to any operational fault is easy and can be performed in a distributed manner. The reliability and layout of this proposed design are evaluated analytically. This design, due to its specific configuration, exhibits significant improvement in reliability while taking only moderately more layout area     

Design and implementation of fault-tolerant multimicrocomputer systems

Distributed computer systems based on a multimicrocomputer structure offer the best preconditions to improve the reliability of a system and to realize fault tolerance. Basic fault-tolerant system (BFS), described in this paper, is the implementation of a fault-tolerant multimicrocomputer system. The architecture of BFS is a partially meshed ring structure, based on previous work. This kind of ring structure is appropriate for system monitoring and reconfiguration mechanisms.     

基于FPGA的双机容错仲裁器研究与设计

仲裁器是双机容错系统的关键部分。本文首先分析仲裁器的功能结构,分析双机系统的故障类型和检测方法,然后在FPGA芯片上,采用片内三模冗余技术和少数表决器方法设计仲裁器,并进行部分重配置设计。解决仲裁器的单点故障和故障累积问题,实现高可靠性的仲裁器设计,并设计相关测试方法完成测试工作。     

Parallel reconfiguration algorithms for mesh-connected processor arrays

Effective fault tolerance techniques are essential for improving the reliability of multiprocessor systems. At the same time, fault tolerance must be achieved at high speed to meet the real-time constraints of embedded systems. While parallelism has often been exploited to increase performance, to the best of our knowledge, there has been no previously reported work on parallel reconfiguration of mesh-connected processor arrays with faults. This paper presents two parallel algorithms to accelerate reconfiguration of the processor arrays. The first algorithm reconfigures a host array in parallel in a multithreading manner. The threads in the parallel algorithm execute independently within a safe rerouting distance. The second algorithm is based on a divide-and-conquer approach to first generate the leftmost segments in parallel and then merge the segments in parallel. When compared to the conventional algorithm, simulation results from a large number of instances confirm that the proposed algorithms significantly accelerate the reconfiguration without loss of harvest.     

环网处理器阵列的容错重构技术

高效的容错技术对于提高多处理器系统的可靠性至关重要。环网(Torus)是连接多处理器阵列的重要网络结构,而环网处理器阵列上的容错重构技术目前尚属空白。针对环网阵列的特殊连接方式,将环网阵列重构问题转化为矛盾图上求解最大独立集问题。矛盾图上的结点表示故障处理器的替换方案,而边代表了不同替换方案之间的不可共存特性。主要是根据三种不同的冗余处理器分布方案,设计生成矛盾图算法,求解最大独立集算法,以及由独立集生成逻辑处理器阵列算法,取得了令人满意的结果。实验结果表明,当阵列规模较小或故障率较低时,一行一列和十字型的冗余单元分布的重构能力较好;而随着阵列规模或故障率的增大,三种冗余单元分布策略的重构成功率都随之下降,但可通过增加冗余单元以及调整冗余分布来改善容错效果。此外,从实验结果中还可以看出,环网处理器阵列的容错能力显然优于网格(Mesh)处理器阵列。     

A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration

Network-on-Chip (NoC) is widely used as a communication scheme in modern many-core systems. To guarantee the reliability of communication, effective fault tolerant techniques are critical for an NoC. In this paper, a novel fault tolerant architecture employing redundant routers is proposed to maintain the functionality of a network in the presence of failures. This architecture consists of a mesh of 2 × 2 router blocks with a spare router placed in the center of each block. This spare router provides a viable alternative when a router fails in a block. The proposed fault-tolerant architecture is therefore referred to as a quad-spare mesh. The quad-spare mesh can be dynamically reconfigured by changing control signals without altering the underlying topology. This dynamic reconfiguration and its corresponding routing algorithm are demonstrated in detail. Since the topology after reconfiguration is consistent with the original error-free 2D mesh, the proposed design is transparent to operating systems and application software. Experimental results show that the proposed design achieves significant improvements on reliability compared with those reported in the literature. Comparing the error-free system with a single router failure case, the throughput only decreases by 5.19% and latency increases by 2.40%, with about 45.9% hardware redundancy.     

Isolation and handling of actuator faults in nonlinear systems

This work considers the problem of control actuator fault detection and isolation and fault-tolerant control for a multi-input multi-output nonlinear system subject to constraints on the manipulated inputs and proposes a fault detection and isolation filter and controller reconfiguration design. The implementation of the fault detection and isolation filters and reconfiguration strategy are demonstrated via a chemical process example.