Low-resistance bandgap-engineeredW/Si1-xGex/Si contacts

Bandgap-engineered W/Si_1-xGe_x/Si junctions (p⁺ and n⁺) with ultra-low contact resistivity and low leakage have been fabricated and characterized. The junctions are formed via outdiffusion from a selectively deposited Si_0.7Ge _0.3 layer which is implanted and annealed using RTA. The Si _1-xGe_x layer can then be selectively thinned using NH₄OH/H₂O₂/H₂O at 75°C with little change in characteristics or left as-deposited. Leakage currents were better than 1.6×10^-9 A/cm² (areal), 7.45×10^-12 A/cm (peripheral) for p⁺/n and 3.5×10^-10 A/cm² (peripheral) for n⁺/p. W contacts were formed using selective LPCVD on Si_1-xGe_x. A specific contact resistivity of better than 3.2×10^-8 Ω cm² for p ⁺/n and 2.2×10^-8 Ω cm² for n⁺/p is demonstrated-an order of magnitude n⁺ better than current TiSi₂ technology. W/Si_1-xGe _x/Si junctions show great potential for ULSI applications     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²     

DC characteristics of high-breakdown-voltage p-i-n diodes made by20-MeV Si implantation in InP:Fe

A vertical p-i-n diode is made for the first time in InP:Fe using megaelectronvolt energy ion implantation, A 20-MeV Si implantation and kiloelectronvolt energy Be/P coimplantation are used to obtain a buried n⁺ layer and a shallow p⁺ layer, respectively. The junction area of the device is 2.3×10^-5 cm² and the intrinsic region thickness is ≈3 μm. The device has a high breakdown voltage of 110 V, reverse leakage current of 0.1 mA/cm² at -80 V, off-state capacitance of 2.2 nF/cm² at -20 V, and a DC incremental forward resistance of 4 Ω at 40 mA     

Experimental determination of electron drift velocity in 4H-SiC p+-n-n+ avalanche diodes

4H-SiC p⁺-n-n⁺ diodes of low series resistivity (<1×10^-4 Ω·cm²) were fabricated and packaged. The diodes exhibited homogeneous avalanche breakdown at voltages U_b=250-270 V according to the doping level of the n layer. The temperature coefficient of the breakdown voltage was measured to be 2.6×10^-4 k^-1 in the temperature range 300 to 573 K. These diodes were capable of dissipating a pulsed power density of 3.7 MW/cm² under avalanche current conditions. The transient thermal resistance of the diode was measured to be 0.6 K/W for a 100-ns pulse width, An experimental determination of the electron saturated drift velocity along the c-axis in 4H-SIC was performed for the first time, It was estimated to be 0.8×10⁷ cm/s at room temperature and 0.75×10⁷ cm/s at approximately 360 K     

Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

Low contact resistance metallization for gigabit scale DRAM's usingfully-dry cleaning by Ar/H2 ECR plasma

A fully-dry cleaning technique with Ar/H₂ Electron Cyclotron Resonance (ECR) plasma was developed as a low contact resistance metallization technology for gigabit scale DRAM contacts. By combining with ECR TiN/Ti-CVD, extremely low contact resistances of 296 Ω and 350 Ω for 0.3-μm contact diameter with aspect ratio of 7 were realized on n⁺ and p⁺ diffusion layers, respectively. No leakage current was observed. By using this technology, a DRAM ULSI, which was planarized by Chemical Mechanical Polishing (CMP) and had deep contact holes with aspect ratio of 6, was successfully demonstrated     

InP/InGaAs HBTs with n+-InP contacting layers grown byMOMBE using SiBr4

InP/InGaAs heterojunction bipolar transistors (HBTs) with low resistance, nonalloyed TiPtAu contacts on n⁺-InP emitter and collector contacting layers have been demonstrated with excellent DC characteristics. A specific contact resistance of 5.42×10^-8 Ω·cm², which, to the best of our knowledge, is the lowest reported for TiPtAu on n-InP, has been measured on InP doped n=6.0×10¹⁹ cm^-3 using SiBr₄. This low contact resistance makes TiPtAu contacts on n-InP viable for InP/InGaAs HBTs     

Low-resistance self-aligned Ti-silicide technology for sub-quartermicron CMOS devices

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-μm CMOS devices with low-resistance and uniform TiSi₂ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi₂ films were achieved on all narrow, long n⁺ and p⁺ poly-Si and diffusion layers of 0.15-μm CMOS devices. TiSi₂ films with a sheet resistance of 5 to 7 Ω/sq were stably and uniformly formed on 0.15-μm-wide n⁺ and p⁺ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi₂ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-μm NMOSFET's and PMOSFET's with self-aligned TiSi₂ films     

The use of refractory metal and electron-beam sintering to reduce contact resistance for VLSI

Low contact resistance for metal on silicon is particularly important for VLSI where contact dimensions become ≤1 µm. This paper reports on e-beam sintering of refractory metal contacts on implanted n⁺- and p⁺-silicon layers. With this technique, we have obtained contact resistivities as low as 1.5 × 10^-7Ω. cm²and 1.2 × 10^-7Ω . cm²for n⁺and p⁺contacts, respectively. These values are the lowest contact resistivities which have been achieved experimentally to date. We found no measurable metal-silicon interdiffusion when e-beam sintering was used. Electron-beam-induced MOS damage, including neutral traps, can be removed by a forming gas anneal.     

High current p/p+-diamond Schottky diode

Epitaxial p-type Schottky diodes have been fabricated on p⁺ -substrate. While the activation energy of the epitaxial layer conductivity is 390 meV, that of the substrate is only 50 meV. At forward bias the substrate conductivity dominates above 150°C, leading for a 5×10^-5 cm² area contact to a series resistance of 14 Ω at 150°C reducing to 8 Ω at 500°C. To our knowledge, this is the lowest series resistance reported so far for a diamond Schottky diode enabling extremely high current densities of 10³ A/cm and a current rectification ratio at ±2 V of 10⁵ making these diodes already attractive as high temperature rectifiers     

A measurement method of the injection dependence of theconductivity mobility in silicon

A new electrical method to measure the conductivity mobility as a function of the injection level is proposed in this paper. The measurement principle is based on the detection of the voltage drop appearing across a n⁺-n-n⁺ (p⁺-p-p⁺) structure when a current step is forced into it at a given injection level in the intermediate region. This is obtained by using a three-terminal test pattern consisting of p⁺ , n⁺ layers realized on top of a n-n⁺ (p-p ⁺) epitaxial wafer, where the p⁺-n-n⁺ (n⁺-p-p⁺) surface diode is forward biased to monitor the conductivity of the epilayer. The use of separate terminals for injection control and mobility measurement allows this technique to overcome some limitations presented by other electrical methods available in literature, Mobility values measured up to 2·10¹⁷ cm^-3 are in good agreement with those predicted by the Dorkel and Leturcq's model (1981)     

Contact and via structures with copper interconnects fabricatedusing dual Damascene technology

A novel submicron process sequence was developed for the fabrication of CoSi₂/n⁺-Si, CoSi₂/p⁺-Si ohmic contacts and multilevel interconnects with copper as the interconnect/via metal and titanium as the diffusion barrier. SiO₂ deposited by plasma enhanced chemical vapor deposition (PECVD) using TEOS/O₂ was planarized by the novel technique of chemical-mechanical polishing (CMP) and served as the dielectric. The recessed copper interconnects in the oxide were formed by chemical-mechanical polishing. (dual Damascene process). Electrical characterization of the ohmic contacts yielded contact resistivity values of 10^-6Ω-cm² or less. A specific contact resistivity value of 1.5×10^-8Ω-cm² was measured for metal/metal contacts     

In0.52Al0.48As/In0.53Ga0.47As double-heterojunction p-n-p bipolar transistors grown bymolecular beam epitaxy

P-n-p In_0.52Al_0.48As/In_0.53Ga_0.47 As double-heterojunction bipolar transistors with a p⁺-InAs emitter cap layer grown by molecular-beam epitaxy have been realized and tested. A five-period 15-Å-thick In_0.53Ga_0.47As/InAs superlattice was incorporated between the In_0.53Ga_0.47As and InAs cap layer to smooth out the valence-band discontinuity. Specific contact resistance of 1×10^-5 and 2×10^-6 Ω-cm² were measured for nonalloyed emitter and base contacts, respectively. A maximum common emitter current gain of 70 has been measured for a 1500-Å-thick base transistor at a collector current density of 1.2×10³ A/cm². Typical current gains of devices with 50×50-μm² emitter areas were around 50 with ideality factors of 1.4     

A high-performance InGaAs/InAlAs double-heterojunction bipolartransistor with nonalloyed n+-InAs cap layer on InP(n) grownby molecular beam epitaxy

An InGaAs/InAlAs double-heterojunction bipolar transistor (DHBT) on InP(n) grown by molecular-beam epitaxy (MBE) that exhibits high DC performance is discussed. An n⁺-InAs emitter cap layer was used for nonalloyed contacts in the structure and specific contact resistances of 1.8×10^-7 and 6.0×10^-6 Ω-cm² were measured for the nonalloyed emitter and base contacts, respectively. Since no high-temperature annealing is necessary, excellent contact surface morphology on thinner base devices can easily be obtained. In devices with 50×50-μm² emitter area, common-emitter current gains as high as 1500 were achieved at a collector current density of 2.7×10³ A/cm² . The current gain increased up to 2000 for alloyed devices     

Steady-state and transient forward current-voltage characteristicsof 4H-silicon carbide 5.5 kV diodes at high and superhigh currentdensities

Steady-state and transient forward current-voltage I-V characteristics have been measured in 5.5 kV p⁺-n-n⁺ 4H-SiC rectifier diodes up to a current density j≈5.5×10 ⁴ A/cm². The steady-state data are compared with calculations in the framework of a model, in which the emitter injection coefficient decreases with increasing current density. To compare correctly the experimental and theoretical results, the lifetime of minority carriers for high injection level, τ_ph, has been estimated from transient characteristics. At low injection level, the hole diffusion length L_pl has been measured by photoresponse technique. For a low-doped n-base, the hole diffusion lengths are L_pl≈2 μm and L_ph≈6-10 μm at low and high injection levels respectively. Hole lifetimes for low and high injection levels are τ_pl≈15 ns and τ_ph≈140-400 ns. The calculated and experimental results agree well within the wide range of current densities 10 A/cm ²3 A/cm². At j>5 kA/cm², the experimental values of residual voltage drop V is lower than the calculated ones. In the range of current densities 5×10³ A/cm²4 A/cm², the minimal value of differential resistance R_d =dV/dj is 1.5×10^-4 Ω cm². At j>25 kA/cm², R_d increases with increasing current density manifesting the contribution of other nonlinear mechanisms to the formation steady-state current-voltage characteristic. The possible role of Auger recombination is also discussed     

Study of bulk and elementary screw dislocation assisted reversebreakdown in low-voltage (<250 V) 4H-SiC p+-n junctiondiodes. II. Dynamic breakdown properties

For Part I see ibid., vol.46, no.3, pp.478-84 (Mar. 1999). This paper outlines the dynamic reverse-breakdown characteristics of low-voltage (<250 V) small-area <5×10^-4 cm² 4H-SiC p⁺-n diodes subjected to nonadiabatic breakdown-bias pulsewidths ranging from 0.1 to 20 μs 4H-SiC diodes with and without elementary screw dislocations exhibited positive temperature coefficient of breakdown voltage and high junction failure power densities approximately five times larger than the average failure power density of reliable silicon pn rectifiers. This result indicates that highly reliable low-voltage SiC rectifiers may be attainable despite the presence of elementary screw dislocations. However, the impact of elementary screw dislocations on other more useful 4H-SiC power device structures, such as high-voltage (>1 kV) pn junction and Schottky rectifiers, and bipolar gain devices (thyristors, ICBT's, etc.) remains to be investigated     

Optimization of the germanium preamorphization conditions forshallow-junction formation

Shallow p⁺-n and n⁺-p junctions were formed in germanium preamorphized Si substrates. Germanium implantation was carried out over the energy range of 50-125 keV and at doses from 3×10¹⁴ to 1×10¹⁵ cm^-2. p ⁺-n junctions were formed by 10-keV boron implantation at a dose of 1×10¹⁵ cm^-2. Arsenic was implanted at 50 keV at a dose of 5×10¹⁵ cm^-2 to form the n⁺-p junctions. Rapid thermal annealing was used for dopant activation and damage removal. Ge, B, and As distribution profiles were measured by secondary ion mass spectroscopy. Rutherford backscattering spectrometry was used to study the dependence of the amorphous layer formation on the energy and dose of germanium ion implantation. Cross-sectional transmission electron microscopy was used to study the residual defects formed due to preamorphization. Complete elimination of the residual end-of-range damage was achieved in samples preamorphized by 50-keV/1×10¹⁵ cm^-2 germanium implantation. Areal and peripheral leakage current densities of the junctions were studied as a function of germanium implantation parameters. The results show that high-quality p⁺-n and n⁺-p junctions can be formed in germanium preamorphized substrates if the preamorphization conditions are optimized     

Study of bulk and elementary screw dislocation assisted reversebreakdown in low-voltage (<250 V) 4H-SiC p+-n junctiondiodes. I. DC properties

Given the high-density (~10⁴ cm^-2) of elementary screw dislocations (Burgers vector=1c with no hollow core) in commercial SiC wafers and epilayers, all large current (>1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the dc-measured reverse-breakdown characteristics of low-voltage (<250 V) small-area (<5×10^-4 cm² ) 4H-SiC p⁺-n diodes with and without elementary screw dislocations. Diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown current-voltage (I-V) knees, and highly localized microplasmic breakdown current filaments compared to screw dislocation-free devices. The observed localized 4H-SiC breakdown parallels microplasmic breakdown observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased     

Distribution of trapped charges in SiO2 film of ap+-gate PMOS structure

To investigate the highly boron-doped SiO₂ film, p⁺ polysilicon-gate PMOSFETs and capacitors were fabricated using the same process as is used for surface-channel-type n⁺-gate devices, except for the gate-type doping. After the application of negatively biased Fowler-Nordheim (FN) stress, it was found that positive charges accumulate near the silicon/SiO₂ interface and electrons accumulate near the polysilicon/SiO₂ interface in p⁺-gate capacitors. DC hot carrier stress was applied to both PMOSFET gate types. The p⁺ gate's stress time dependence of I_sub is smaller than that of the n⁺ gate, and the electric field near the drain in the p⁺ -gate PMOSFET was found to be more severe than that of the n⁺ -gate device. The subthreshold slope of the p⁺-gated PMOSFET was improved and then degraded during the hot carrier stressing, while that of the n⁺-gated device did not significantly change. The actual change of V_th was larger than the value derived from Δ_gm using the channel-shortening concept. The idea of widely spreading and partially compensated electron distribution along with source-drain direction in the SiO₂ film, which assumes the existence of trapped holes in the p⁺-gate PMOSFET, is proposed to explain these phenomena     

Strong Efficiency Improvement of SOI-LEDs Through Carrier Confinement

Contemporary silicon light-emitting diodes in silicon-on-insulator (SOI) technology suffer from poor efficiency compared to their bulk-silicon counterparts. In this letter, we present a new device structure where the carrier injection takes place through silicon slabs of only a few nanometer thick. Its external quantum efficiency of 1.4middot10^-4 at room temperature, with a spectrum peaking at 1130 nm, is almost two orders higher than reported thus far on SOI. The structure diminishes the dominant role of nonradiative recombination at the n⁺ and p⁺ contacts, by confining the injected carriers in an SOI peninsula. With this approach, a compact infrared light source can be fabricated using standard semiconductor processing steps