Investigation of voltage-swing effect and trap generation in high-k gate dielectric of MOS devices by charge-pumping measurement

Charge-pumping (CP) techniques with various rise and fall times and with various voltage swings are used to investigate the energy distribution of interface-trap density and the bulk traps. The charge pumped per cycle (Q_cp) as a function of frequency was applied to detect the spatial profile of border traps near the high-k gate dielectric/Si interface and to observe the phenomena of trap migration in the high-k dielectric bulk during constant voltage stress (CVS) sequence. Combining these two techniques, a novel CP technique, which takes into consideration the carrier tunneling, is developed to measure the energy and depth profiles of the border trap in the high-k bulk of MOS devices.     

Mechanisms of interface trap-induced drain leakage current inoff-state n-MOSFET's

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFET's after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si/SiO₂ interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 μm n-MOSFET was subjected to a dc voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsibility for the leakage current at a large drain-to-gate bias (V_dg). The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression ΔI_d=Aexp(B_it/F). The value of B_it about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V_dg decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V_dg, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant     

Compact class AB CMOS current mirror

Current mirrors are, together with differential pairs, the most common analogue building blocks in modern analogue and mixed-signal integrated circuits. Desirable features of current mirrors include: low standby power dissipation, wide input and output current swings, low supply voltage requirements, accurate current copy, and high linearity. Conventional class A topologies are unable to achieve simultaneously low quiescent power consumption and wide current swings, since they have maximum input and output currents limited by the DC bias currents. To overcome this shortcoming, class AB current mirrors have been proposed, which feature maximum currents not limited by the quiescent currents and reduced sensitivity to process tolerances [1]. Unfortunately, the additional circuitry required to achieve class AB operation often increases supply voltage requirements. For instance, the most common approach to achieve a class AB CMOS current mirror requires stacking of two MOS gate?source voltages [2]. This additional circuitry also often increases standby power consumption and adds extra intrinsic capacitances at the internal nodes. Another common issue is that quiescent currents are often dependent on supply voltage, process variations or temperature [2]. Other approaches are based on SC dynamic biasing [3], requiring the generation of two non-overlapping clock signals and suffering from charge injection errors.     

HfO_2高k栅介质漏电流机制和SILC效应

利用室温下反应磁控溅射的方法在 p- Si(1 0 0 )衬底上制备了 Hf O2 栅介质层 ,研究了 Hf O2 高 k栅介质的电流传输机制和应力引起泄漏电流 (SIL C)效应 .对 Hf O2 栅介质泄漏电流输运机制的分析表明 ,在电子由衬底注入的情况下 ,泄漏电流主要由 Schottky发射机制引起 ,而在电子由栅注入的情况下 ,泄漏电流由 Schottky发射和 Frenkel-Poole发射两种机制共同引起 .通过对 SIL C的分析 ,在没有加应力前 Hf O2 / Si界面层存在较少的界面陷阱 ,而加上负的栅压应力后在界面处会产生新的界面陷阱 ,随着新产生界面陷阱的增多 ,这时在衬底注入的情况下 ,电流传     

A model for shifts in the gate turn-on voltage of insulated-gate field-effect devices induced by ionizing radiation

Insulated gate field-effect devices with thermally grown silicon dioxide and deposited nitride insulation were subjected to electron irradiation up to a total dose of sufficient magnitude to establish dynamic equilibrium. The resultant linear shift of the gate turn-on voltage with applied gate bias over a wide range of biasing conditions has been interpreted by a model postulating a positive space charge region bounded by the insulator-semiconductor interface and a negative space charge region bounded by the insulator-metal interface. It is shown that the linearity holds for an arbitrary space charge distribution within these two regions whose widths are independent of the gate voltage during irradiation. The conditions for obtaining completely radiation-resistant devices have also been derived.     

Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs

The effects of intermittent low-bias annealing on NBT stress-induced threshold voltage shifts in p-channel VDMOSFETs are analysed in terms of mechanisms responsible for underlying changes in the densities of gate oxide-trapped charge and interface traps. Negative bias annealing after an initial NBT stress appears to freeze the initial degradation. Alternatively, either positive or zero bias removes the portion of stress-generated oxide-trapped charge and creates new reversible component of interface traps, while each repeated NBT stress regenerates the oxide-trapped charge and removes the reversible component of interface traps. The post-stress generation of interface traps under positive oxide field is ascribed to the processes at SiO₂/Si interface arising from the reversed drift direction of positively charged species, which are not likely to occur under negative gate bias. Despite all these phenomena, intermittent annealing does not seem to affect the device lifetime.     

Injection-gated DI diode with gate-controlled holding voltage

Double-injection (DI) devices consist of an anode (p⁺) and a cathode (n⁺) in a semi-insulator containing deep traps and exhibit S-type differential negative resistance (DNR) similar to SCR's under proper conditions [1]-[6]. Recently this laboratory reported a DI device with a hole emitting (p⁺) gate between the anode and the cathode which resulted in substantial improvement in the switching threshold voltage VThas well as extreme sensitivity Of VThto gate voltage [7]. A major limitation of these DI devices was Seen to be the relatively high ON state voltage. In this paper, we describe some recent results where the ON state or holding voltage VHis controlled by a supplementary gate bias which allows VHto be arbitrarily reduced to zero or even to a negative value by applying sufficiently large negative voltages to the controlling gate with respect to the cathode.     

Effects of electrical stressing in power VDMOSFETs

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps to interface-trap precursors Si_s–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Si_s–H with the charged oxide traps and H⁺ ions are proposed to be responsible for interface trap buildup.     

Mechanism of Dynamic Bias Temperature Instability in p- and nMOSFETs: The Effect of Pulse Waveform

The waveform effect on dynamic bias temperature instability (BTI) is systematically studied for both p- and nMOSFETs with ultrathin SiON gate dielectrics by using a modified direct-current current–voltage method to monitor the stress-induced interface trap density. Interface traps are generated at the inversion gate bias (negative for pMOSFETs and positive for nMOSFETs) and are partially recovered at the zero or accumulation gate bias. Devices under high-frequency bipolar stress exhibit a significant frequency-dependent degradation enhancement. Approximate analytical expressions of the interface trap generation for devices under the static, unipolar, or bipolar stress are derived in the framework of conventional reaction–diffusion (R–D) model and with an assumption that additional interface traps$(N_ it^ast)$are generated in each cycle of the dynamic stress. The additional interface trap generation is proposed to originate from the transient trapped carriers in the states at and/or near the$hboxSiO_2/hboxSi$interface upon the gate voltage reversal from the accumulation bias to the inversion bias quickly, which may accelerate dissociation of Si–H bonds at the beginning of the stressing phase in each cycle. Hence,$N_ it^ast$depends on the interface-state density, the voltage at the relaxation (i.e., accumulation) bias, and the transition time of the stress waveform (the fall time for pMOSFETs and the rise time for nMOSFETs). The observed dynamic BTI behaviors can be perfectly explained by this modified R–D model.     

The process dependence on positive bias temperature aginginstability of p+(B) polysilicon-gate MOS devices

During positive bias temperature (BT) aging, a large number of interface traps on p⁺(B) polysilicon MOS devices are generated in the upper half of the bandgap without an increase in the charges trapped in the gate oxide. The increase in interface traps can be reduced by processes which exclude the hydrogen included during fabrication. The increase in the interface-state density is explained as follows. The generation of the interface traps is caused by hydrogen ions reaching at the SiO₂/Si interface through the gate oxide from the polysilicon-gate electrode. The hydrogen ions combine with activated boron and are released from the boron under positive BT aging. The increase in interface traps is formulated by equations which are derived from the above model     

On the effect of bias on the behavior of MOS structures subjected to ionizing radiation

Using a quantitative model [6], the analysis of published data on the effect of the gate bias on the behavior of MOS structure subjected to ionizing radiation is performed. It is shown that, along with hydrogen-containing traps, there are hydrogen-free hole traps in samples with a low content of hydrogen; traps of both types are distributed inhomogeneously over the thickness of the gate insulator. In addition to ionized hydrogen, neutral hydrogen is involved in the formation of surface states and provides the main contribution to this process at negative gate bias. A decrease in the shift of the threshold voltage in the case of high fields is caused by an increase in the drift component of the hole drain to the electrodes.

     

Temperature and voltage dependences of the capture and emission times of individual traps in high-k dielectrics

Quantized threshold voltage (VTH) relaxation transients are observed in nano-scaled field effect transistors (FETs) after bias temperature stress. The abrupt steps are due to trapping/detrapping of individual defects in the gate oxide and indicate their characteristic emission/capture times. Individual traps are studied in n-channel SiO₂/HfSiO FETs after positive gate stress to complement previous studies performed on SiO(N). Similarly to single SiO(N) traps, strong thermal and bias dependences of the emission and capture times are demonstrated. The high-k traps have a higher density but a reduced impact on VTH due to their separation from the channel.     

Extraction of Si-SiO/sub 2/ interface trap densities in MOS structures with ultrathin oxides

Si-SiO/sub 2/ interface trap densities can be measured in MOS structures with ultrathin oxides using charge pumping (CP) and small gate pulses. This presents three decisive advantages with respect to the conventional large gate voltage swing approach. First, the extraction is simple as carrier emission does not contribute to the CP signal so that the CP current magnitude directly reflects the interface trap density. Second, the tunneling current is strongly reduced allowing a more easy extraction of the CP signal and third, such a reduction prevents the insulator and the insulator-silicon interface from any degradation. By doing so, Si-SiO/sub 2/ interface trap densities are measured in MOSFETs with oxides which are 1.8 and 1.3 nm thick.     

Characterization, modeling, and minimization of transient thresholdvoltage shifts in MOSFETs

MOSFETs subjected to large-signal gate-source voltage pulses on microsecond to millisecond time scales exhibit transient threshold voltage shifts which relax over considerably longer periods of time. This problem is important in high-accuracy analog circuits where it can cause errors at the 12 b level and above. In this paper, transient threshold voltage shifts are characterized with respect to their dependence on stress amplitude and duration, relaxation time, gate bias, substrate bias, drain voltage, temperature, and channel width and length. In contrast to previous studies, threshold voltage shifts are measured at time and voltage scales relevant to analog circuits, and are shown to occur even when the effects of Fowler-Nordheim tunneling, avalanche injection, hot carriers, trap generation, self-heating, mobile ions, and dipolar polarizations are absent. A new model is proposed in which channel charge carriers tunnel to and from near-interface oxide traps by one of three parallel pathways. Transitions may occur elastically, by direct tunneling between the silicon band edges and an oxide trap, or inelastically, by tunneling in conjunction with a thermal transition in the insulator or at the Si-SiO₂ interface. Simulations based on this model show excellent agreement with experimental results. The threshold voltage shifts are also shown to be correlated with 1/f noise, in corroboration of the tunneling model. Techniques for the minimization and modeling of errors in circuits are presented     

Effects of measurement frequency and temperature anneal on differential gate capacitance spectra observed in hot carrier stressed MOSFET's

Hot carrier generated fixed and interface traps, located at the Si-SiO/sub 2/ interface near the drain junction, are observed from the gate-to-drain capacitance of the MOS transistor, using an AC measurement signal applied to the drain. When the channel is biased in inversion, the drain junction is forward biased and carriers from the AC signal source are readily injected into the channel, leading to charge exchange between the inversion carriers and the traps located in one half of the band gap. In channel depletion, the drain junction is reverse biased, and charge exchange is between the substrate majority carriers and traps located in the other half of the band gap. The charge interaction manifests itself in a differential gate capacitance, extracted from pre- and post-stress gate capacitance voltage curves. The differential capacitance spectrum shows two distinct peaks, which are attributed to the response of donor and acceptor interface traps, located on either half of the band gap. This model is supported by capacitance measurements at different frequencies. Lower frequencies lead to a proportionally larger increase in the depletion regime response. Prolonged stress results in the convolution of the two peaks. A reverse bias on the drain leads to the deconvolution of the spectrum, allowing the two peaks to be clearly resolved. Trap response may be masked by the fixed charge, but this can be overcome by depopulation of trapped electrons or neutralization of trapped holes through elevated temperature anneal. The differential gate-to-drain capacitance allows the electrical identification of both donor and acceptor interface traps in the same device.<>     

LDMOS器件热载流子退化特性测试中的电荷泵技术研究

A measuring technique based on the CP（charge pumping）method for hot-carrier degradation measurement of high voltage N-LDMOS is researched in depth.The impact of the special configuration on the CP spectrum and the gate voltage pulse frequency range which is suitable for high voltage N-LDMOS in CP measurements is investigated in detail.At the same time,the impacts of different reverse voltage applied on the source and drain electrodes and of the gate pulse shape on the CP curve change in N-LDMOS are also proposed and analyzed.The conclusions give guidance on measuring the density of interface states with experimental instructions and offer theoretic instructions for analyzing CP curves in high voltage N-LDMOS more accurately.     

Research into charge pumping method technique for hot-carrier degradation measurement of LDMOS

A measuring technique based on the CP (charge pumping) method for hot-carrier degradation measure ment of high voltage N-LDMOS is researched in depth. The impact of the special configuration on the CP spectrum and the gate voltage pulse frequency range which is suitable for high voltage N-LDMOS in CP measurements is investigated in detail. At the same time, the impacts of different reverse voltage applied on the source and drain electrodes and of the gate pulse shape on the CP curve change in N-LDMOS are also proposed and analyzed. The conclusions give guidance on measuring the density of interface states with experimental instructions and offer theoretic instructions for analyzing CP curves in high voltage N-LDMOS more accurately.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

The role of electron traps on the post-stress interface trapgeneration in hot-carrier stressed p-MOSFETs

The generation of interface traps in p-MOSFETs subjected to hot-electron injection is found to proceed even after the stress has been terminated. The extent of post-stress interface trap generation is strongly dependent on the magnitude of the preceding hot-electron stress, as well as the magnitude and polarity of the gate voltage during relaxation. Trap generation is enhanced for negative gate voltage anneal, but suppressed for positive gate voltage anneal. For a given stress-induced damage, the corresponding trap generation kinetics can be completely described by a single characteristic, which is shifted in time according to the magnitude of the applied gate voltage. Existing interface trap generation models are discussed in the light of the experimental results. A new model involving the tunneling of holes from the inversion layer to deep-level electron traps is proposed. Similar post-stress effect observed for hot-electron stressed n-MOSFETs provides additional support for the model. Our work suggests that near-interface electron traps, apart from the well-known hole traps, may also significantly affect the long-term stability of the Si-SiO₂ interface     

Experimental evidence of suppression on oxygen vacancy formation in Hf based high-κ gate dielectrics with La incorporation

Experimental evidence of suppression on oxygen vacancy formation in Hf based high-κ gate dielectrics with La incorporation is provided by using modified charge-pumping (CP) techniques. The original distribution of interface traps and bulk traps of pure HfO₂ and HfO₂/LaOx dielectric stack are extracted and compared by CP techniques. It is found that devices with HfO₂/LaOx dielectric stack have higher interface trap but lower bulk trap density than those with pure HfO₂. Especially, device with HfO₂/LaOx dielectric stack is highly resistant to constant voltage stress, which can be attributed to the suppression on oxygen vacancy formation in Hf based high-κ gate dielectrics with La incorporation.