Study of microwave damage effect on HEMT low noise amplifier under different drain voltage bias

The microwave damage effect on high electron mobility transistor (HEMT) low noise amplifier (LNA) under different drain voltage bias is studied using TCAD simulation and experiments. Simulation and experimental results suggest that the damage power thresholds and damage locations of single stage LNA under different drain voltage bias are almost the same. Nevertheless, the output power under zero drain bias is about 5.6 dB higher than it under normal (3 V) drain bias with the injection of large power microwave pulses. In Addition, the output power relative to it under normal drain bias decreases linearly with the increase of drain bias, following the function of P_dB = − 1.85V_ds + 5.7. For multi-stage LNA, the observation using optical microscope reveals that the first and second stage HEMT of LNA under zero drain bias are both damaged while only first stage HEMT of LNA under normal bias is damaged with the injection of same large power microwave pulses, which is consistent with simulated output characteristics results.     

Effect of body bias and temperature on low-frequency noise in 40-nm nMOSFETs

This study investigated the effects of temperature and body bias on drain current flicker noise (1/f) in 40-nm nMOSFETs. The 1/f noise is attributable to the charge number fluctuation correlating with the mobility fluctuation. At 300 K, as the depletion width was decreased, 1/f noise decreased with the body bias from − 0.5 to + 0.5 V in the weak inversion; conversely, 1/f noise was independent of the body bias because of the neglected depletion charge capacitance in the strong inversion. When the temperature was below 150 K, 1/f noise increased when the drain voltage was low because of the Fermi level toward the band edge, which has a higher trap density and corresponds to the inverse square of the subthreshold swing. However, when the drain voltage was high, 1/f noise was dominated by the mobility fluctuation because a wider strong inversion region at 150 K resulted in a lower 1/f noise and insignificant body effect. The analysis of this behavior in 40-nm devices may assist in determining the optimal device fabrication methods and circuit design.     

High-performance diketopyrrolopyrrole-based organic field-effect transistors for flexible gas sensors

We demonstrate high-performance flexible polymer OFETs with P-29-DPP-SVS in various geometries. The mobilities of TG/BC OFETs are approximately 3.48 ± 0.93 cm²/V s on a glass substrate and 2.98 ± 0.19 cm²/V s on a PEN substrate. The flexible P-29-DPP-SVS OFETs exhibit excellent ambient and mechanical stabilities under a continuous bending stress of 1200 times at an R = 8.3 mm. In particular, the variation of μ_FET, V_Th and leakage current was very negligible (below 10%) after continuous bending stress. The BG/TC P-29-DPP-SVS OFETs on a PEN substrate applies to flexible NH₃ gas sensors. As the concentration of NH₃ increased, the channel resistance of P-29-DPP-SVS OFETs increased approximately 100 times from ∼10⁷ to ∼10⁹ Ω at V_SD = −5 V and V_GS = −5 V.     

The effect of external stress on the electrical characteristics of AlGaN/GaN HEMTs

The electrical characteristics of AlGaN/GaN high electron mobility transistors under the application of uniform in-plane tensile and compressive stress were measured. The results demonstrate the change of the drain–source I_ds–V_ds characteristics as a function of the external stress. The output current at V_ds = 10 V increases linearly with the stress with the slope about 3 × 10⁻⁶ A MPa⁻¹. It is associated with the piezoelectric effect and kink effect. Moreover, the magnitude of the kink effect is found to be affected by the stress. It displays a linear changing trend with the slope of 3.3 × 10⁻⁴ mS MPa⁻¹ within the stress level. The energy band structure is suggested to be responsible for the dependence of the kink effect on the stress.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Low-voltage,high speed inkjet-printed flexible complementary polymer electronic circuits

We report the development of high-performance inkjet-printed organic field-effect transistors (OFETs) and complementary circuits using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) and poly(methyl methacrylate) (PMMA) for high-speed and low-voltage operation. Inkjet-printed p-type polymer semiconductors containing alkyl-substituted thienylenevinylene (TV) and dodecylthiophene (PC12TV12T) and n-type P(NDI2OD-T2) OFETs showed high field-effect mobilities of 0.1–0.4 cm² V^?1 s^?1 and low threshold voltages down to 5 V. These OFET properties were modified by changing the blend ratio of P(VDF-TrFE) and PMMA. The optimum blend – a 7:3 wt% mixture of P(VDF-TrFE) and PMMA – was successfully used to realize high-performance complementary inverters and ring oscillators (ROs). The complementary ROs operated at a supplied bias (V_DD) of 5 V and showed an oscillation frequency (f_osc) as high as ～80 kHz at V_DD = 30 V. Furthermore, the f_osc of the complementary ROs was significantly affected by a variety of fundamental parameters such as the electron and hole mobilities, channel width and length, capacitance of the gate dielectrics, V_DD, and the overlap capacitance in the circuit configuration.     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

Natural polyelectrolyte: Major ampullate spider silk for electrolyte organic field-effect transistors

The major ampullate (MA) silk collected from giant wood spiders Nephila pilipes consists of 12% glutamic acid (Glu) and 4% tyrosine (Tyr) acidic amino residues. The MA silk may act as a natural polyelectrolyte for organic field-effect transistors (OFETs). Pentacene and F₁₆CuPc OFETs were fabricated with the MA silk thin film as the gate dielectric. The MA silk thin film with surface roughness of 4 nm and surface energy of 36.1 mJ/m² was formed on glass using a hexafluoroisopropanol (HFIP) organic process. The MA silk gate dielectric in pentacene OFETs may improve the field-effect mobility (μ_FE,sat) value in the saturation regime from 0.11 in vacuum to 4.3 cm² V⁻¹ s⁻¹ in air ambient at ca. 70% RH. The corresponding threshold voltage (V_TH) value reduced from −6 V in vacuum to −0.5 V in air ambient. Similar to other polyelectrolytes, the changes of μ_FE,sat and V_TH may be explained by the generation of electric double layers (EDLs) in the MA silk thin film in air ambient due to water absorption.     

Improved multi-recessed 4H–SiC MESFETs with double-recessed p-buffer layer

An improved multi-recessed 4H–SiC metal semiconductor field effect transistor (MRD-MESFET) with double-recessed p-buffer layer (DRB-MESFET) is proposed in this paper. By introducing a double-recessed p-buffer layer, the gate depletion layer is further modulated, and higher drain saturation current and DC transconductance are obtained compared with the MRD-MESFET. The simulations show that the drain saturation current of the DRB-MESFET is about 42.4% larger than that of the MRD-MESFET. The DC transconductance of the DRB-MESFET is almost 15% higher than that of the MRD-MESFET and very close to that of double-recessed structure (DR-MESFET) at the bias conditions of V_gs=0 V and V_ds=40 V. The proposed structure has an improvement of 26.1% and 74.2% in the output maximum power density compared with that of the MRD-MESFET and DR-MESFET, respectively. In the meanwhile, the proposed structure possesses smaller gate-source capacitance, which results in better RF characteristics.     

The role of water in the device performance of n-type PTCDI-C8 organic field-effect transistors with solution-based gelatin dielectric

Gelatin is a natural protein, which works well as the gate dielectric for N,N-dioctyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C₈) organic field-effect transistors (OFETs). An aqueous solution process was applied to form the gelatin gate dielectric on poly(ethylene terephthalate) (PET) by spin-coating and subsequent casting. The field-effect mobility in the saturation regime (μ_FE,sat) and the threshold voltage (V_T) values of a typical 40 nm PTCDI-C₈ OFET are (0.22 cm² V⁻¹ s⁻¹, 55 V) in vacuum and (0.74 cm² V⁻¹ s⁻¹, 2.6 V) in air ambient. The maximum voltage shift in hysteresis is also reduced from 10 V to 2 V when the operation environment for PTCDI-C₈ OFETs is changed from vacuum to air ambient. Nevertheless, a slight reduction of electron mobility was found when the device was stressed in the air ambient. The change in the device performance has been attributed to the charged ions generation owing to water absorption in gelatin in air ambient.     

Analysis of traps effect on AlGaN/GaN HEMT by luminescence techniques

The study is carried out on AlGaN/GaN HEMTs presenting current collapse effect at V_ds lower than 6 V. This effect is completely recovered by illuminating the component with light of 710 nm wavelength (1.75 eV). The spectral analysis of the light emission in the visible near infrared spectrum shows a bell-shape with superimposed distinct emission peaks. These features suggest that the electroluminescence (EL) signal is due to the direct intraband of electrons and inelastic intraband transition of electrons due to scattering by charged centres. Photoionisation experiments have been conducted to determine the light wavelengths/energies that separately change the drain current and the gate leakage current.     

Complementary-like inverters based on an ambipolar solution-processed molecular bis(naphthalene diimide)-dithienopyrrole derivative

We report on high-mobility top-gate organic field-effect transistors (OFETs) and complementary-like inverters fabricated with a solution-processed molecular bis(naphthalene diimide)-dithienopyrrole derivative as the channel semiconductor and a CYTOP/Al₂O₃ bilayer as the gate dielectric. The OFETs showed ambipolar behavior with average electron and hole mobility values of 1.2 and 0.01 cm² V^?1 s^?1, respectively. Complementary-like inverters fabricated with two ambipolar OFETs showed hysteresis-free voltage transfer characteristics with negligible variations of switching threshold voltages and yielded very high DC gain values of more than 90 V/V (up to 122 V/V) at a supply voltage of 25 V.     

Investigation on the thermal behavior of 0.15 μm gate-length In0.4Al0.6As/In0.4Ga0.6As MHEMT

In this study, we have successfully investigated the electrical performances of In_0.4Al_0.6As/In_0.4Ga_0.6As metamorphic high-electron-mobility transistor (MHEMT) at temperatures range from 275 K to 500 K comprehensively. By extracting the device S-parameters, the temperature dependent small signal model has been established. At room temperature, 0.15 μm T-gate device with double δ-doping design exhibits f_T and f_MAX values of 103 GHz and 204 GHz at V_ds = 1 V, an extrinsic transconductance of 678 mS/mm, and a current density of 578 mA/mm associated with a high breakdown voltage of ?13 V. Power measurements were evaluated at 40 GHz and the measured output power, linear power gain, and maximum power-added efficiency, were 7.12 dBm, 10.15 dB, and 23.1%, respectively. The activation energy (E_a) extracted from Arrhenius plots is = 0.34 eV at 150 ≦ T ≦ 350 K. The proposed device is promisingly suitable for millimeter-wave power application.     

Current spreading effects in fully printed p-channel organic thin film transistors with Schottky source–drain contacts

Contact effects have been analyzed, by using numerical simulations, in fully printed p-channel OTFTs based on a pentacene derivative as organic semiconductor and with Au source/drain contacts. Considering source–drain Schottky contacts, with a barrier height of 0.46 eV, device characteristics can be perfectly reproduced. From the detailed analysis of the current density we have shown that current spreading occurs at the source contact, thus influencing the effective contact resistance. At low V_ds and for a given V_gs, the current is mainly injected from an extended source contact region and current spreading remains basically constant for increasing V_ds. However, by increasing V_ds the depletion layer of the Schottky contact expands and reaches the insulator–semiconductor interface, causing the pinch-off of the channel at the source end (V_dsat1). For V_ds > V_dsat1 the current injected from the edge of the source contact rapidly increases while the current injected from the remaining part of the source contact basically saturates. Current spreading shows a V_gs-dependence, since the contact injection area depends on the channel resistance and also barrier lowering of the Schottky source contact depends upon V_gs. The injected current from the edge of the source contact can be reproduced using the conventional diode current expression, assuming a constant value for the zero barrier lowering saturation current and considering a V_gs-dependent barrier lowering. The presented analysis clarifies the V_gs-dependence of the contact current–voltage characteristics and points out that the I–V contact characteristics cannot directly be related to a single diode characteristics. Indeed, the contact characteristics result from the combination of two rather different regimes: at low V_ds the current is injected from an extended source contact region with a current spreading related to V_gs, while for V_ds above the pinch-off of the channel at source end, the current is injected primarily from the edge of the source contact and is strongly enhanced by the barrier lowering.     

Short-channel effect and device design of extremely scaled tunnel field-effect transistors

For serving as ideal switching devices in future energy-efficient applications, scaling down the channel lengths of tunnel-field effect transistors (TFETs) is essential to follow the pace of Si-based CMOS technologies. This work elucidates the short-channel mechanisms and the role of the drain in extremely-scaled TFETs. The scalability of TFETs depends strongly on the appropriately low drain concentration, whereas the capability of the drain for scaling relies on a sufficient drain region. The drain with a light concentration of 5 × 10¹⁷ cm⁻³ and a minimum length of 20 nm enables 5 nm TFETs to exhibit favorable on–off switching characteristics. In sub-20 nm TFETs, the total drain and channel lengths must satisfy the minimum criteria of approximately 25 nm to sustain reversely biased drain voltage of 0.7 V. The asymmetric Si_1−xGe_x source heterojunction is combined with the minimum drain design in 5 nm TFETs to separately optimize the source- and drain-side tunnel junctions, generating ideal on-/off-currents and switching characteristics to serve as a promising design approach of sub-5 nm TFETs.     

Gain improvement and microwave operation of 4H–SiC MESFET with a new recessed metal ring structure

A new multi-recessed 4H-SiC MESFET with recessed metal ring for RF embedded circuits is proposed (MR2-MESFET). The key idea in the proposed structure is based on the elimination of the spaces adjacent to gate and stopped the depletion region extending towards drain and source and the reduction of the channel thickness between gate and drain to increase breakdown voltage (V_BR); meanwhile the elimination of the gate depletion layer extension to source/drain to decrease gate-source capacitance (C_gs). The influence of multi-recessed drift region and recessed metal ring structures on the characteristics of the MR2-MESFET is studied by numerical simulation. The optimized results show that the V_BR of the MR2-MESFET is 119% larger than that of the conventional 4H–SiC MESFET (C-MESFET); meanwhile maintain 85% higher saturation drain current. Therefore, the maximum output power density of the MR2-MESFET is 23.1 W/mm compared to 5.5 W/mm of the C-MESFET. Also, the cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of 24.9 and 91.7 GHz are obtained for the MR2-MESFET compared to 11 and 40 GHz of the C-MESFET structure, respectively. The proposed MR2-MESFET shows a maximum stable gain (MSG) exceeding 23.6 dB at 3.1 GHz which is the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

High-performance solution-processed organic transistors with electroless-plated electrodes

Electroless-plated gold and platinum films are used as source and drain electrodes in high-performance solution-processed organic field-effect transistors (OFETs), representing a promising large-area, near-room-temperature and vacuum-free technique to form low-resistance metal-to-semiconductor interfaces in ambient atmosphere. Developing non-displacement conditions using a Pt-colloidal catalyst for soft electroless plating, the electrodes are deposited on crystallized thin films of 2,9-didecyl-dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (C₁₀-DNTT) without significant damage to the semiconductor material. The top-contact OFETs show remarkable performance, with a mobility of 6.0 cm² V^?1 s^?1. The method represents a practical fabrication technique to mass-produce circuitry arrays of nearly best-performing OFETs for the printed electronics industry.     

Dielectric surface-polarity tuning and enhanced operation stability of solution-processed organic field-effect transistors

The electrical performance of triethylsilylethynyl anthradithiophene (TES-ADT) organic field-effect transistors (OFETs) was significantly affected by dielectric surface polarity controlled by grafting hexamethyldisilazane and dimethyl chlorosilane-terminated polystyrene (PS-Si(CH₃)₂Cl) to 300-nm-thick SiO₂ dielectrics. On the untreated and treated SiO₂ dielectrics, solvent–vapor annealed TES-ADT films contained millimeter-sized crystals with low grain boundaries (GBs). The operation and bias stability of OFETs containing similar crystalline structures of TES-ADT could be significantly increased with a decrease in dielectric surface polarity. Among dielectrics with similar capacitances (10.5–11 nF cm⁻²) and surface roughnesses (0.40–0.44 nm), the TES-ADT/PS-grafted dielectric interface contained the fewest trap sites and therefore the OFET produced using it had low-voltage operation and a charge-carrier mobility ∼1.32 cm² V⁻¹ s⁻¹, on–off current ratio >10⁶, threshold voltage ∼0 V, and long-term operation stability under negative bias stress.     

Organic field-effect transistor and its photoresponse using a benzo[1,2-b:4,5-b′]difuran-based donor–acceptor conjugated polymer

Organic field-effect transistors (OFETs) were fabricated through a solution process with a donor–acceptor (D–A) conjugated polymer poly{4,8-bis(2′-ethylhexylthiophene)benzo [1,2-b;3,4-b′]difuran-alt-5,5-(4′,7′-di-2-thienyl-5′,6′-dioctyloxy-2′,1′,3′-benzothiadiazole)} (PBDFTDTBT) as the active layer, which is a highly efficient D–A conjugated polymer as a donor in polymer solar cells with a power conversion efficiency (PCE) over 6.0%. The OFET devices showed a hole mobility of 0.05 cm²/Vs and an on/off ratio of 4.6 × 10⁵. Those are one of the best performance parameters for OFETs based on D–A conjugated polymers including benzo[1,2-b:4,5-b′]dithiophene (BDT) or benzo[1,2-b:4,5-b′]difuran (BDF) unit. The photoresponse of OFETs was investigated by modulating light with various intensities. The devices produced a photosensitivity (I_light/I_dark) of 1.2 × 10⁵ and a photoresponsivity of 360 mA W⁻¹ under white light illumination. The drain current in saturation region increases gradually with increasing illumination intensity. The threshold voltage exhibited a positive shift from −15.6 V in darkness to 27.8 V under illumination, which can be attributed to the well-known photovoltaic effect resulting from the transport of photogenerated holes and trapping of photogenerated electrons near the source electrode in organic phototransistors. Meanwhile, the devices showed good stability and with no obvious degeneration for 3 months in air. The study suggests that D–A conjugated polymers including BDF unit can be potentially applied in OFETs and organic phototransistors in addition to highly efficient polymer solar cells.     

Investigation of temperature variations on analog/RF and linearity performance of stacked gate GEWE-SiNW MOSFET for improved device reliability

In this paper, reliability issues of Stacked Gate (SG)-Gate Electrode Workfunction Engineered (GEWE)-Silicon Nanowire (SiNW) MOSFET is examined over a wide range of ambient temperatures (200–600 K) and results so obtained are simultaneously compared with conventional SiNW and GEWE-SiNW MOSFET using 3D-technology computer aided design quantum simulation. The results indicate that two temperature compensation points (TCP) are obtained: one for drain current (I_ds) and other for cut-off frequency (f_T) where device Figure Of Merits (FOMs) become independent of temperature, and it is found at 0.65 V in SG-GEWE-SiNW in comparison to other devices, hence will open opportunities for wide range of temperature applications. Furthermore, significant improvement in Analog/RF performance of SG-GWEW-SiNW is observed in terms of I_on/I_off, Subthreshold Swing (SS), device efficiency, f_T, noise conductance and noise figure as temperature reduces. It is also observed that at low temperature SG-GEWE-SiNW unveils highly stable linearity performance owing to reduced distortions. These results explain the improved reliability of SG-GEWE-SiNW at low temperatures over GEWE-SiNW MOSFET.