Very low phase noise RF quadrature oscillator architecture

An architecture for RF quadrature oscillators is presented, which, according to simulations, shows a figure of merit some 20 dB higher than that of other quadrature oscillators. The new quadrature oscillator compares favourably even with a state-of-the-art design of the popular negative-resistance differential oscillator     

Low noise RF MOSFETs on flexible plastic substrates

We report a low minimum noise figure (NF/sub min/) of 1.1 dB and high associated gain (12 dB at 10 GHz) for 16 gate-finger 0.18-/spl mu/m RF MOSFETs, after thinning down the Si substrate to 30 /spl mu/m and mounting it on plastic. The device performance was improved by flexing the substrate to create stress, which produced a 25% enhancement of the saturation drain current and lowered NF/sub min/ to 0.92 dB at 10 GHz. These excellent results for mechanically strained RF MOSFETs on plastic compare well with 0.13-/spl mu/m node (L/sub g/=80 nm) devices.     

铌酸锂晶片的键合减薄及热释电性能研究

铌酸锂(LN)作为一种热释电材料,可以被用于制作光电探测器敏感单元的敏感层,但通常LN晶片厚度为0.5 mm,远大于光电敏感单元厚度的要求,所以需要用键合减薄及抛光技术对LN晶片进行加工处理。本研究所用键合减薄技术主要包含:RZJ-304光刻胶键合、铣磨、抛光、剥离液剥离和丙酮清洗RZJ-304胶。利用该技术加工得到了面积为10 mm×10 mm,厚度为50μm,表面比较光滑,表面粗糙度为1.63 nm的LN晶片。LN晶片的热释电信号峰峰值在减薄抛光后为176 mV,是未经处理时的4倍,满足了热释电探测器敏感层的要求。     

An investigation of the DC and RF performance of InP DHBTs transferred to RF CMOS wafer substrate

This paper investigated the DC and RF performance of the InP double heterojunction bipolar transistors (DHBTs) transferred to RF CMOS wafer substrate.The measurement results show that the maximum values of the DC current gain of a substrate transferred device had one emitter finger,of 0.8μm in width and 5μm in length,are changed unobviously,while the cut-off frequency and the maximum oscillation frequency are decreased from 220 to 171 GHz and from 204 to 154 GHz,respectively.In order to have a detailed insight on the degradation of the RF performance,small-signal models for the InP DHBT before and after substrate transferred are presented and comparably extracted.The extracted results show that the degradation of the RF performance of the device transferred to RF CMOS wafer substrate are mainly caused by the additional introduced substrate parasitics and the increase of the capacitive parasitics induced by the substrate transfer process itself.     

Low-voltage low-power CMOS RF low noise amplifier

In this paper, a 1 V, 2 GHz CMOS low-noise amplifier (LNA) was developed intended for use in the front-end receiver. The circuit is simulated in standard $0.25\mathrm{\mu }\mathrm{m}$ CMOS MOSIS. The LNA gain is 25.675 dB, noise figure (NF) is 4 dB, reverse isolation $(S_{12})$ is $-134.3\mathrm{dB}$, input return loss $(S_{11})$ is $-14.6\mathrm{dB}$, output return loss $(S_{22})$ is $-13.34\mathrm{dB}$, and the power consumption is 5.13 mA from a single 1 V power supply. One of the features of the proposed design is using a three-component cascode limitation, one of it is a transistor, to reduce the supply voltage.     

Accurate electron mobility extraction in nMOSFETs by RF split CV

In this paper, an accurate capacitance extraction method, based on high frequency measurements (100 MHz–1 GHz), is used to study the carrier mobility in conventional nMOSFETs and metal/high-k gate stacked nMOSFETs. Simulations have been made to extract the main physical parameters. Effective carrier mobility is extracted, using a split CV methodology and a comparison is drawn between RF (radio frequency) and LF (low frequency) measurements for RF dedicated devices. Several problems encountered during high frequency measurements are also discussed. Finally, a method for using RF split CV with any kind of devices is proposed.     

Power amplifier/low noise amplifier RF switch

Front-end RF switches commonly use PIN diodes as the switching element. A novel RF switch using the existing front-end power amplifier and low noise amplifier to give better performance with reduced component count and lower cost is demonstrated     

High-quality crystalline layer transfer from a silicon-on-insulator substrate onto a sapphire substrate using wafer bonding

We demonstrate layer transfer of 150 nm of Si from a 200-mm, silicon-on-insulator (SOI) substrate onto a sapphire substrate using low-temperature wafer bonding (T=150°C). The crystalline quality and the thermal stability of the transferred Si layer were characterized by x-ray diffraction (XRD). A broadening of the (004) Si peak is observed only for anneal temperatures T_A≥800°C, indicating some degradation of the crystalline quality of the transferred Si film above these temperatures. The measured electron Hall mobility in the bonded Si layer is comparable to bulk silicon for T_A≤800°C, indicating excellent material quality.     

RF model of flexible microwave single-crystalline silicon nanomembrane PIN diodes on plastic substrate

This paper reports the realization and RF modeling of flexible microwave P-type-Intrinsic-N-type (PIN) diodes using transferrable single-crystalline Si nanomembranes (SiNMs) that are monolithically integrated on low-cost, flexible plastic substrates. With high-energy, high-dose ion implantation and high-temperature annealing before nanomembrane release and transfer process, the parasitic parameters (i.e. resistance, inductance, etc.) are effectively reduced, and the flexible PIN diodes achieve good high-frequency response. With consideration of the flexible device fabrication, structure and layout configuration, a RF model of the microwave single-crystalline Si nanomembrane PIN diodes on plastic substrate is presented. The RF/microwave equivalent circuit model achieves good agreement with the experimental results of the single-crystalline SiNM PIN diodes with different diode areas, and reveals the most influential factors to flexible diode characteristics. The study provides guidelines for properly designing and using single-crystalline SiNMs for flexible RF/microwave diodes and demonstrates the great possibility of flexible monolithic microwave integrated systems.     

Ge outdiffusion effect on flicker noise in strained-Si nMOSFETs

The flicker noise characteristics of strained-Si nMOSFETs are significantly dependent on the gate oxide formation. At high temperature (900/spl deg/C) thermal oxidation, the Si interstitials at the Si/oxide interface were injected into the underneath Si-SiGe heterojunction, and enhanced the Ge outdiffusion into the Si/oxide interface. The Ge atoms at Si/oxide interface act as trap centers, and the strained-Si nMOSFET with thermal gate oxide yields a much larger flicker noise than the control Si device. The Ge outdiffusion is suppressed for the device with the low temperature (700/spl deg/C) tetraethylorthosilicate gate oxide. The capacitance-voltage measurements of the strained-Si devices with thermal oxide also show that the Si/oxide interface trap density increases and the Si-SiGe heterojunction is smeared out due to the Ge outdiffusion.     

Study on the effects of wafer thinning and dicing on chip strength

Die cracking is an annoying problem in the packaging industry. In this paper, we identified the weak regions, in terms of mechanical strength, in chips in a semiconductor wafer using the three-point bending test. The weak regions were observed in two sectors approximately 45/spl deg/ wide, axisymmetric to the wafer center. The strength of the chips within these weak regions was about 30%-35% lower than the average chip strength of the whole wafer. The existence of these weak regions was related to spiral grinding marks, which, in turn, were formed by backside mechanical grinding. The probability distributions of the chip strength and the chip fragmentary pattern confirmed this relationship. When wafers were mechanically ground until they were 50-/spl mu/m thick, chip warpage was found to be oriented to the direction of the grinding marks. Meanwhile, by slowing the mechanical grinding speed by 50%, we were able to increase the average chip strength by 56%. Either plasma etching or polishing after mechanical grinding eliminated the weak regions, and the optimal amount of mechanical grinding and the polishing depths were observed, beyond which the chip strength would not increase. On the other hand, a preprocess for blunting a new saw blade for chip dicing was found to be essential as the chip strength increased five-fold, whereas increasing the dicing speed or using dual saw instead of a single saw had only small effects on the chip strength degradation.     

A low-complexity UWB RF receiver based on a novel low noise amplifier

A novel low-complexity ultra-wideband UWB receiver is proposed for short-range wireless transmission communications without considering multipath effect. The receiver chip uses a low-complexity UWB non-coherent receiving system solution with the core module composed of squarer and low-pass filter. By introducing asymmetric gate series inductance and RCL parallel negative feedback loop into the two-stage push–pull amplifier, the low-noise amplification and input impedance matching at ultra-wide bandwidth were achieved. With only two inductors and self-biased function, the chip area and power consumption can be saved largely. The proposed UWB receiver chip was fabricated in a 0.18 μm RF CMOS technology. Experimental results show that it can achieve a bandwidth of 3–5 GHz, maximum receiving symbol rate of 250 Mbps, receiving sensitivity of −80 dBm and power consumption of 36 mW, providing a low-complexity and high-speed physical implementation of the short-range high-speed wireless interconnection between electronic devices in the future.     

Very low noise photodetector system using p-i-n diode and baseband parametric upconvertor

The communication describes a sensitive photodetector system consisting of a p-i-n photodiode followed by a baseband parametric upconvertor. The overall noise performance is shown to be potentially better than that of existing avalanche photodiode systems.     

Electromigration reliability of interconnections in RF low noise amplifier circuit

With the continuous increase of the circuit complexity and the scaling down of the device size, electromigration (EM) failure in the interconnects has become the determining factor for circuit reliability. Most of the EM circuit simulators in the literature are at 2D level. The application of 2D simulators is limited as the actual physical implementation of the circuit in a wafer is indeed 3D in nature, and is much more complicated than 2D. In this paper, we construct a complete 3D circuit model of a RF low noise amplifier (LNA) circuit, including both the intra- and inter-block interconnects. Electric-thermal-structural simulations are performed and the modifications that help to enhance the EM reliability of the circuit are carried out based on the simulation results.     

A new method for on wafer noise measurement

A method for measuring the noise parameters of MESFETs and HEMTs is presented. It is based on the fact that three independent noise parameters are sufficient to fully describe the device noise performance. It is shown that two noise parameters, R_n and |Y_OPT|, can be directly obtained from the frequency variation of the noise figure F₅₀ corresponding to a 50 Ω generator impedance. By using a theoretical relation between the intrinsic noise sources as additional data, the F₅₀ measurement only can provide the four noise parameters. A good agreement with more conventional techniques is obtained     

Processing aspects in the low-frequency noise of nMOSFETs on strained-silicon substrates

The impact of different processing factors on the low-frequency (LF) noise of nMOSFETs fabricated in strained-silicon (SSi) substrates will be described. It is shown that the use of an SSi substrate can yield improved LF noise performance compared with standard Czochralski silicon material. This is demonstrated for both full-wafer and selective epitaxial SSi material. The lower 1/f noise points to an improved gate oxide quality, i.e., with a lower interface and bulk defect density, and is correlated with the low-field mobility or transconductance of the transistors. At the same time, it will be demonstrated that there exist defect-related LF noise mechanisms, which generally give rise to excess generation-recombination (GR) noise. Associated with this GR noise, a degradation of either the OFF-state leakage current or the mobility (transconductance) of the devices is observed. It is clear that noise is a sensitive parameter to local defectiveness and may be a useful tool for both materials' characterization and the analysis of processing-related device degradation mechanisms.     

Effect of body bias and temperature on low-frequency noise in 40-nm nMOSFETs

This study investigated the effects of temperature and body bias on drain current flicker noise (1/f) in 40-nm nMOSFETs. The 1/f noise is attributable to the charge number fluctuation correlating with the mobility fluctuation. At 300 K, as the depletion width was decreased, 1/f noise decreased with the body bias from − 0.5 to + 0.5 V in the weak inversion; conversely, 1/f noise was independent of the body bias because of the neglected depletion charge capacitance in the strong inversion. When the temperature was below 150 K, 1/f noise increased when the drain voltage was low because of the Fermi level toward the band edge, which has a higher trap density and corresponds to the inverse square of the subthreshold swing. However, when the drain voltage was high, 1/f noise was dominated by the mobility fluctuation because a wider strong inversion region at 150 K resulted in a lower 1/f noise and insignificant body effect. The analysis of this behavior in 40-nm devices may assist in determining the optimal device fabrication methods and circuit design.     

Thin oxide grown on heavily channel-implanted substrate by using a low temperature wafer loading and N2 pre-annealing process

In this paper, we present high integrity thin oxides grown on the channel implanted substrate (3 × 10¹⁷ cm⁻³) and heavily doped substrate (1 × 10²⁰ cm⁻³) by using a low-temperature wafer loading and N₂ pre-annealing process. The presented thin oxide grown on the channel implanted substrate exhibits a very low interface state density (1 × 10¹⁰ cm⁻² eV⁻¹) and a very high intrinsic dielectric breakdown field (15 MV/cm). It also shows a lower charge trapping rate and interface state generation rate than the conventional thermal oxide. For the thin oxide grown on the heavily-doped substrate by using the proposed recipe, the implantation-induced damage close to the silicon surface can be almost annealed out. The presented heavily-doped oxide shows much better dielectric characteristics, such as the dielectric breakdown field and the charge-to-breakdown, as compared to the conventional heavily-doped oxide.     

High-performance inductors on plastic substrate

Wafer-transfer technology (WTT) has been applied to transfer RF inductors from a silicon wafer to an opaque plastic substrate (FR-4). By completely eliminating silicon substrate, the high performance of integrated inductors (Q-factor > 30 for inductance /spl sim/3 nH with resonant frequency /spl sim/23 GHz) has been achieved. Based on the analysis of a modified /spl pi/-network model, our results suggest that the performance limitation is switched from being a synthetic mechanism of substrate and metal-ohmic losses on low resistivity Si-substrate to merely a metal-ohmic loss on FR-4. Thus, the inductor patterns, which are optimized currently for RFICs on silicon wafer, can be further optimized to take full advantage of the WTT on new substrate from the newly obtained design freedom.