On Design of Parallel Memory Access Schemes for Video Coding

Some of the modern powerful digital signal processors (DSPs) have byte-addressable internal data memory. This property is valuable especially in computationally demanding inter frame video encoding, where data accesses are typically unaligned according to word boundaries. The byte-addressable memory allows load or store command to start accessing from any byte-address, providing at most as many successive bytes from subsequent addresses as data bus can handle in parallel. Maybe the simplest way to construct such a byte-addressable memory is to use N 8-bit memory modules or banks to be accessed in parallel, when N is data bus width in bytes. However, in addition to byte-addressable subsequent bytes, memory consisting of parallel memory modules can provide much more versatile addressing capabilities with reasonable implementation cost. Versatile access formats can significantly reduce the need for data reordering in the register file. At first, we provide motivation for using parallel memory architecture with versatile access formats as an internal on-chip data memory of modern DSP. After this, notations are described and general view of parallel memory design is given. We propose some example parallel data memory architecture designs with data access formats especially helpful in H.263 encoding and MPEG-4 core profile motion and texture encoding. The examples are given for different data bus widths (16, 32, 64, and 128 bits). Finally, performance is shortly compared to other memory architectures and area, delay, and power figures are estimated.Jarno K. Tanskanen was born in Joensuu, Finland in 1975. He studied analog and digital electronics in the Department of Electrical Engineering, and computer architecture in the Department of Information Technology at Tampere University of Technology, where he received his M.Sc. degree in 1999. He is currently working as a research scientist in the Institute of Digital and Computer Systems at TUT. His Dr.Tech. research concerns parallel processing of video compression. jarno.tanskanen@tut.fiReiner Creutzburg received his Diploma in Mathematics in 1976 and attained his Ph.D. in Mathematics in 1984 from the Rostock University, Germany. Prof. Creutzburg has published 3 books, filed 2 patents, and produced approximately 100 articles, preprint, and conference papers. Professional Experience: Since 2000—Part-time Professor for Multimedia technology, Tampere University of Technology, Finland. Since 1992—Full-time Professor of Computer Science, Fachhochschule Brandenburg-University of Applied Sciences, Brandenburg, Germany. 1990 to 1992—Assistant Professor, University of Karlsruhe, Institute of Algorithms and Cognitive Systems, Germany. 1987 to 1989—Head of the Research Section Image Processing. 1986 to 1989—Founder and Head of the International Base Laboratory of Image Processing and Computer Graphics for East European countries at the Central Institute of Cybernetics and Information Processes of the Academy of Sciences (Berlin), Germany. 1976 to 1989—Researcher and Assistant Professor in various Universities and the Academy of Sciences, Central Institute of Cybernetics and Information, Berlin. creutzburg@fh-brandenburg.deJarkko T. Niittylahti was born in Orivesi, Finland, in 1962. He received the M.Sc, Lic.Tech, and Dr.Tech degrees at Tampere University of Technology (TUT) in 1988, 1992, and 1995, respectively. From 1987 to 1992, he was a researcher at TUT. In 1992–93, he was a researcher at CERN in Geneva, Switzerland. In 1993–95, he was with Nokia Consumer Electronics, Bochum, Germany, and in 1995–97 with Nokia Research Center, Tampere, Finland. In 1997–2000, he was a Professor at Signal Processing Laboratory, TUT, and in 2000–2002 at Institute of Digital and Computer Systems, TUT. Currently, he is a Docent of Digital Techniques at TUT and the managing director of Staselog Ltd. He is also a co-founder and President of Atostek Ltd. He is interested in designing digital systems and architectures. jarkko.niittylahti@tut.fi     

Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors

Upcoming multi-media compression applications will require high memory bandwidth. In this paper, we estimate that a software reference implementation of an MPEG-4 video decoder typically requires 200 Mtransfers/s to memory to decode 1 CIF (352×288) Video Object Plane (VOP) at 30 frames/s. This imposes a high penalty in terms of power but also performance.However, we also show that we can heavily improve on the memory transfers, without sacrificing speed (even gaining about 10% on cache misses and cycles for a DEC Alpha), by aggressive code transformations. For this purpose, we have manually applied an extended version of our data transfer and storage exploration (DTSE) methodology, which was originally developed for custom hardware implementations.     

AVS中的音视频编码压缩技术

介绍了音视频编码标准AVS中的主要技术特点,对AVS标准所采用的主要技术进行了综述,给出了AVS视频标准与MPEG-4 AVC/H.264编码器性能的比较和分析,讨论了AVS的发展前景.     

免疫算法

本文在分析标准遗传算法的优越性与存在不足的基础上,借鉴生命科学中免疫的概念与理论,提出了一种新的算法——免疫算法.该算法的核心在于免疫算子的构造,而免疫算子又是通过接种疫苗和免疫选择两个步骤来完成的.理论证明免疫算法是收敛的,并结合TSP问题,提出了免疫疫苗的选取与免疫算子的构造方法.最后,用免疫算法对75城市的TSP问题进行了仿真计算,并将其计算过程与标准遗传算法进行了对比,结果表明该算法对减轻遗传算法后期的波动现象具有明显的效果,同时使收敛的速度有较大的提高.     

一种快速的SVC多模式决策方法

H.264/AVC SVC为了提供一种可伸缩的视频编码解决方案,增加了许多宏块模式的组合,从而导致模式决策的计算量大幅度增加。本文提出了一种面向SVC的快速多模式决策算法,该方法首先利用模式在层间、帧间和空间的相关性,决定当前宏块的起始搜索模式,然后利用相邻运动向量的差异性决定是否合并或拆分当前分块进行细化搜索。从测试结果来看,本算法在率失真性能不降低的情况下,令模式决策的运算速度提高了数倍。     

基于内容的视频编码技术

介绍了基于内容的交互性及视频对象面（ＶＯＰ）的新概念,给出了一种基于内容的视频编码系统框架,并展望了基于内容的视频编码的应用前景。     

一种面向新一代可伸缩视频编码的上采样设计

可伸缩视频编码属于新一代H.265/HEVC视频编码标准中的关键技术。本文分析了其相关技术,针对传统空间可伸缩视频编码中的上采样过程运算复杂、时间延迟等缺点,借鉴双边滤波器,将内容自适应嵌入到上采样过程中,提出了一种新的非线性和内容自适应设计方法。通过理论推导得出了改进后滤波器的表示公式,并设计出了新的上采样实现流程。通过仿真实验验证了理论推导的正确性,并与传统方法进行了比较,结果表明该方法可有效地提高编码效率、降低系统复杂性。     

结合视频压缩编码的动态图像水印方案

本文提出了一种新的、结合视频压缩编码的动态图像水印方案。在嵌入水印时，充分考虑动态图像压缩编码的特性，对帧内编码帧(I帧)，将水印信息嵌入到DCT低额系数中；面对帧间编码帧(P、B帧)，结合动态补偿/离散余弦变换(MC/DCT)混合编码，把水印信息嵌入到运动补偿后的残差图象的直流成分中。同时，在水印嵌入时，采用扩频技术与多维水印相结合的方法，并通过相关检测的方法判断水印的存在。由于水印的检测是对视频码流直接实施的，不需要对压缩数据进行完全解码，从而大大降低了计算量，提高了视频数据水印的适用性。     

H.264并行视频编码的分配机制的研究

H.264作为新的视频压缩标准,采用了许多先进的算法,提供了很好的视频压缩质量。获得出色压缩效果和质量的代价是压缩编码算法复杂度的增加。为了寻求更高的编码速度,集群并行计算被运用到H.264的视频编码计算中。本文结合并行算法设计,通过对H.264视频编码的研究,分析了H.264可实现并行计算的任务单元选择;采用了片（Slice）级的H.264并行编码计算方法,并对其性能进行了测试和分析。     

一种新的渐进精细可分级编码算法

文中提出了一种新的渐进精强可分级编码算法.新算法利用基本层运动矢量在增强层进行小窗口搜索来获得更精确的增强层运动矢量,从而提高了原有算法增强层的预测精度.新算法继承了原有算法的所有优点.此仿真结果表明,在同样的码率下,新算法较原有算法的峰值信噪比提高了0.3～0.5dB.     

网络电视视频编解码主流标准的比较研究

网络电视视频编解码主流标准有MPEG-4、H.264与AVS等多种标准制式。本文在所用技术基础上从基本概念、技术特征差异分析和发展趋势等方面对这些标准进行了比较评价,并得出一些重要结论。对于我国网络电视标准选择的参考,是十分必要也是完全可行的。由于这些网络电视标准系统均未进入大规模商用,标准可能存在的一些问题和缺陷很难暴露,在这些标准的实施过程中也会逐步认识各种标准的不足之处。     

基于VC++的H.263到MPEG-4视频流转码的实现

在对H.263和MPEG-4两种视频编码标准以及几种常见转码器结构进行对比的基础上,基于VC++,在PC平台上实现了H.263到MPEG-4的转码系统.通过Foreman标准测试序列的码流进行转码测试,结果没有察觉图像失真,说明该方法能够达到较满意的效果.     

小波可分级视频编码技术综述

主要对小波图像视频可分级编码方法进行了分析和评述,并探讨了目前小波可分级视频编码技术的研究热点和今后的发展方向.     

Introduction to the High-Efficiency Video Coding Standard

The high-efficiency video coding(HEVC) standard is the newest video coding standard currently under joint development by ITU-T Video Coding Experts Group(VCEG) and ISO/IEC Moving Picture Experts Group(MPEG).HEVC is the next-generation video coding standard after H.264/AVC.The goals of the HEVC standardization effort are to double the video coding efficiency of existing H.264/AVC while supporting all the recognized potential applications,such as,video telephony,storage,broadcast,streaming,especially for large picture size video(4k × 2k).The HEVC standard will be completed as an ISO/IEC and ITU-T standard in January 2013.In February 2012,the HEVC standardization process reached its committee draft(CD) stage.The ever-improving HEVC standard has demonstrated a significant gain in coding efficiency in rate-distortion efficiency relative to the existing H.264/AVC.This paper provides an overview of the technical features of HEVC close to HEVC CD stage,covering high-level structure,coding units,prediction units,transform units,spatial signal transformation and PCM representation,intra-picture prediction,inter-picture prediction,entropy coding and in-loop filtering.The HEVC coding efficiency performances comparing with H.264/AVC are also provided.     

可分级视频编码差错控制技术综述

H.264/AVC视频压缩标准相比于H.263和MPEG-4,H.264,其压缩性能提高了近一倍,但H.264/AVC局限于传统的单层编码模式,即便在编解码两端添加差错控制措施,仍不足以达到在高丢包率信道下流畅清晰观看视频的要求。分析了SVC(可分级视频编码)在高丢包率信道下的容错性,较为详细地介绍了目前SVC中提出的一些容错编码以及差错掩盖的方法,并介绍了SVC差错控制技术的发展。     

基于模型的H263＋可扩展性编码

提出了基于模型的视频时空可扩展性编码方法,即根据人眼视觉敏感程度的不同,将视频中的每帧图象根据模型划分为程度不同的区域,对每一个区域分配不同的时间和空间分辨率,以期在极低码率的传送环境中保证人眼敏感区域的图象质量和传送效率。     

可伸缩视频编码标准中的差错控制

可伸缩视频编码标准（SVC）是由ISO/IEC的MPEG专家组和ITU-T的VCEG专家组联合组成的联合视频专家组制定的对H.264/AVC视频编码标准的可伸缩性扩展。SVC通过对时间分辨率、空间分辨率和质量等参数的可伸缩性来适应不同网络环境下用户对视频资料的分辨率、帧率、质量的不同需求,是目前解决这一问题的最好方法之一。由于信道传输中大量存在的衰减、误码和数据丢失,差错控制显得十分重要,因而两种有效的对抗措施——错误弹性编码和错误隐藏技术被引入到SVC中：一部分是直接从H.264中继承而来;还有一部分则是利用了可伸缩视频的自身特性而提出的。文中将对SVC中一些有代表性的错误弹性和错误隐藏技术进行介绍,并给出部分实验结果来展示这些技术带来的性能提升。     

变码率MPEG-2视频编码的统计特性及数据分割可分级的新方法

本文研究了变码率ＭＰＥＧ－２视频编码的统计特性，认为基于条带的统计分析方法能更好地描述视频序列的特性。本文同时提出了一种按照图像编码类型的可分级数据分割新方法，该方法降低了基本层流量的变化，减少了带宽需求，并能提供良好的主观图像质量。     

非扩展性与可扩展性视频编码流式技术

介绍面向存储的非扩展性视频编码和面向传输的可扩展性视频编码及其网络传输技术 ,以及它们在网络上应用时各自存在的优点和缺点