Out-of-Order Execution in Sequentially Consistent Shared-Memory Systems:Theory and Experiments

Traditional implementation of sequential consistency in shared-memory systems requires memory accesses to be globally performed in program order.Based on an event ordering model for correct executions in shared-memory systems,this paper proposes and proves that out-of-order execution does not influence the correctness of an execution providing certain condition is met.Simulation results show that out-of-order execution proposed in this paper is an effective way to improve the performance of a sequentially consistent shared-memory system.     

顺序一致共享存储系统中的乱序执行技术——基本理论

本文首先研究了共享存储系统中的访存事件及其发生次序，从访存事件次序的角度建立了顺序一致性共享存储系统行正确性模型，然后在执行正确性模型的基础上，提出并证明了一种乱序列执行的方案，根据这个方案，只要满足一定条件，取数操作就可以越过它前面的访存操作执行而不影响系统的正确性。     

Formal Verification of Out-of-Order Execution with Incremental Flushing

We present an approach for formally verifying that a high-level microprocessor model behaves as defined by an instruction-set architecture. The technique is based on a specialization of self consistency called incremental flushing and reduces the need and effort required to create manually-generated implementation abstractions. Additionally, incremental flushing reduces the computational complexity of the proof obligations generated when reasoning about out-of-order execution. This is accomplished by comparing the functional behavior of the implementation abstraction over two sets of inputs: one that represents normal operation and one that is simpler, but functionally equivalent. The approach is illustrated on a simple out-of-order microprocessor core.     

Verification of FM9801: An Out-of-Order Microprocessor Model with Speculative Execution, Exceptions, and Program-Modifying Capability

We have verified the FM9801, a microprocessor design whose features include speculative execution, out-of-order issue and completion of instructions using Tomasulo's algorithm, and precise exceptions and interrupts. As a correctness criterion, we used a commutative diagram that compares the result of the pipelined execution from a flushed state to another flushed state with that of the sequential execution. Like many pipelined microprocessors, the FM9801 may not operate correctly if the executed program modifies itself. We discuss the condition under which the processor is guaranteed to operate correctly. In order to show that the correctness criterion is satisfied, we introduce an intermediate abstraction that records the history of executed instructions. Using this abstraction, we define a number of invariant properties that must hold during the operation of the FM9801. We verify these invariant properties, and then derive the proof of the commutative diagram from them. The proof has been mechanically checked by the ACL2 theorem prover.     

顺序一致共享存储系统中的乱序执行技术——模拟实现

在文献（４）中，我们从理论上提出并证明了顺序一致共享存储系统的一种乱序执行方案本文讨论该乱序执行方案的实现策略并建立了一个地址流驱动（Ｔｒａｃｅ－ｄｒｉｖｅｎ）的模拟模型来评估乱序执行对性能的影响，模拟结果表明，乱序执行能有效地提高顺序一致共享存储系统的性能。     

Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology

This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bitsliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.     

多任务CAD系统的执行中心模型

针对直接操纵的多任务CAD系统的实时反馈、并发对话等需求,提出CAD 系统的基于事件驱动的层次化执行中心模型EDHM。该模型遵循对话独立性原则,将执行中心划分为3个层次5大部件,支持连续语义反馈和异步并发对话,并以统一的框架支持顺序和异步交织的交互风格。此模型已被应用到多任务CAD支撑系统OpenDesign的执行中心构造中。实践表明,基于EDHM模型建立的执行中心满足直接操纵和多进程的需求,具有结构上的独立性,易于移植和封装复用。     

Y-Invalidate: A New Protocol for Implementing Weak Consistency in DSM Systems

In this work we propose and implement a new variant of the well-known write invalidate protocol called Y-invalidate. Whereas the former protocol required that every copy of a page be invalidated every time that page is updated, our variant invalidates a copy of a page at process A only at the next synchronization point which is relevant to Aand or if the copy was modified by the owner's process after the page was copied to A. We thus avoid invalidating copies of pages that were modified but never read after modification, and avoid, of course, the associated overhead. Y-Invalidate is basically a weak-consistency protocol. Its main advantage is that it implements weak consistency without the need to merge copies of a page that were updated in different machines. To the best of our knowledge, this is the first variant of weak consistency protocols which does not merge multiple copies of pages. Unlike other variants of weak consistency, Y-invalidate supports implicit synchronization points in the program by invalidating copies of shared memory pages that are referenced by while-loops. In this way, Y-invalidate approximates strict consistency. The Y-invalidate protocol was implemented in the ParC system, which is a powerful parallel extension of the C language. The ParC compiler was modified to detect some of the implicit synchronization points in the source code. Experimental results show significant improvement compared to both the traditional write-invalidate protocol and weak consistency.     

A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory

The on-chip memory performance of embedded systems directly affects the system designers＇ decision about how to allocate expensive silicon area. A novel memory architecture, flexible sequential and random access memory （FSRAM）, is investigated for embedded systems. To realize sequential accesses, small “links”are added to each row in the RAM array to point to the next row to be prefetched. The potential cache pollution is ameliorated by a small sequential access buyer （SAB）. To evaluate the architecture-level performance of FSRAM, we ran the Mediabench benchmark programs on a modified version of the SimpleScalar simulator. Our results show that the FSRAM improves the performance of a baseline processor with a 16KB data cache up to 55%, with an average of 9%; furthermore, the FSRAM reduces 53.1% of the data cache miss count on average due to its prefetching effect. We also designed RTL and SPICE models of the FSRAM, which show that the FSRAM significantly improves memory access time, while reducing power consumption, with negligible area overhead.     

可信执行环境访问控制建模与安全性分析

可信执行环境(TEE)的安全问题一直受到国内外学者的关注. 利用内存标签技术可以在可信执行环境中实现更细粒度的内存隔离和访问控制机制, 但已有方案往往依赖于测试或者经验分析表明其有效性, 缺乏严格的正确性和安全性保证. 针对内存标签实现的访问控制提出通用的形式化模型框架, 并提出一种基于模型检测的访问控制安全性分析方法. 首先, 利用形式化方法构建基于内存标签的可信执行环境访问控制通用模型框架, 给出访问控制实体的形式化定义, 定义的规则包括访问控制规则和标签更新规则; 然后利用形式化语言B以递增的方式设计并实现该框架的抽象机模型, 通过不变式约束形式化描述模型的基本性质; 再次以可信执行环境的一个具体实现TIMBER-V为应用实例, 通过实例化抽象机模型构建TIMBER-V访问控制模型, 添加安全性质规约并运用模型检测验证模型的功能正确性和安全性; 最后模拟具体攻击场景并实现攻击检测, 评估结果表明提出的安全性分析方法的有效性.     

分布式共享存储系统中的存储管理及优化技术

分布式共享存储体系结构由于结合了较好的可扩展性和可编程性，已经成为目前并行计算机领域的主要发展方向。文章针对分布式共享存储系统中存储管理的两个关键问题——存储一致性模型和数据局部性优化技术进行了探讨。     

Efficient Deterministic and Probabilistic Simulations of PRAMs on Linear Arrays with Reconfigurable Pipelined Bus Systems

In this paper, we present deterministic and probabilistic methods for simulating PRAM computations on linear arrays with reconfigurable pipelined bus systems (LARPBS). The following results are established in this paper. (1) Each step of a p-processor PRAM with m=O(p) shared memory cells can be simulated by a p-processors LARPBS in O(log p) time, where the constant in the big-O notation is small. (2) Each step of a p-processor PRAM with m=(p) shared memory cells can be simulated by a p-processors LARPBS in O(log m) time. (3) Each step of a p-processor PRAM can be simulated by a p-processor LARPBS in O(log p) time with probability larger than 1–1/p^c for all c>0. (4) As an interesting byproduct, we show that a p-processor LARPBS can sort p items in O(log p) time, with a small constant hidden in the big-O notation. Our results indicate that an LARPBS can simulate a PRAM very efficiently.     

Effect of fault distribution and execution patterns on fault exposure in software: a simulation study

Execution patterns and fault distribution characteristics of a program will affect the failure process and thus reliability estimates. The failure process of a software system is influenced by many factors, and traditional software reliability engineering has found it difficult to isolate the effect of each individual factor. A simulation approach is used to investigate the effects of fault distribution, execution pattern and program structure on software reliability estimates. A reliability simulation environment (RSIM) is extended by introducing variable fault distribution patterns in its code generation phase. Flow control points allow varying the execution frequency of different parts of a program. The simulation results show that fault distribution patterns and execution patterns have dramatic effects on fault exposure rate. If the fault distribution is non‐uniform, a non‐uniform code execution exposes faults more efficiently and effectively than uniform execution. Results also show that the structure of a program affects fault exposure rate and testing time required. Copyright © 2000 John Wiley & Sons, Ltd.     

动态数组在系统可靠性与维修性仿真中的应用

系统可靠性与维修性仿真属于离散事件仿真的范畴。针对可靠性与维修性仿真过程中可能涉及大量的随机变量的问题，论述了利用动态数据结构提高仿真运行的效率和扩大仿真解题规模的可能性。并以Turbo C为背景，讨论了动态数组的建立、动态内存的管理以及动态数组的使用方法，给出了动态数组在系统可靠性与维修性仿真中的应用。     

Developing a Theory to Explain the Insights Gained Concerning Information Systems and Business Process Behaviour: The ASSESS-IT Project

Business Process (BP) literature promotes the value of business processes as essential gearwheels that help organisations to reach their goals. Similarly, many process design approaches claim that information technology is a major enabler of business process, a view also shared by the Information Systems (IS) community. Despite this, BP and IS approaches do not provide clear guidance on how to coordinate the design of BP and IS. Nor is any indication of which modelling techniques could be used to detect and design IT opportunities within a business process context given.The ASSESS-IT project examined this domain and proposed the use of simulation techniques to achieve BP and IT integration. The outcome of this project gave indication that depicting the dynamic behaviour of IS could be very helpful for BP modellers to predict the impact that the insertion of IS may have on organisational processes. This paper proposes a simulation framework to depict IS behaviour within a BP simulation model, namely BPS/ISS, and tests it using the case study that was part of the ASSESS-IT project.     

A process-oriented methodology for evaluating the impact of IT: A proposal and an application in healthcare

In order to improve the performance of business processes often Information Technologies (ITs) are introduced. However, business processes are known to be complex and distributed among multiple business entities. As a result, the impact of new IT on an entire business process is typically hard to assess as quantitative methods for evaluation are missing. Therefore, in this paper, we propose a process-oriented methodology for evaluating the impact of IT on a business process ahead of its implementation. In our method, process mining and discrete event simulation are key ingredients. Based on automatically stored data, process mining allows for obtaining detailed knowledge on a business process, e.g., it can be discovered how a business process is actually executed. Using discrete event simulation, a model can be built which accurately mimicks the discovered process and which can subsequently be used for exploring and evaluating various redesign of the same process.     

PRAM programming: in theory and in practice

That the influence of the PRAM model is ubiquitous in parallel algorithm design is as clear as the fact that it is technologically infeasible for the forseeable future. The current generation of parallel hardware prominently features distributed memory and high‐performance interconnection networks—very much the antithesis of the shared memory required for the PRAM model. It has been shown that, in spite of communication costs, for some problems very fast parallel algorithms are available for distributed‐memory machines—from embarassingly parallel problems to sorting and numerical analysis. In contrast it is known that for other classes of problem PRAM‐style shared‐memory simulation on a distributed‐memory machine can, in theory, produce solutions of comparable performance to the best possible for such architectures. The Bulk Synchronous Parallel (BSP) model accurately represents most parallel machines—theoretical and actual—in an execution and cost model. We introduce a scalable portable PRAM realization appropriate for BSP computers and a methodology for usage. Our system is fast and built upon the familiar sequential C++ coupled with the new standard BSP library of parallel computation and communication primitives. It is portable to and predictable on a vast number of parallel computers including workstation clusters, a 256‐processor Cray T3D, an 8‐node IBM SP/2 and a 4‐node shared‐memory SGI Power Challenge machine. Our approach achieves simplicity of programming over direct‐mode BSP programming for reasonable overhead cost. We objectively compare optimized BSP and PRAM algorithms implemented with our C++ PRAM library and provide encouraging experimental results for our new style of programming. Copyright © 2000 John Wiley & Sons, Ltd.     

On the machining induced residual stresses in IN718 nickel-based alloy: Experiments and predictions with finite element simulation

Residual stresses after machining processes on nickel-based super alloys is of great interest to industry in controlling surface integrity of the manufactured critical structural components. Therefore, this work is concerned with machining induced residual stresses and predictions with 3-D Finite Element (FE) based simulations for nickel-based alloy IN718. The main methods of measuring residual stresses including diffraction techniques have been reviewed. The prediction of machining induced stresses using 3-D FE simulations and comparison of experimentally measured residual stresses for machining of IN718 have been investigated. The influence of material flow stress and friction parameters employed in FE simulations on the machining induced stress predictions have been also explored. The results indicate that the stress predictions have significant variations with respect to the FE simulation model and these variations can be captured and the resultant surface integrity can be better represented in an interval. Therefore, predicted residual stresses at each depth location are given in an interval with an average and standard deviation.     

Atomic-level molecular modeling of the nonionic surfactant Triton X-100: the OPE9 component in vacuum and water

The commercially available nonionic surfactant Triton X-100 is a mixture of polyoxyethylene tert-octylphenyl ethers (OPE_n) with an average of n = 9.5 oxyethylene (OE) units in the molecules, and the population maximum at n = 9. Thus, the OPE_{n = 9} component was chosen to be studied by atomic level molecular modeling, using second-generation force fields. The 1,000 conformers generated via random sampling of torsional angles around single bonds yielded 11 clusters based on geometrical similarity. Representatives of geometrically distinctly different clusters with significant populations were chosen from a narrow energy range around the most probable energy to be analyzed for interaction with water. The effect of water on the conformation of the OE chain was found to be modest, similar to the situation that had been reported earlier for the anionic surfactant Aerosol-OT (AOT). The number of bound water molecules is strongly dependent on the conformation of the OE chain and is affected by electrostatic as well as steric effects. Unlike the case of AOT, for which the length of the hydrophobic tail was found to govern the size of reverse micelles in CCl₄, the size of reverse micelles of OPE_{n = 9} cannot be predicted from the dimensions of the hydrophilic tail.     

How to stimulate the continued use of ICT in higher education: Integrating Information Systems Continuance Theory and agency theory

This study examines the motivations underlying teachers’ intention to continue using information and communication technology (ICT) in higher education. In an extended model based on Information Systems Continuance Theory (ISCT) and agency theory (PAT), teachers’ continuance intention is theorized as a function of their perceived usefulness of ICT and confidence in the effect of incentive structures. The research model was analyzed using structural equation modeling (SEM) with LISREL, and seven out of eight hypotheses were supported. By combining the two theories, the paper fills a gap in the literature by addressing both personal and managerial perspectives. Thus, the study contributes to Information Systems continuance research by theorizing and validating an extended model that integrates two complementary perspectives and by explaining the interrelationships between these perspectives. Finally, the theoretical and practical implications are presented and discussed, and suggestions for future research are provided.