片上网络体系结构的研究与进展

片上网络(NoC)是基于多处理器技术的一种新型的计算集成形式，涉及硬件通信结构、中间件、操作系统通信服务、设计方法及工具等。NoC体系结构的设计重点是实现低功耗和高效通信/计算能力。该文介绍了4种新的NoC体系结构，并在同等约束下进行了功耗比较，2D网格结构的功耗最大、性能最差，聚合环面网络结构则最优。     

基于蚁群优化算法的NoC映射

功耗问题正逐渐成为NoC领域的研究热点,很多研究人员都在研究NoC功耗最小化的设计技术。文章采用一种有效的蚁群优化算法实现了NoC映射：在自动映射处理单元的同时,尽可能地减少了系统的通讯功耗。实验结果表明采用蚁群优化算法可以很快地收敛;针对不同的应用,可以减少25％-70％通讯功耗。     

基于改进遗传算法的3DNoC低功耗映射研究

二维片上网络（Two-Dimensional Network-on-Chip,2D NoC）在面积、功耗、布局布线、封装密度等方面都已达到了瓶颈。与2D NoC相比,三维片上网络（Three-dimensional Network-on-Chip,3D NoC）有着诸多优势,因此3D NoC逐渐成为一个重要的研究方向。随着3D NoC集成度的提高,低功耗映射逐渐成为研究热点。将贪心算法的思想与遗传算法相结合提出一种改进的遗传算法,用以解决3D NoC低功耗映射问题,相对于传统遗传算法,改进遗传算法具有更优的搜索能力。仿真结果表明,采用改进后的遗传算法解决3D NoC映射问题可以降低功耗,从总体趋势来看随着处理单元数量的增加功耗降低幅度逐渐增大,在120个处理单元情况下总功耗可降低14%。     

延迟优化的片上网络低功耗映射*

片上网络（NoC）是解决传统基于总线的片上系统（SoC）所面临的功耗、延迟、同步和信号完整性等挑战的有效解决方案。功耗和延迟是NoC设计中的重要约束和性能指标,在设计的各个阶段都存在着优化空间。基于蚁群优化算法,通过通信链路上并发通信事件的均匀分布来降低NoC映射阶段的功耗和延迟。仿真实验表明,与链路通信量负载均衡的方法相比,该方案能进一步在拓扑映射阶段优化功耗和延迟。     

基于云自适应遗传算法的NoC映射研究

NoC映射是NoC设计中的重要步骤,映射结果的优劣对NoC的QoS约束和通信功耗有着很大的影响。提出一种采用云自适应遗传算法实现NoC映射的方案,该算法利用云模型对传统遗传算法加以改进,以此新方法自动调整遗传算法过程中的交叉概率和变异概率,从而达到优化遗传算法的目的。结合NoC映射中的具体问题,在功耗和延时约束的限制条件下,建立了延时约束下的NoC映射功耗数学模型。实验表明,该方法在NoC映射中取得了良好的效果,降低了通信功耗。     

基于Innovus的低功耗物理设计

为了减少芯片功耗,可靠的低功耗物理设计必不可少。基于新一代布局布线工具Innovus,分四个部分阐述了新的低功耗物理设计流程。这些内容包括:基于低功耗的物理库设计;低功耗布局和优化、基于输入向量的功耗优化;低功耗时钟树协同设计CCOPT(clock concurrent optimization);时钟树后低功耗优化。Innovus作为Cadence全新的布局布线工具,提供基于Giga Opt引擎的功耗驱动优化和高级时钟树协同优化(CCOPT)等方法,有效帮助设计者实现低功耗芯片设计。全新的低功耗物理设计可改善芯片数字逻辑15%功耗。     

二次改进遗传算法与3D NoC低功耗映射

随着集成电路技术的迅速发展,芯片的集成度不断提高,片上众多处理单元间的高效互连成为关键问题,因而相继出现了片上系统(system-on-chip,SoC)和二维片上网络(two-dimensional network-on-chip,2D NoC).当二维片上网络在多方面达到瓶颈时,三维片上网络(three-dimensional network-on-chip,3D NoC)应运而生.三维片上网络已引起学术界和产业界的高度重视,三维片上网络低功耗映射是其中的1个关键问题.之前的研究曾提出过一种基于改进遗传算法的3D NoC低功耗映射算法,并收到了良好的仿真效果.但当问题规模变大时,计算量随之增大、运行效率明显降低.针对这一问题,对3D NoC中面向功耗优化的二次改进遗传算法任务映射机制进行研究,提出了一种新的3D NoC低功耗映射算法,并对该映射算法进行了仿真实验.实验结果表明,在种群规模较大的条件下,该算法不仅能够继续降低功耗,而且能够大幅度地减少映射算法的运行时间.     

IXP 2400网络处理器低功耗技术应用研究

文章从软件低功耗优化角度,结合IXP2400网络处理器中XScalecore处理器体系结构的低功耗技术特点,在SimWattch模拟平台上,就频率动态调整和程序设计语言不同结构成分对应用程序运行功耗的影响进行了模拟和分析,通过对一组Banchmark程序的模拟,结果表明在编译系统、操作系统或应用程序设计中采用这些低功耗优化技术设计可降低至少23%以上的运行功耗。     

片上网络的低功耗自适应数据保护

针对片上网络(NoC)提出了一种低功耗自适应数据保护机制。根据不同的片上网络通信链路错误数目自适应选择，在路由节点之间进行数据保护的跳距，保证了系统芯片功耗效率最优化。实验结果证明，在同样的可靠约束条件下，采用自适应数据保护，其功耗低于节点到节点，端到端的数据保护，特别是对需要高可靠性的NoC通信结构，自适应数据保护机制表现得更为有效。     

多核、多线程处理器的低功耗设计技术研究

随着微处理器设计技术和半导体制造工艺的进步，芯片的规模和复杂度急剧增大，超高的功耗密度对系统稳定性造成很大影响，功耗壁垒已经成为提升微处理器性能的最大障碍。本文介绍了低功耗设计的基本原理、研究内容、设计方法，分析了CMP和SMT体系结构的功耗需求和特性，讨论了不同的功耗优化策略在两种体系结构下的适用程度以及对性能造成的影响。针对多核、多线程体系结构，着重从系统级、结构级和电路级等不同抽象层次对典型的功耗优化技术做了讨论。最后，展望了未来微处理器低功耗设计技术的发展趋势。     

Energy-efficient NoC with multi-granularity power optimization

As the core count grows rapidly, NoC (Network-on-Chip) consumes an increasing fraction of the modern processors/SoCs (System-on-Chips) power. It is thus very important to design energy-efficient NoC architecture. Multi-NoC (Multiple Network-on-Chip) has demonstrated its advantages in power gating for reducing leakage power, which constitutes a significant fraction of NoC power. In this paper, we propose Chameleon, a novel heterogeneous Multi-NoC design. Chameleon employs a fine-grained power gating algorithm which exploits power saving opportunities at different levels of granularity simultaneously. Integrated with a congestion-aware traffic allocation policy, Chameleon is able to achieve both high performance and low power at varying network utilization. Our experimental results on both synthetic and real workloads show that Chameleon delivers an average of 2.61 % higher performance than Catnap, the best in the literature. More importantly, Chameleon consumes an average of 27.75 % less power than Catnap.     

NoC节点编码及路由算法的研究

NoC的设计和实现受到芯片的面积、功耗、深亚微米效应的限制.将拓扑结构和节点编码相结合,提出一种基于约翰逊码的二维平面编码.该编码隐含了Torus网络拓扑结构以及网络节点之间的连接关系并且有很好的扩展性,能够简化Torus拓扑结构上路由算法的实现和降低硬件成本.基于此编码和利用X-Y路由的路由确定性特点,提出改进X-Y路由,在中间节点只需要3或5个逻辑运算,降低路由的计算复杂性和硬件成本.最后,进行了节点结构设计.提出的编码不仅用于NoC的路由方面而且在NoC任务映射方面有重要应用.     

Multi-hop communications on wireless network-on-chip using optimized phased-array antennas

Network-on-Chip (NoC) as a promising design approach for on-chip interconnect fabrics could overcome the energy as well as synchronization challenges of the conventional interconnects in the gigascale System-on-Chips (SoC). The advantages of communication performance of traditional wired NoC will no longer be continued by the future technology scaling. Packets that travel between distant nodes of a large scale wired on-chip network significantly suffer from energy dissipation and latency due to the routing overhead at each hop. According to the International Technology Roadmap for Semiconductors annual report, the RFCMOS characteristics will be steadily improved by technology scaling. As the operating frequency of RF devices increases, the size of Si integrated antenna will decrease and it is feasible to employ them as a revolutionary interconnect for intra-chip wireless communications. In this paper, we focus on physical requirements and design challenges of wireless NoC. It is demonstrated that employing an optimum-radiation phased array antenna and multihop communications will increase the reliability of on-chip wireless links by several orders of magnitude using a limited power budget less than 0.1 pJ/bit.     

支持存储访问的NoC模拟器的设计与实现

随着片上网络的发展,片上多处理器系统通信性能提高的同时,存储器的访问性能将成为片上多处理器系统的性能瓶颈.目前片上网络的研究主要依赖于模拟器,而现有的片上网络模拟器都不能完成对存储器访问的准确模拟.本文设计并实现了一个能对存储器访问进行模拟的模拟器,为存储器性能的研究提供了一个实验平台;论文通过采用大量访问集对该模拟器进行测试,得出了若干条与存储器访问性能优化相关的片上网络设计建议.     

Problems and challenges of emerging technology networks−on−chip: A review

Networks−on−chip (NoC) are an alternative to alleviate the problems of legacy interconnect fabrics. However, many emerging technology NoC are developed and are now seen as their potential substitutes. In this context, this work introduces how the NoC industry is involved in the NoC technology design−trends and promotion. Secondly, an extensive discussion on the outstanding research problems and challenges for conventional and emerging technology NoC is developed. The related security concerns are particularly investigated.     

An efficient numerical-based crosstalk avoidance codec design for NoCs

With technology scaling, crosstalk fault has become a serious problem in reliable data transfer through Network on Chip (NoC) channels. The effects of crosstalk fault depend on transition patterns appearing on the wires of NoC channels. Among these patterns, Triplet Opposite Direction (TOD) imposes the worst crosstalk effects. Crosstalk Avoidance Codes (CACs) are the overhead-efficient mechanisms to tackle TODs. The main problem of CACs is their high imposed overheads to NoC routers. To solve this problem, this paper proposes an overhead-efficient coding mechanism called Penultimate-Subtracted Fibonacci (PS-Fibo) to alleviate crosstalk faults in NoC wires. PS-Fibo coding mechanism benefits the novel numerical system that not only completely removes TODs but also, is applicable to a wide range of NoC channel widths. The PS-Fibo coding mechanism is evaluated using BookSim-2 and VHDL-based simulations in the terms of codec efficiency on the crosstalk fault reduction, codec power consumption, codec area occupation and network performance. Evaluation results, carried out for a wide range of NoC channel widths indicate that PS-Fibo can improve power consumption and area occupations of codec and NoC performance with respect to the other state-of-the-art coding mechanisms.     

A novel 3D NoC architecture based on De Bruijn graph

Networks on Chip (NoC) and 3-Dimensional Integrated Circuits (3D IC) have been proposed as the solutions to the ever-growing communication problem in System on Chip (SoC). Most of contemporary 3D architectures are based on Mesh topology, which fails to achieve small latency and power consumption due to its inherent large network diameter. Moreover, the conventional XY routing lacks the ability of fault tolerance. In this paper, we propose a new 3D NoC architecture, which adopts De Bruijn graph as the topology in physical horizontal planes by leveraging its advantage of small latency, simple routing, low power, and great scalability. We employ an enhanced pillar structure for vertical interconnection. We design two shifting based routing algorithms to meet separate performance requirements in latency and computing complexity. Also, we use fault tolerant routing to guarantee reliable data transmission. Our simulation results show that the proposed 3D NoC architecture achieves better network performance and power efficiency than 3D Mesh and XNoTs topologies.     

用NS2评估片上网络体系结构的性能

随着SoC复杂度的不断提高,总线互连结构面临着越来越严峻的挑战,因此,以网络互连为特点的NoC应运而生。分析了影响NoC性能的几项重要指标,并用网络仿真软件NS2对几种常用拓扑结构的几项性能参数进行了评估,得出了在进行NoC设计时的指导性结论：结合具体的设计,对传输延迟、吞吐量、面积、功耗和可重用性等性能参数进行折衷考虑后选取合适的体系结构。     

基于多FPGA的NoC多核处理器验证平台设计

为了能够灵活地验证和实现自主设计的基于NoC的多核处理器,缩短NoC多核处理器的设计周期,提出了设计集成4片Virtex-6-550T FPGA的NoC多核处理器原型芯片设计/验证平台.分析和评估了NoC多核处理器的规模以及对FPGA硬件资源的需求,在此基础上给出了集成4片FPGA的开发板详细设计方案,并对各主要模块如互联架构、电源、板级时钟分布、接口技术、存储资源等关键设计要点进行阐述.描述了开发板各个主要模块的测试过程和结果,表明了该设计的可行性.