A 1-V, 8-bit successive approximation ADC in standard CMOS process

A 1-V 8-bit 50-kS/s successive approximation analog-to-digital converter (ADC) implemented in a conventional 1.2-μm CMOS process is presented. Low voltage, large signal swing sample-and-hold, and digital-to-analog conversion are realized based on inverting op-amp configurations with biasing currents added to the op-amp negative input terminal so that the op-amp input common-mode voltages can be biased near ground to minimize the supply voltage. At the same time, the input and output quiescent voltages can be set at half of the supply rails. A low-voltage latched comparator is realized based on the current-mode approach. The entire ADC including all the digital circuits consumes less than 0.34 mW. An effective number of bits of 7.9 was obtained for a 1-kHz 850-mV peak-to-peak input signal     

Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters

This paper discusses the design, analysis and performance of a low-voltage, highly linear switched-R-MOSFET-C filter. High linearity, even at a low supply voltage, is achieved through the use of duty-cycle-controlled tuning. Tuning MOSFETs are switched completely on while conducting, such that their nonlinear resistance is much smaller than the linear filter resistors, resulting in low distortion. The MOSFETs are also placed inside the filter feedback loop which further reduces distortion. Because tuning is done in the time domain, rather than in the voltage domain, the tuning range is independent of the supply voltage. The filter achieves -77 dB total harmonic distortion (THD) using a 0.6-V supply, and -90 dB THD using a 0.8-V supply, with a 0.6-Vpp differential 2 kHz sine input. The prototype IC, implemented in a 0.18-mum CMOS process, occupies an area of 0.7 mm² and consumes 1 mW of power from a 0.6-V supply.     

Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward

This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Measurements results for a 0.35-m CMOS design show a 1:2 tuning range with total harmonic distortion figures at 10 MHz below 58 dB over the whole range up to a 200- differential output current. The proposed cell consumes less than 1.1 mW from a single 1.8-V supply.     

Digital frequency and Q tuning technique for low-voltage activefilters

A digital frequency and Q tuning technique is proposed for low-voltage (1 V) active RC biquad filters that uses programmable capacitor arrays (PCAs). The proposed technique does not require any peak detectors, which are difficult to implement at low voltages. Instead, it uses a small number of analogue comparators, a digital comparator and binary counters to adjust the PCAs     

A feedforward technique with frequency-dependent current mirrorsfor a low-voltage wideband amplifier

A feedforward technique using frequency-dependent current mirrors for a low-voltage wideband amplifier is presented. In the conventional single-stage wideband amplifiers, the folded cascode structure is used. However, the common-gate transistor requires an additional V_{DS sat} and reduces the available output voltage range. In this study the cascode structure is avoided; instead, a frequency-dependent current mirror, whose input impedance becomes higher for a higher frequency, is used to form the feedforward path from the input of the current mirror with a feedforward capacitor. This technique is effective to improve a 100 MHz-1 GHz frequency characteristic of the amplifier. The amplifier has been fabricated using the standard 0.8 μm CMOS process. The phase margin is improved from 46-66° without sacrificing the unity gain frequency of 133 MHz compared with the amplifier without this technique. The amplifier operates at 2.5 V power supply voltage and consumes 12 mW     

5.7 GHz low-power variable-gain LNA in 0.18 /spl mu/m CMOS

A variable-gain low-noise amplifier (LNA) suitable for low-voltage and low-power operation is designed and implemented in a standard 0.18 /spl mu/m CMOS technology. With a current-reused topology, the common-source gain stages are stacked for minimum power dissipation while achieving high small-signal gain. The fully integrated 5.7 GHz LNA exhibits 16.4 dB gain, 3.5 dB noise figure and 8 dB gain tuning range with good input and output return losses. The LNA consumes 3.2 mW DC power from a supply voltage of 1 V. A gain/power quotient of 5.12 dB/mW is achieved in this work.     

High-Precision Differential-Input Buffered and External Transconductance Amplifier for Low-Voltage Low-Power Applications

Recently, the demand for low-voltage low-power integrated circuits design has grown dramatically. For battery-operated devices both the supply voltage and the power consumption have to be lowered in order to prolong the battery life. This paper presents an attractive approach to designing a low-voltage low-power high-precision differential-input buffered and external transconductance amplifier, DBeTA, based on the bulk-driven technique. The proposed DBeTA possesses rail-to-rail voltage swing capability at a low supply voltage of ±400 mV and consumes merely 62 μW. The proposed circuit is a universal active element that offers more freedom during the design of current-, voltage-, or mixed-mode applications. The proposed circuit is particularly interesting for biomedical applications requiring low-voltage low-power operation capability where the processing signal frequency is limited to a few kilohertz. An oscillator circuit employing a minimum number of active and passive components has been described in this paper as one of many possible applications. The circuit contains only a single active element DBeTA, two capacitors, and one resistor, which is very attractive for integrated circuit implementation. PSpice simulation results using the 0.18 μm CMOS technology from TSMC are included to prove the unique results.     

A Millimeter-Wave 90-nm CMOS Self-Mixing Frequency Divider

This letter presents a millimeter-wave 90 nm CMOS divide-by-four frequency divider using self-mixing technique. The output of the push-push oscillator mixes with the input signal, and the resulting intermediate frequency signal locks the fundamental oscillation frequency of the oscillator at exactly one-fourth of the input signal frequency. The frequency divider is implemented in TSMC 90 nm 1P9M digital CMOS technology and the overall die size is 0.91 mm $times,$ 0.53 mm. For low-power mode, the divider consumes only 0.8 mW with a 0.8 V supply voltage, and the measured locking range is 300 MHz. For normal mode, the divider consumes 2 mW with a 1 V supply, and the locking range is extended to 1100 MHz. The operating range of the divider covers from 46.1 to 52.8 GHz with varactor tuning and band switching.      

A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators

A low-voltage fourth-order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled inductors, thus providing bandwidth tuning with small passband ripple. Each resonator is built using on-chip spiral inductors and accumulation-mode pMOS capacitors to provide center frequency tuning. The filter has been implemented in HP 0.5-/spl mu/m CMOS process and occupies an area of 0.15 mm/sup 2/. It consumes 16 mA from a single 2.7-V supply at a center frequency of 1.84 GHz and a bandwidth of 80 MHz while providing a passband gain of 9 dB and more than 30 dB of image attenuation for an IF frequency of 100 MHz. The measured output 1-dB compression point and output noise power spectral densities are -16 dBm and -137 dBm/Hz, respectively. This results in a 1-dB compression dynamic range of 42 dB. The filter minimum power supply voltage for proper operation is 2 V. The chip experimental results are in good agreement with theoretical results.     

A Low-Voltage Quadrature CMOS VCO Based on Voltage-Voltage Feedback Topology

A novel low-voltage quadrature voltage-controlled oscillator (QVCO) with voltage feedback to the input gate of a switching amplifier is proposed and implemented using the standard TSMC 0.18-mum CMOS 1P6M process. The proposed circuit topology is made up of two low-voltage LC-tank VCOs, where the coupled QVCO is obtained using the transformer coupling technique. At the 0.7-V supply voltage, the output phase noise of the VCO is -124.9 dBc/Hz at 1-MHz offset frequency from the carrier frequency of 2.4GHz, and the figure of merit is -185.35dBc/Hz. Total power consumption is 5.18 mW. Tuning range is about 135 MHz while the control voltage was tuned from 0 to 0.7V     

Differential Difference Current Conveyor Using Bulk-Driven Technique for Ultra-Low-Voltage Applications

Nowadays the necessity of having low-voltage operation and low-power consumption is essential for electronic devices, particularly for portable electronics. Therefore, this paper presents a new ultra-low-voltage CMOS topology for a differential difference current conveyor (DDCC) based on the bulk-driven (BD) principle. Due to the use of the BD technique, the proposed circuit is capable of working with a low supply voltage of ±0.3 V and consumes about 18.6 μW with a wide input common-mode range. The proposed BD-DDCC is suitable for ultra-low-voltage low-power applications. As application examples, a voltage-mode multifunction biquadratic filter based on two BD-DDCCs and four grounded passive elements, and a fourth-order band-pass filter are presented. All passive elements of both applications are grounded, which is advantageous for monolithic integration. Also, the input voltage signals are applied directly to the high input impedance terminals, which is a desirable feature for voltage-mode operation. The simulations were performed with PSPICE using the TSMC 0.18 μm n-well CMOS technology to prove the functionality and attractive results of the proposed circuit.     

A Wide Tuning Range Gm –C Continuous-Time Analog Filter

A CMOS operational transconductance amplifier (OTA) for low-power and wide tuning range filter application is proposed in this paper. The OTA can work from the weak inversion region to the strong inversion region to maximize the transconductance tuning range. The transconductance can be tuned by changing its bias current. A fifth-order Elliptic low-pass filter implemented with the OTAs was integrated by TSMC 0.18-mum CMOS process. The filter can operate with the cutoff frequency of 250 Hz to 1 MHz. The wide tuning range filter would be suitable for multi-mode applications, especially under the consideration of saving chip areas. The third-order inter-modulation (IM3) of -40 dB was measured over the tuning range with two tone input signals. The power consumption is 0.8 mW at 1-MHz cutoff frequency and 1.8-V supply voltage with the active area less than 0.3 mm²     

A Millimeter-Wave CMOS LC-Tank VCO With an Admittance-Transforming Technique

A novel circuit topology suitable for millimeter-wave voltage-controlled oscillators (VCOs) is presented. With the admittance-transforming technique, the proposed VCO can operate at a frequency close to the f_max of the transistors while maintaining remarkable circuit performance in terms of phase noise, tuning range, and output power. Using a standard micrometer CMOS process, a U-band VCO is implemented for demonstration. The fabricated circuit exhibits a frequency tuning range of 1.1 GHz in the vicinity of 50 GHz. The measured output power and phase noise at 1-MHz offset are -11 dBm and -101 dBc/Hz, respectively. Operated at a supply voltage of 1.8 V, the VCO core consumes a DC power of 45 mW.     

A 0.8-V accurately tuned linear continuous-time filter

An accurately tuned low-voltage linear continuous-time filter is presented in this paper. Accurate tuning is achieved using time-constant matched master-slave tuning combined with power-up mismatch calibration. A low-pass biquad designed for a corner frequency of 115 kHz achieves better than -80-dB total harmonic distortion with a 250-mV/sub pp/ 10-kHz input signal. The prototype implemented in 0.18-/spl mu/m CMOS process occupies an area of 0.4 mm/sup 2/ and dissipates 4.6 mW (2.6 mW for the filter and 2 mW for tuning) of power.     

A highly linear CMOS Gm-C bandpass filter with on-chipfrequency tuning

A fourteenth-order CMOS transconductance-C (G_m-C) bandpass filter with on-chip automatic frequency tuning is described. By using highly linear G_m-C integrators, the filter achieves 75 dB dynamic range over 700 kHz noise bandwidth. The measured intermodulation distortion (IM3) @ 600 kHz for a 4 V_pp input signal is only -61 dB. On-chip automatic frequency tuning provides more than 300% center frequency range (i.e., 165-505 kHz) of the filter with ±1% frequency accuracy. The 0.7-μm CMOS filter measures 4.8 mm ² and consumes 70 mW from a single 5 V power supply     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

OTA linearity enhancement technique for high frequency applications with IM3 below -65 dB

A technique to enhance the linearity of continuous-time operational transconductance amplifiers (OTA)-C filters working at high frequencies is proposed. Each OTA consumes 10.5 mW and the transconductance can be tuned from 70 to 160 /spl mu/A/V while the IM3 remains below -70 dB up to 50 MHz for a 1.3-V/sub pp/ differential input. For a 20-MHz low-pass second-order filter implementation, the measured IM3 with an input voltage of 1.3 V/sub pp/ is below - 65 dB. The supply voltage is 3.3 V. Experimental results of the circuit, fabricated in a standard CMOS 0.35-/spl mu/m technology, are presented.     

A Wideband Power Detection System Optimized for the UWB Spectrum

A wideband radio-frequency (RF) power detection system is presented. The detection technique uses NMOS devices operating in the triode regime to generate an average current proportional to RF input power; this current is converted to voltage and amplified using a piecewise linear logarithmic approximation. Optimization of the NMOS devices is discussed, and a method of gain control is proposed for compensation of temperature and process variation. The power detector occupies an active area of 0.36 mm² in a 0.18 mum CMOS process and consumes 10.8 mW from the power supply. Error between the output and a linear-in-dB best-fit curve is plusmn2.4 dB for a 20 dB input range, when measured at discrete frequencies. The output response is frequency independent, varying by less than 1.8 dB for a fixed input power as frequency is swept across the UWB spectrum.     

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two Active- ${rm G}_{rm m}{-}{rm RC}$ biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The $-$ 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The $-$3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 $mu{rm m}$ CMOS technology with ${V}_{THN}approx 0.25 {rm V}$ and ${V}_{THP}approx 0.3 {rm V}$, the filter operates with a supply voltage as low as 0.55 V. The filter $({rm total} {rm area}=0.47 {rm mm}^{2})$ consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.      

A wide-band CMOS injection-locked ring oscillator

An injection-locked ring oscillator fabricated in a 0.18-/spl mu/m CMOS process is presented for high-speed applications. By tuning the free-running frequency, the proposed circuit provides 2:1 and 4:1 frequency division over a wide input frequency range. The measured input frequency range covers 16.7-25.2 GHz and 41.2-46.9 GHz for 2:1 and 4:1 frequency division, respectively. The divider core operates at a 1.8-V supply voltage with a power consumption between 21.0 and 23.8mW for the entire frequency tuning range.