Electrothermal Monte Carlo Simulations of InGaAs/AlGaAs HEMTs

Results from the application of our electrothermal simulator to n-type 0.15 μm gate In_0.15Ga_0.85As-Al_0.28Ga_0.72As HEMT structures are presented. The simulator involves an iterative procedure which alternately solves the Heat Diffusion Equation (HDE) and executes a Monte Carlo electronic transport algorithm. The net thermal flux generated during each Monte Carlo stage, calculated from the net rate of phonon emission, is fed into the thermal solution; the resulting temperature map is then used in the following Monte Carlo iteration. The HDE is solved through application of a novel analytical thermal resistance matrix technique which allows calculation of temperatures solely within the region of interest while including the large-scale boundary conditions. A novel charge injection scheme is applied for the treatment of side ohmic contacts, which avoids anomalous generation of thermal flux in adjacent regions. The characteristic ‘thermal droop’ is found in the I-V characteristics of the simulated device. Associated temperature distributions are shown to be spatially non-uniform with peak values and spatial locations dependent upon bias and the length of the containing die. Electron drift velocities and energies along the HEMT channel exhibit the largest shift on the inclusion of thermal self-consistency below the drain end of the gate, not at the location of the temperature peak.     

3D Parallel Simulations of Fluctuation Effects in pHEMTs

The use of 3D simulations is essential in order to study the effects of fluctuations when devices are scaled to deep submicron dimensions. A 3D drift-diffusion device simulator has been developed to effectively simulate pseudomorphic high electron mobility transistors (pHEMTs) on a distributed memory multiprocessor computer. The drift-diffusion equations are discretized using a finite element method on an unstructured tetrahedral mesh. The obtained set of equations is solved in parallel on an arbitrary number of processors using the message-passing interface library. We have applied our simulator to a 120 nm pHEMT based on the Al_0.3Ga_0.7As/In_0.2Ga_0.8As interface and carried out a calibration to real experimental data.     

Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO₂–HfO₂ (7.5?nm)–Ag/Au nc/C60 embedded HfO₂ (6?nm)–HfO₂ (30?nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.     

NEGF simulations of the effect of strain on scaled double gate nanoMOSFETs

The effect of biaxial strain on double gate (DG) nanoscaled Si MOSFET with channel lengths in the nanometre range is investigated using Non-Equilibrium Green’s Functions (NEGF) simulations. We have employed fully 2D NEGF simulations in order to answer the question at which body thickness the effects of strain is masked by the confinement impact. Following ITRS, we start with a 14 nm gate length DG MOSFET having a body thickness of 9 nm scaling the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm. The simulated I _D–V _G characteristics show a 6% improvement in the on-current for the 14 nm gate length transistor mainly due to the energy separation of the Δ valleys. The strain effect separates the 2 fold from the 4 fold valleys thus keeping mostly operational transverse electron effective mass in the transport direction. However, in the device with an extreme body thickness of 1.3 nm, the strain effect has no more impact on the DG performance because the strong confinement itself produces a large energy separation of valleys.     

Analytical modeling and analysis of Al m Ga1−m N/GaN HEMTs employing both field-plate and high-k dielectric stack for high-voltage operation

In this paper, a new high-voltage Al _m Ga_1?m N/GaN HEMT (High Electron Mobility Transistors) with Field-Plate and high-k dielectric stack, Graded two-dimensional electron gas (2DEG) Channel Field-Plate Stack dielectric (GCFPS) HEMTs structure has been reported. The proposed structure has shown enhancements of the performances of the GaN-based HEMTs taking into account the effects of spontaneous and piezoelectric polarization fields. In order to analyze this structure, a 2D analytical model has been developed where the expressions for 2D channel potential and electric field distribution have been derived. It was shown that the GCFPS design exhibits significantly reduction of the electric field peaks along the 2DEG channel. Therefore, the breakdown voltage (BV) is greatly improved in comparison with the standard AlGaN/GaN FP-HEMTs. The developed model is validated by the good agreement with the 2D simulated data.     

Simulations of Scaled Sub-100 nm Strained Si/SiGe p-Channel MOSFETs

This paper investigates scaled sub-100 nm strained Si channel p-type MOSFETs. For a 30–40% Ge content SiGe buffer, 1D Poisson-Schrödinger analysis indicates that the parasitic effects of the SiGe buffer are negligible in small devices with high n-type channel doping (>10¹⁷ cm^?3). The device published by IBM and calibrated by us has been scaled down to a 35 nm physical gate length and shows notable performance enhancement over the Si control MOSFET. Well-tempered MOSFET designs have also been adopted to study potential performance improvement associated with the introduction of a strained Si channel. These provide a performance improvement comparable with the scaled versions of the IBM devices for effective gate length down to 25 nm. Improved well engineering is required to suppress short channel effects during the scaling process.     

Random Telegraph Noise in 30 nm FETs with Conventional and High-κ Dielectrics

The magnitude of fractional current variation in ultra-small (30 nm channel length) MOSFETs due to single charge trapping-detrapping events at any position within the gate dielectric is studied using numerical simulation. These random telegraph signals in the drain current indicate the amplitude of low frequency MOSFET noise. Simulations are performed for realistic devices with poly-silicon gates subject to poly-silicon depletion, and for both SiO₂ and HfO₂ as dielectric materials.     

Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor

High‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of In_xGa_1‐xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 10²³ m⁻³, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 10²³ m⁻³, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ). Copyright © 2014 John Wiley & Sons, Ltd.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

Simulation Study of High Performance III-V MOSFETs for Digital Applications

We have studied the performance potential of an 80 nm physical gate length MOSFET with GaAs channel and high-k gate insulator using ensemble Monte Carlo simulations. The results show that a such device could deliver a 100–125% increase in the drive current compared to conventional MOSFETs with analogous channel lengths and device structure. This improvement is much higher than the 20–30% drive current increase in similar devices with strained Si channels on virtual SiGe substrates.     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

Concentration‐dependent minority carrier lifetime in an In0.53Ga0.47As interdigitated lateral PIN photodiode model based on spin‐on chemical fabrication methodology

The fitted parameters for the analytic function used to specify the doping dependence of minority carrier lifetimes for In_0.53Ga_0.47As (InGaAs) is described in this paper. This model together with other carrier models was used to develop an interdigitated lateral PIN photodiode utilizing InGaAs as the absorbing layer. We propose the usage of spin‐on chemicals such as spin‐on dopants and spin‐on glass to form the p+ wells, n+ wells and the surface passivation layer of the device hence providing a cheap and easy solution versus the conventional epitaxial growth methodology. The modeled device achieved dark currents of 0.21 nA and capacitance of 2.87 nF at an operating voltage of 5 V. Optical illumination at a wavelength of 1550 nm and power of 10 W/cm² enabled the device to achieve responsivity of 0.56 A/W and external quantum efficiency of 44%. The −3 dB frequency response of the device was at 8.93 GHz and signal‐to‐noise ratio is 36 dB. The developed device shows close correlation with experimentally developed devices developed using other fabrication methodologies. The results of this work would be useful in the thorough development of InGaAs‐based devices based on spin‐on chemical fabrication methodology using commercial device simulation packages. Copyright © 2010 John Wiley & Sons, Ltd.     

Performance enhancement of recessed silicon channel double gate junctionless field-effect-transistor using TCAD tool

In this paper, we propose an n-type double gate junctionless field-effect-transistor using recessed silicon channel. The recessed silicon channel reduces the channel thickness between the underlap regions, results in lowering the number of charge carriers in the silicon channel, and therefore, diminishing the OFF-current in the device. The proposed device shows similar electrical characteristics with improved transconductance, as compared to the conventional double gate junctionless field-effect-transistor. The effect of channel length scaling on the performance have been investigated, and it has been found that the recessed junctionless device shows higher ON-to-OFF current ratio, lower subthreshold swing and better immunity against the short channel effects, namely threshold voltage roll-off and drain-induced-barrier-lowering. For a channel length of 20 nm the OFF-current of the order of 1.20?×?10^–14 A/µm, ON-to-OFF current ratio of the order of 6.01?×?10¹⁰, subthreshold swing of the value of 67 mV/dec, and DIBL of 37.8 mV V^?1 has been achieved with the proposed junctionless device, in comparison of conventional double gate junctionless FET. The performance of proposed device with respect to the variations in depth and length of recessed silicon area, has also been presented as a roadmap for further tuning of its electrical behaviour. Comparatively, steeper DC transfer characteristics and improved rail-to-rail swing in transient behaviour has been reported with the designed complementary metal–oxide–semiconductor inverter, based on recessed double gate junctionless FET. The proposed recessed silicon channel double gate junctionless field-effect-transistor has been simulated using TCAD tool.

     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

Enhanced of electrical characteristics of nano-crystal floating gate memory with In2O3 nano-particles embedded in polyimide

We fabricated the nano-floating gate memory (NFGM) with In₂O₃ nano-particles embedded in polyimide gate insulators. Self-assembled In₂O₃ nano-particles were created by chemical reaction between the polymer precursor and the indium film. The particle size and density of In₂O₃ nano-particles were about 7 nm and 6?×?10¹¹ cm^?2, respectively. The electrical characterization of the NFGM with In₂O₃ nano-particles embedded in polyimide layer were measured and the memory window larger than 3.8 V was obtained from the fabricated NFGM devices due to the charging effects of In₂O₃ particles. Subthreshold swing, output current characteristics and retention time of fabricated NFGM devices were considerably improved by the post-annealing process in 3% hydrogen diluted H₂/N₂ ambient.     

Effect of quantum dots on InAs/GaAs p-i-p quantum dots infrared photodetectors

ABSTRACT

In this paper, the InAs/GaAs p-i-p quantum dots infrared photodetectors (QDIPs) were successfully demonstrated by Apsys software. It consists of Al_0.3Ga_0.7As/GaAs structure to reduce dark current and InAs quantum dots (QDs) embedded in In_0.15Ga_0.85As as an active layer. The effect of structure parameters of InAs QDs on the dark current, photocurrent of the device and SNR (signal to noise) is discussed respectively, including different QDs density, the number of QD layer, GaAs thickness between QDs layers and Al_0.3Ga_0.7As, and GaAs thickness between two the QD layers.     

Random Doping Fluctuations of Small-Signal Parameters in Nanoscale Semiconductor Devices

Random dopant induced fluctuations of small-signal parameters in nanoscale semiconductor devices are analyzed by using the perturbation (linearization) technique. This technique requires only first-order derivatives of the transport equations, which makes it suitable for implementation in commercial device simulators. Sample numerical results are presented for a 25 nm channel length n-channel MOSFET device.     

Comparison of Double-Gate MOSFETs and FinFETs with Monte Carlo Simulation

A full-band Monte Carlo simulator has been used to analyze and compare the performance of n-channel double-gate MOSFETs and FinFETs. Size quantization effects were accounted for by using a quantum correction based on Schrödinger equation. FinFETs are a variation of typical double-gate devices with the gate surrounding the channel on three sides. From our simulations, we observed that the quantization effects in double-gate devices are less significant as compared to bulk MOSFETs. The total sheet charge density drops only slightly as the depletion of charge at the interface is counterbalanced by the increased volume inversion effect. We also observed an appreciable drop in average velocity distribution when quantum corrections were applied. For FinFETs, the fin extension lengths on either side of the gate affect the device performance significantly. These underlap regions have low carrier concentration and behave as large resistors. The current drops non-linearly with increasing fin extension lengths.     

A novel efficiency‐enhancement topology: GaN high‐electron mobility transistors with waveform‐modulation structure composed of Schottky diodes

To improve the power‐added efficiency (PAE) of the gallium nitride (GaN) high‐electron mobility transistor (HEMT) in radio frequency applications, this paper studies the relationship between the nonlinearity of the gate capacitance and the PAE of the GaN HEMTs. The theoretical analysis and simulation results demonstrate that the nonlinearity of the gate capacitance modulates the signal phase at the GaN HEMT input and increases the average drain current, leading to increased power consumption and reduced PAE. Then, an efficiency‐enhancement topology for GaN HEMTs that employs the waveform‐modulation effect of Schottky diodes to reduce power consumption and improve efficiency is presented. The efficiency‐enhancement topology for a 4 × 100‐μm GaN HEMT with waveform‐modulation diodes is then fabricated. Results of load‐pull test demonstrate that the novel topology can increase the PAE of the 4 × 100‐μm GaN HEMT by more than 5% at 8 GHz. The novel efficiency‐enhancement topology for GaN HEMTs proposed in this paper will be suitable for applications that demand high‐efficiency GaN HEMTs or circuits.