Evaluation of hybrid bonding technology of single-micron pitch with planar structure for 3D interconnection

In this paper, we describe hybrid bonding technology of single-micron pitch with planar structure for three-dimensional (3D) interconnection. Conventionally, underfill method utilizing capillary force was used after the bonding of microbump. However, the filling becomes insufficient in a gap less than 10 μm between chips or bumps. One promising technology is the hybrid bonding technology that microbumps and an adhesive can be simultaneously bonded. To realize a single-micron pitch hybrid bonding, we fabricated a planar structure that consists of 8 μm-pitch Cu/Sn microbumps and a non-conductive film (NCF) by a chemical mechanical polishing (CMP) of resin. After planarization, the Cu/Sn bumps and the NCF were simultaneously bonded at 250 °C for 60 s. Cross-sectional scanning electron microscope (SEM) images and energy dispersive X-ray spectroscopy (EDX) images show that the adhesive resin on the bump surface was successfully removed by the CMP. In addition, SEM images of the bonded sample show that the adhesive filled the 2.5-μm gap between the chip and substrate. The Cu/Sn bumps were properly bonded in a corner on the chip. The proposed bonding method is expected to enable single-micron pitch interconnection for ultra-high density 3D LSI of next generation.     

Asynchronous transfer mode switching LSI chips with 10-Gb/s serialI/O ports

LSI chips were developed that fit on a switching fabric using chip-to-chip optical interconnections; they have 10-Gb/s serial input and output ports, which facilitates the layout of optically interfaced switching element modules. A test switching module composed of these chips was operated at 10.2 Gb/s without bit errors. Ultrahigh-speed switching LSI chips have been developed for a future asynchronous transfer mode (ATM) switching system with an over-Tb/s capacity. Their serial input and output ports facilitate chip-to-chip optical interconnection. Cell-dropper and crosspoint-router LSI chips, composing the core of the switching element, were fabricated by using GaAs LSI technology. A test switching module composed of these chips was operated at 10.2 Gb/s without bit errors     

面向三维集成应用的Cu/SiO2晶圆级混合键合技术研究进展

Cu/SiO₂混合键合技术被认为是实现芯片三维集成和高密度电学互连的理想方案,但由于其需兼顾介质和金属两种材料的键合,目前鲜有自主开发且工艺简单、成本低廉的混合键合方案的报道。文章归纳了现有的晶圆级键合技术,包括直接键合、活化键合以及金属固液互扩散键合,分析了其应用于混合键合技术的可能性。进一步总结了近年来部分Cu/SiO₂混合键合技术的研究进展,从原理上剖析该工艺得以实现的关键,为国内半导体行业占领此高端领域提供一定的参考。     

新一代电子组装技术——表面组装技术与多芯片组件技术

２０世纪９０年代初，表面组装技术（ＳＭＴ）已成为世界电子整机组装的主流，现正向窄间距技术、高速、高精度、多功能、免洗焊接和采用无铅焊料发展。微组装技术（ＭＰＴ）则是在半导体ＩＣ技术、混合ＩＣ技术和ＳＭＴ的基础上发展起来的第五代电子组装技术。多芯片组件（ＭＣＭ）是ＭＰＴ的代表产品，ＭＣＭ的关键技术是高密度多层基板技术、叠层芯片技术、芯片互连技术和窄间距技术     

Integrated CoolMOS FET/SiC-diode module for high performance power switching

A Si CoolMOS field effect transistor and SiC diode assembly with gate driver in boost configuration (ratings at 600V/12A), for power factor correction application, has been fabricated in a version of an integrated power electronic module. It uses the so-called embedded power technology, to form a three-dimensional multiple chip/component interconnection with the embedded chips in a co-planar ceramic substrate with thin-film metallization bond/interconnection added on top. In this paper, the switching parameters of this module and their effects on the performance of a converter have been analyzed and experimentally characterized. The procedures adopted for the defined fabrication process of planar metallization interconnects are presented. In addition to the improvement of structural electrical properties, compared to a conventional discrete version, the characteristics of the planar process integration have also been demonstrated.     

Voltage‐Mode 1.5 Gbps Interface Circuits for Chip‐to‐Chip Communication

In this paper, interface circuits that are suitable for point‐to‐point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi‐gigabits per‐second between two chips with a point‐to‐point interconnection, the input receiver uses an on‐chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode‐connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 µm dual gate oxide CMOS technology.     

Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages

This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer enhancement. Besides, in the silicon carrier, there are through silicon vias (TSVs) with metal film on sidewall for electrical interconnection. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. The advantage of this 3-D stacking method is that it provides a method of simultaneously realizing electrical interconnection and fluidic path and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.     

Embedded power: a 3-D MCM integration technology for IPEM packaging application

Embedded power (EP) is the name for an integration technology for the power electronics switching stage, in which the multiple bare power chips, such as IGBTs, MOSFETs, and diodes, are buried in a ceramic frame and covered by a dielectric layer with via holes on the Al pads of the chips. Then, a planar metallization pattern is deposited onto it both for bonding to the power chips and a circuit wiring. The ceramic frame can be used as an extra thermal path and substrate for fabrication of the hybrid circuit with compatible thin- or thick-film techniques. When this integrated chips component is stacked with a base substrate and the associated components, a novel three-dimensional (3-D) multichip module (MCM) is produced. Such an integrated power electronics module (IPEM) offers performance improvement, functional integration, and process integration, as compared to conventional power hybrid modules. This paper presents the details of this technology, including the process design and implementation. A subsystem IPEM, incorporating power factor correction (PFC) and dc/dc switching stages for a distributed power system (DPS) front-end converter application, has been fabricated and characterized to demonstrate the feasibility of this power electronics integration technology. The capability for functional integration and the electrical performance improvement, which includes reduction in parasitics and increase in efficiency, are presented.     

No clock, no bus - no sweat [asynchronous IC interconnect network]

This article presents a UK start-up which believes it has come up with a fundamental shift in interconnection technology that will solve timing closure problems in complex chips. It is based on an asynchronous design and uses packet switching technology. It is expected to be particularly effective in SoC design.     

Design and fabrication of waveguide-based chip-to-chip optical interconnection network on printed circuit boards

A waveguide-based chip-to-chip optical interconnection network on printed circuit board (PCB) was designed and fabricated, and experiments confirmed that the data rate in each channel could reach above 3.125 Gbit/s and the bit error rate (BER) could be up to 1.27×10-18, which would be a good solution to solve the communication bottlenecks between high-speed very large scale integration chips. Besides, the whole design and fabrication of optical interconnection network on printed circuit board has the advantages of high reliable, low cost and ease of manufacture.     

Substrate interconnect technologies for 3-D MEMS packaging

We report the development of 3-dimensional silicon substrate interconnect technologies, specifically for reducing the package size of a MOSFET relay. The ability to interconnect multiple chips at different elevations on a single substrate can significantly improve device performance and size. We present the process development of through-hole interconnects fabricated using deep reactive ion etching (DRIE), with an emphasis on achieving positively tapered, smooth sidewalls to ease deposition of a seed layer for subsequent Cu electroplating. Gray-scale technology is integrated on the same substrate to provide smooth inclined surfaces between multiple vertical levels (>100 μm apart), enabling interconnection between the two levels via simple metal evaporation and lithography. The developments discussed for each technique may be used together or independently to address future packaging and integration needs.     

Series resistance of devices with submicrometer source/drain areas

The source-drain series resistances of devices contacted by a local interconnection technology utilizing polysilicon strapped with selective CVD tungsten were measured and compared to predictions obtained using a theoretical model. Asymmetrical devices in which the local interconnections were intentionally misaligned to the gate were fabricated to study the effects of misalignment on device characteristics. Experiments indicate that the technology is quite forgiving to the misalignment between the gate and the local interconnection     

Electroless remetallization of aluminum bond pads on CMOS driverchip for flip-chip attachment to vertical cavity surface emitting lasers(VCSEL's)

A method for remetallizing the bond pads of electronic chips, which are initially metallized with aluminum or aluminum alloy is presented. Application of electroless plating process for the remetallization of aluminum to a solderable gold surface can reduce the cost and complication of the widely accepted flip-chip interconnection technology. We have developed a step by step nickel/gold wafer bumping technique (remetallized bump height is 5.0 μm) for the appropriate solder (15.0 μm of In:Pb). Variation of roughness of the remetallized surface has been studied carefully. We have completed prototype research studies on test devices and successfully packaged the flip-chip bonded hybrid pair of a CMOS driver chip and a dummy structure of vertical cavity surface emitting laser (VCSEL) array. Cross section of the flip-chip solder joint is studied. Also, adhesion strength of the metal deposit is investigated     

Multichip packaging and the need for new materials

The sole determiner of speed, of cost, and of possible system size is the interconnection density of the circuits. The best way to increase the interconnection density is to reduce the dielectric constant, and there are new materials that offer almost a 2:1 reduction. Designing new modules with these low dielectric constant materials and with larger chips increases the wattage and increases the wattage density. Ceramic substrates must be used to dissipate the heat of the new large higher wattage chips without destroying them. This requires the use of new ceramic materials. A choice must be made between the leading contenders. A new multichip module technology is being defined, and will result in a major packaging change. The processes and the materials choices are presently overwhelming, but there are great advantages to those who identify the best solutions.     

Using GA-SVM for defect inspection of flip chips based on vibration signals

Flip chip technology has been widely used in IC packaging, and the combination of flip chip technology and solder joint interconnection technology has been utilized in the manufacturing of electronic devices universally. As the development of flip chip towards high density and ultra-fine pitch, the inspection of flip chips is confronted with great challenges. In this paper, we developed an intelligent system used for the detection of flip chips based on vibration. Thirty-four features including 18 time domain features and 16 frequency domain features were extracted from the raw vibration data. The support vector machine was employed to implement the recognition and classification of flip chips. In order to improve the classification accuracy of SVM, cross validation (CV) and genetic algorithm (GA) were utilized to optimize the parameters of SVM respectively. SVM, CV-SVM and GA-SVM were applied to classification separately and the results were obtained. By comparison, GA-SVM can recognize and classify the flip chips rapidly with high accuracy. Thus, GA-SVM is effective for the defect inspection of flip chips.     

三维集成大功率同步整流器的研究与设计

实现同步整流能够有效提高次级整流效率,并且有利于实现电源模块的小型化.将同步整流器中的控制电路和整流桥分别制作在两层芯片上,然后堆叠两层芯片并通过TSV实现层间信号互连,不仅能进一步提高集成度,还能有效降低引线延迟和功耗.设计了一种大功率同步整流器,仿真实现了输出电压为5V、最大输出电流为13.38A、输出电压和输出电...     

Complex Monolithic Arrays: Some Aspects of Design and Fabrication

Large scale integration is the simultaneous realization of large area circuit chips and optimum component packing density for the express purpose of reducing costs by maximizing the number of system connections done at the chip level. The highly complex monolithic circuits being offered today are obviously the forerunners of true LSI. Many questions pertinent to LSI are asked repeatedly today. Some of the more timely aspects of large scale integration are considered here. The prime objective of this paper is, therefore, to establish where LSI is today. The coverage is limited to bipolar silicon integrated circuits. A DTL design is compared to an ECL design to illustrate a basis for choice of circuit type, power level, and interrelationship with respect to resistor and transistor parameters. Arrays of DTL and ECL gates with single-layer interconnection metal are next considered; each gate is assumed to have one semiconductor crossunder tunnel. The resulting expressions relate the maximum allowable number of DTL and ECL gates in the monolayer array to circuit threshold. Next, the characteristics of metal interconnections are examined to obtain a method for predicting average interconnection length, die area occupied by the interconnections, and signal delay introduced by the interconnections. Finally, some thermal aspects of packaging a square hybrid LSI array of 2n X 2n chips are analyzed for an ECL and a DTL design. An expression is derived which relates power density of the hybrid array to the number of gates in the array and pertinent properties of the base system.     

可重构阵列处理器光电混合互连原型系统实现

高效视频编码(HEVC)标准在提升编码性能的同时,对系统带宽提出了更高的要求。传统电互连方式存在带宽小和时延大的问题,而光互连的高带宽和低功耗为片上资源数据通信提出了新的解决方案。然而由于工艺水平的限制,集成光器件无法在现场可编程门阵列(FPGA)芯片内部实现。采用片外光器件模拟片上光互连系统可以达到原型验证的目的。文章基于BEE4开发平台在单片上采用电互连方式进行数据通信,在Xilinx V6系列芯片间通过接入4通道小型可插拔+(QSFP+)光模块搭建光通信链路,构建光通信网络,实现了光电混合互连网络原型系统。以分辨率176×144的标准测试序列akiyoqcif176×144.yuv为例进行测试,实验结果表明,以光链路替代片间电通信能够正确实现,且板间传输时间仅为电互连的一半,综合频率为51.327 MHz。     

80 Gbit/s ATM switch MCM based on multilayer ceramic technology

An 80 Gbit/s asynchronous transfer mode (ATM) switch multichip module (MCM) of dimensions 114×160×6.5 mm has been fabricated. This MCM can support high-density mounting and high-speed interconnection among large-scale-integrated (LSI) chips. Using LSI, ceramic-substrate, high-speed/high-power connector, and compact liquid-cooling technologies, an 80 Gbit/s ATM switching module has been built     

A selective CVD tungsten-strapped polysilicon local interconnectiontechnology

A local interconnection technology utilizing polysilicon strapped with selective-chemical-vapor-deposited (CVD) tungsten has been developed. Both n- and p-channel MOS transistors have been successfully fabricated using this technology. Tungsten deposited on polysilicon is an attractive gate shunt and local interconnection material because of its low resistivity, immunity to dopant segregation and diffusion, and resistance to electromigration. A potential problem of this technology is the excessive diode leakage current associated with strapping shallow source/drain diodes with tungsten. The leakage is attributed to defects induced by the heavy source/drain implant, which can be effectively eliminated with a proper annealing procedure