DMB-T系统中FFT模块的设计与实现

介绍了地面数字多媒体/电视广播传播系统(DMB-T)中3 780点FFT模块的重要作用.考虑到不适合直接利用现已成熟的基-2和基-4的算法,提出一种全并行流水结构的3 780点FFT的设计和实现方案.该方案采用WFTA算法和PFA算法,把3780分解为7×9×5×4×3共5级的流水线结构.通过对整个系统的仿真与硬件实现,证明该方案性能上能够满足TDS-OFDM系统的信噪比要求.     

3780点FFT处理器的研究

3780点FFT模块是地面数字多媒体／电视广播传播系统（DMB—T）中的重要模块之一，由于该模块不能直接利用现已成熟的基-2和基-4的算法，故给出了三种实现3780点FFT的算法和处理器结构，分别是内插成4096点的FFT算法、混合基FFT算法和综合分解算法，并对各种方法的优缺点进行了讨论。     

一种适用于宽带无线移动通信系统下行链路的TDS-OFDM发送方法

本文将主要介绍宽带无线城域网系统(BRadio)中下行链路的TDS-OFDM(时域同步正交频分复用)发送方法.TDS-OFDM是针对宽带无线传输信道设计的一种多载波调制方式,既适用于具有多径干扰和多普勒频移的地面数字电视广播传输信道,也适用于其他宽带数字传输系统.TDS-OFDM技术已经在地面数字多媒体/电视广播(DMB-T)传输系统中得到了应用,在此基础上,本文结合对已有的宽带无线移动通信系统的研究,对宽带无线移动通信系统的帧结构、OFDM符号组成、子载波分配方案进行了改进,使TDS-OFDM能够适用于宽带无线移动通信系统,满足其需求.     

TD-LTE系统中定时同步算法的研究

定时同步算法性能的好坏将直接影响到频偏估计的误差和FFT解调窗口起始位置的确定。综合考虑无线信道场景中多径时延以及多普勒效应对发送信号的影响,分析对比了TD-LTE系统中常规定时同步算法的基本原理和性能。在此基础上提出了基于时域前后半帧PSS主同步信号的差分相关算法来确定定时同步位置,利用前后半帧PSS相关消除整数倍频偏对常规相关算法的影响;采用差分相关算法降低前后半帧的较大时延对信号的影响。仿真结果表明本文提出的算法性能良好,在实际的场景中其具有稳定、低复杂度的特性。     

一种通用MPSK载波同步方法及其FPGA实现

为解决MPSK体制信号解调中可能存在的较大载波频偏,介绍一种结合基于最大似然准则的FFT频偏估计与通用载波锁相环的多调制体制通用载波同步方案。依次分析了该方案的算法原理、结构特点与运算和硬件复杂度,并说明该算法在FPGA上实现该方案的整体结构安排与关键技术要点。在Xilinx的XC4VLX200芯片上实现了该电路。结果表明该电路可完成对较大的频偏、较低的信噪比条件下MPSK信号载波同步工作,具有较好的工程应用价值。     

降低TDS-OFDM信号峰均功率比的方法

针对具有大量子载波的时域同步正交频分复用(TDS-OFDM)系统,提出了应用星座图扩展降低TDS-OFDM系统的峰均功率比(PAPR),同时增加保护间隔的能量以增大信号的平均功率,使得TDS-OFDM的PAPR进一步降低.最后给出了相应的仿真结果.     

空时发射分集技术在DTTB中的应用

为提高在衰落信道下数字电视地面广播(DTTB)系统的传输性能,介绍了一种空时发射分集的实现方法.利用时域同步正交频分复用(TDS-OFDM)系统信号帧结构的特点,不同发射链路的信号配置简单易行.仿真结果证明,这种发射分集方法能够有效提高系统的接收性能,增加了信号传输的可靠性.     

基于激光导引头信号的并行高速FFT算法设计

为了减少激光半主动武器中测量光学器件光斑点坐标时噪声和干扰对探测精度影响、增加脉冲信号的测量带宽、提取信号的有效值,同时克服串行快速傅里叶变换（FFT）运算耗时及时间复杂度较大的问题,基于多核和并行架构的SoC-FPGA平台以及OpenCL软件,提出了实现并行FFT的计算方法。结果表明,利用该方法可使FFT（1-D）的时间复杂度下降到原来的1/Q,得到了较好的加速效果;通过3种平台（先进精简指令集微处理器、数字信号处理器和片上系统现场可编程门阵列）的运算耗时实验对比,该算法运算耗时为6.0449ms（1-D 4096点）,要比同点数其它两种平台运算耗时少。并行FFT算法不仅满足激光半主动导引头信号实时性的要求,而且可以达到去噪的效果,能有效地降低噪声和背景光的影响。     

5G下行信号解调算法研究

针对5G下行信号的解调测试需求，设计了5G下行信号解调方法。采用5G下行信号解调模块化设计思想，首先采用信号同步找到信号帧的起始位置、终止位置以及整数载波频率偏移，利用去循环前缀（Cyclic Prefix,CP）模块确定最佳的傅里叶变换（Fast Fourier Transform,FFT）起始点，并对每个正交频分复用（Orthogonal Frequency Division Multiplexing,OFDM）符号进行FFT运算；其次信道估计模块根据5G下行信号解调参考信号（DeModulation Reference Signal,DMRS）位置计算出信道传输函数，再使用线性插值算法估计出5G下行信道所有符号上子载波位置的幅度和相位响应特性；再次进入信道均衡模块，补偿信道传输函数的幅度和相位；最后进入误差矢量幅度（Error Vector Magnitude,EVM）计算测量模块，评估通信发射机发射信号的质量，通过比较接收的测量符号和理想的参考信号，完成信号解调。通过理论推导和实际应用相结合，验证了本文设计的完整信号解调算法可以实现5G下行信号解调。     

LTE系统中一种低复杂度的PSS定时同步算法

研究了长期演进技术(LTE)系统下行链路中的 PSS定时同步。针对传统 PSS定时同步算法将接收信号与本地 PSS 信号在时域进行匹配滤波,计算复杂度较高的问题,提出了一种分段频域相关算法。该算法将接收时域数据分段做 FFT,转换到频域进行相关检测。多径信道下仿真结果表明,选择分段间隔为512时,所提算法与传统算法相比,在保证同步性能相当的情况下,可大大降低计算复杂度(约94%)。     

非2-基FFT的素因子算法研究

提出一种新的非2-基N点FFT的素因子算法.该方案与原素因子分解算法比较,实现了各个小点数DFT的同址顺序运算,并通过简单的地址模加运算得到顺序的输出,省去了多余的整序运算,是一种通用N点FFT算法.设计结构规整简单,利于硬件实现.以中国数字电视广播地面传输标准(DTMB)规定的3 780点FFT为例,结合WFTA算法和混合基算法,介绍了算法的具体设计与实现方案.     

超高速全并行快速傅里叶变换器

设计和实现超高速快速傅里叶变换器(FFT)在雷达与未来无线通信等系统中具有重要意义。该文提出首个全并行架构的FFT处理器,其避免了复杂的路由寻址以及数据访问冲突等问题,基于较大基进行分解降低运算复杂度。由于旋转因子已知和固定,大量的乘法转化为了定系数乘法。同时由于采用了串行的计算单元,在达到全并行结构的高速度同时硬件复杂度相对较低;所有的硬件计算单元处于满载的条件,其硬件效率能达到100%。根据实际的实现结果,所提出的512点FFT处理器结构能够达到5.97倍速度面积比的提升,同时硬件开销仅占用了Xilinx V7-980t FPGA 30%的查找表资源与9%的寄存器资源。     

A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring

A single-chip reconfigurable FFT/IFFT processor that employs a ring-structured multiprocessor architecture is presented. Multi-level reconfigurability is realized by dynamically allocating computation resources needed by specific applications. The processor IC was fabricated in 0.25-/spl mu/m CMOS. It performs 8-point to 4096-point complex FFT/IFFT with power-consumption scalability and provides useful trade-offs between algorithm flexibility, implementation complexity and energy efficiency.     

Novel Reversible Integer Fourier Transform With Control Bits

This paper presents a novel concept of the reversible integer discrete Fourier transform (RiDFT) of order 2^r, r > 2, when the transform is split by the paired representation into a minimum set of short transforms, i.e., transforms of orders 2^k, k < r. By means of the paired transform the signal is represented as a set of short signals which carry the spectral information of the signal at specific and disjoint sets of frequencies. The paired transform-based fast Fourier transform (FFT) involves a few operations of multiplication that can be approximated by integer transforms. Examples of 1-point transforms with one control bit are described. Control bits allow us to invert such approximations. Two control bits are required to perform the 8-point RiDFT, and 12 (or even 8) bits for the 16-point RiDFT of real inputs. The proposed forward and inverse RiDFTs are fast, and the computational complexity of these transforms is comparative with the complexity of the FFT. The 8-point direct and inverse RiDFTs are described in detail.     

An expandable column fft architecture using circuit switching networks

The Fast Fourier Transform (FFT) is widely used in various digital signal processing applications. The performance requirements for FFT in modern real-time applications has increased dramatically due to the high demand on capacity and performance of modern telecommunication systems, where FFT plays a major role. Software implementations of FFT running on a general purpose computer can no longer meet current speed requirements. However, recent advances in VLSI technology have made it possible to implement the entire FFT system on a single silicon substrate. This article presents a column FFT design suitable for ULSI (Ultra Large Scale Integration) implementations. The basic building block is a 64-point column FFT. FFTs with longer transform lengths can be easily realized using the 64-point column FFT building block. The butterfly processors in the column FFT are connected using circuit switching networks. The circuit switching networks not only provide dynamically recon-figurable interconnections among the butterfly processors, but also provide a fault-tolerant capability. Bit-serial arithmetic is used in the architecture. Assuming the data word length is 16 bits, the 1024-point column FFT engine proposed in this article is capable of processing 1024 complex data samples in 533 clock cycles. If the clock frequency is 40 MHz, it will take 13.3 µs to complete a 1024-point FFT.     

改进的16QAM载波频偏估计算法

针对QAM相干光传输系统中载波频偏估计算法存在估计范围小、计算复杂度高的问题,提出一种基于训练符号的FFT频偏估计算法.利用训练符号相位信息消除部分采样信号调制相位,取该部分信号的幅角进行FFT变换,最终得到频偏估计值.消除了原频偏估计算法中除以4的运算,从而扩大了频偏估计范围,同时由于减少了FFT长度进而降低计算复杂度.仿真结果表明,改进后的算法在QAM相干检测系统保持较高精度的频偏估计情况下,其估计范围可以达到±50％符号速率.     

On the testability of array structures for FFT computation

This article presents new approaches for testing VLSI array architectures used in the computation of the complexN-point Fast Fourier Transform. Initially, an unrestricted single cell-level fault model is considered. The first proposed approach is based on a process whose complexity is independent (or C- as constant) of the number of cells in the FFT architecture. This is accomplished by showing a topological equivalence between the FFT array and a linear (one-dimensional) array. The process of fault location is also analyzed. The second proposed method is based on a testing process whose complexity is linear with respect to the number of stages (columns) of the FFT array. A component-level fault model is also proposed and analyzed. The implications of this model on the C-testability process are fully described.This research is supported by grants from NSF and NSERC.     

A Low-Complexity PTS-Based Radix FFT Method for PAPR Reduction in OFDM Systems

A low-complexity partial transmit sequence (PTS) technique for reducing the peak-to-average power ratio (PAPR) of an orthogonal frequency division multiplexing (OFDM) signal is presented. Signals at the middle stages of an -point radix FFT using decimation in frequency (DIF) or decimation in time (DIT) are considered for PTS subblocking. We show that DIF has a lower multiplicative complexity than DIT for similar PAPR reduction. A higher radix based FFT achieves better PAPR reduction per stage with less multiplicative complexity compared with a lower radix FFT. We further reduce the computational complexity by proposing a new technique, called decomposition PTS (D-PTS) subblocking, where subblocks are assigned through different stages of the transform. This new technique reduces the multiplicative complexity, while providing PAPR reduction similar to other techniques such as original PTS (O-PTS). Moreover, it has lower additive complexity.     

高吞吐率双模浮点可重构FFT处理器设计实现

高吞吐浮点可灵活重构的快速傅里叶变换(FFT)处理器可满足尖端雷达实时成像和高精度科学计算等多种应用需求。与定点FFT相比,浮点运算复杂度更高,使得浮点型FFT的运算吞吐率与其实现面积、功耗之间的矛盾问题尤为突出。鉴于此,为降低运算复杂度,首先将大点数FFT分解成若干个小点数基2k 级联子级实现,提出分别针对128/256/512/1024/2048点FFT的优化混合基算法。同时,结合所提出同时支持单通道单精度和双通道半精度两种浮点模式的新型融合加减与点乘运算单元,首次提出一款高吞吐率双模浮点可变点FFT处理器结构,并在28 nm标准CMOS工艺下进行设计并实现。实验结果表明,单通道单精度和双通道半精度浮点两种模式下的运算吞吐率和输出平均信号量化噪声比分别为3.478 GSample/s, 135 dB和6.957 GSample/s, 60 dB。归一化吞吐率面积比相比于现有其他浮点FFT实现可提高约12倍。     

基于FPGA的24点离散傅里叶变换结构设计

基于Good—Thomas映射算法和ISE快速傅里叶变换IP核,设计了一种易于FPGA实现的24点离散傅里叶变换,所设计的24点DFF模块采用流水线结构,主要由3个8点FFT模块和1个3点DFT模块级联而成。并且两级运算之间不需要旋转因子,整个DFF模块仅仅需要14个实数乘法器,布局布线后仿真工作时钟频率可达200MHz。首先根据Good—Thomas算法将并行的24路输入信号分成3组,每组8路信号,并进行并／串转换,得到3路串行信号;其次。将3路串行信号分别输入至3个FFrIP核模块进行8点FFT运算;然后,将上述3个FFrIP核模块同一时刻输出的3路信号进行3点DFF变换;最后,将得到的3路并行输出信号分别进行串／并转换,得到24路DFF输出信号。此外,设计的24点DFT结构还具有很好的扩展性,通过修改FFTIP核变换点数参数便可实现长度N=3×2^N点DFT。