用分量匹配法实现对高速时钟电路的动态优化

本文讨论如何设计工作在GHz频率下的VLSI芯片时钟电路.时钟树采用平衡平面布局消除时钟偏差;利用插入缓冲器对电路性能进行动态优化.最后用一个电路模拟软件对电路进行评估.和以往的工作相比较,本文实现了在频域内对时钟电路的优化,显著地提高了仿真速度.     

Dynamically De-Skewable Clock Distribution Methodology

In a typical clock distribution scheme, a central clock signal is distributed to several sites on the integrated circuit (IC). Local regenerators at these sites buffer the clock signal for the logic in regions close to the regenerator. Minimizing the skew between the clocks at these regeneration sites is critical. In recent times, this is becoming harder due to increasing intra-die processing variations. In this paper, we describe a novel technique to distribute a clock signal from a central location to several sites on a VLSI IC. Our technique uses a buffered H-tree and includes circuitry to dynamically remove any skew that may result due to intra-die processing variations. While existing approaches to deskewing a clock tree have utilized several phase detection circuits (number of phase detectors dependent on the number of clock regenerators), our method requires only one phase detector. Also, in our approach, the resolution of the phase detector is inconsequential unlike existing techniques. Our deskewing technique can be applied dynamically, either at boot time or periodically during the operation of the IC. Using a six-level H-tree clock distribution network with process variations deliberately included, we demonstrate that our technique can reduce skews as high as 300 ps down to just 3 ps. We compare our clock tree with traditional buffered and unbuffered H-tree networks.      

Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers

The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or altering hold/setup constraints, possibly causing the circuit to operate incorrectly. The knowledge of the spatial distribution of temperature can be used to properly design a clock network that is able to compensate such thermal non-uniformities. However, redesign of the clock network is effective only if temperature distribution is stationary, i.e., does not change over time. In this paper, we specifically address the problem of dynamically modifying the clock tree in such a way that it can compensate for temporal variations of temperature. This is achieved by exploiting the buffers that are inserted during the clock network generation, by transforming them into tunable delay elements. Temperature-induced delay variations are then compensated by applying the proper tuning to the tunable buffers, which is computed offline and stored in a tuning table inserted in the design. We propose an algorithm to minimize the number of inserted tunable buffers, as well as their tunable range (which directly relates to complexity). Results show that clock skew is kept within original bounds with worst-case power and area penalty of 3.5% and 5.5%, respectively.      

ASIC设计中时钟偏移分析

目前的ASIC设计中,时钟偏移对同步数字电路的影响越来越大,它也越来越受到高速电路设计者的关注,因此如何解决它给电路带来的不利影响成了设计中的重要挑战、文章分析了时钟偏移的产生机理,然后提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器,以平衡时钟网络,最后还分析了如何利用有用的时钟偏移来改善电路的时序。     

专用集成电路设计中的时钟偏移分析

目前的专用集成电路设计中，时钟偏移对同步数字电路的影响越来越大，它也越来越受到高速电路设计者的关注。因此如何解决它给电路带来的不利影响成了设计中的重要挑战。本文分析了时钟偏移的产生机理，然后提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器，以平衡时钟网络，最后还分析了如何利用有用的时钟偏移来改善电路的时序。     

ASIC设计中时钟偏移分析

目前的ASIC设计中,时钟偏移对同步数字电路的影响越来越大,它也越来越受到高速电路设计者的关注,因此如何解决它给电路带来的不利影响成了设计中的重要挑战.分析了时钟偏移的产生机理,提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器,以平衡时钟网络,以及如何利用有用的时钟偏移来改善电路的时序.     

ASIC后端设计中的时钟树综合

时钟树综合是当今集成电路设计中的重要环节,因此在FFT处理器芯片的版图设计过程中,为了达到良好的布局效果,采用时序驱动布局,同时限制了布局密度;为了使时钟偏移尽可能少,采用了时钟树自动综合和手动修改相结合的优化方法,并提出了关于时钟树约束文件的设置、buffer的选型及手动修改时钟树的策略,最终完成了FFT处理器芯片的时钟树综合并满足了设计要求。     

Clock Mesh Network Design with Through‐Silicon Vias in 3D Integrated Circuits

Many methodologies for clock mesh networks have been introduced for two‐dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three‐dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through‐silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.     

Clock distribution networks in synchronous digital integratedcircuits

Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described the clock distribution networks of specific industrial circuits are surveyed and future trends are discussed     

同步电路设计中CLOCK SKEW 的分析

Clock skew是数字集成电路设计中一个重要的因素。本文比较了在同步电路设计中0clock skew和非0clock skew时钟分布对电路性能的影响，分析了通过调整时钟树中CLOCK SKEW来改善电路性能的方法，从而说明非0clock skew时钟分布是如何提高同步电路运行的最大时钟频率的。     

基于BUFGMUX与DCM的FPGA时钟电路设计

与ASIC(专用集成电路)的时钟电路相比,基于FPGA(现场可编程门阵列)的时钟电路有其自身的特点。FPGA一般提供专用时钟资源搭建时钟电路,相应的综合工具也能够自动使用这些资源,但是针对门控时钟和时钟分频电路,如果直接使用综合工具自动处理的结果,会造成较大的时钟偏差。通过合理使用DCM(数字时钟管理单元)和BUFG-MUX(全局时钟选择缓冲器)等FPGA的特殊资源,手动搭建时钟电路,可以尽可能地减少时钟偏差对电路时序的影响。     

Clock Buffer Polarity Assignment for Power Noise Reduction

Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: 1) partitioning; 2) 2-coloring on minimum spanning tree; and 3) recursive min-matching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 50% and 51%, respectively.      

A GHz MOS adaptive pipeline technique using MOS current-mode logic

This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-μm MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits     

时钟偏斜补偿电路设计与实现

时钟系统的稳定性直接决定了在不同操作环境下时钟偏斜值的大小,并影响芯片的可靠性,因此讨论了时钟偏斜补偿电路的设计与实现技术,为提高时钟系统的稳定性并提高在不同操作条件下的可靠性,从电路设计、版图实现的角度采取了有效措施,有效提高了芯片的可靠性。     

时钟延时及偏差最小化的缓冲器插入新算法

本文提出了以最小时钟延时和时钟偏差为目标的缓冲器插入新算法.基于Elmore延时模型,我们得到相邻缓冲器间的延时是缓冲器在时钟树中位置的凸函数.当缓冲器布局使所有缓冲器间延时函数具有相同导数值时,时钟延时达到最小;当所有源到各接收端点路径的延时函数值相等时,时钟偏差达到最小.对一棵给定的时钟树,我们在所有从源点到各接收端点路径上插入相同层数的缓冲器,通过优化缓冲器的位置实现时钟延时最小;通过调整缓冲器尺寸和增加缓冲器层数,实现时钟偏差最小.     

Clock generation and distribution for the first IA-64microprocessor

The clock design for the first implementation of the IA-64 microprocessor is presented. A clock distribution with an active distributed deskewing technique is used to achieve a low skew of 28 ps. This technique is capable of compensating skews caused by within-die process variations that are becoming a significant factor of the clock design. The global, regional and local clock distributions are described. A multilevel skew budget and local clock timing methodology are used to enable a high-performance design by providing support for intentional clock skew injection and time borrowing. By providing a test access port interface to the deskew architecture and the incorporation of the on-die-clock-shrink, this design is equipped with two very powerful post-silicon timing debug tools that are critical to high-performance microprocessor design and enabled quick time-to-market     

Clock Distribution Methodology for PowerPC™ Microprocessors

Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC? microprocessors that aim at alleviating some of these problems.

     

用Encounter实现Mesh-Local-Tree结构的时钟设计流程

提出了一种实用的设计流程,即在Cadencd公司的Encounter环境中去实现对网格 本地树(MLT)时钟结构的综合与分析方法.对一个实际工业设计试验的数据表明:运用Clockmesh CRS的综合方式,MLT的时钟架构相对于单一的树结构能够实现更小的时钟偏差(114ps、 171ps).同时,将这种设计流程运用于其他设计中,以比较MLT和CTS不同的设计流程.结果显示,MLT的时钟架构可以实现更小的时钟偏差,同时还可以降低缓冲器的数量,这样也弥补了单一网格结构的功耗问题.     

Low-Power Rotary Clock Array Design

Rotary clock is a recently proposed clock distribution technique based on wave propagation in transmission lines. In this paper, we investigate the problem of power minimization of rotary clock designs. Specifically, we have developed a software tool based on the method of partial element equivalent circuit that is capable of extracting the SPICE netlist from the layout specification of a rotary clock design. Using our tool, we have performed extensive analysis that links various design parameters of a rotary clock design to its oscillation frequency and power dissipation. Based on the results of our analysis, we then propose a power minimization algorithm. Our algorithm derives a rotary clock structure that dissipates the minimal power while satisfying the clock dimension requirement and oscillating at the target frequency with the given clock load. Experimental results have demonstrated that, for target operating frequencies ranging from 0.5 to 5 GHz, rotary clock designs can achieve power savings of up to 80% in comparison with conventional clock tree implementations     

合理偏差驱动的时钟线网构造及优化

提出了一种新的时钟布线算法 ,它综合了 top- down和 bottom- up两种时钟树拓扑产生方法 ,以最小时钟延时和总线长为目标 ,并把合理偏差应用到时钟树的构造中 .电路测试结果证明 ,与零偏差算法比较 ,该算法有效地减小了时钟树的总体线长 ,并且优化了时钟树的性能