Symbol timing recovery in digital subscribers loops in the presenceof residual echo and crosstalk

A general analysis is presented for the jitter performance of a common symbol timing recovery (STR) system used in a digital subscriber loop (DSL) transceiver that uses adaptive echo cancellation for high-speed digital communications. Exact analytical expressions for the mean and variance of the timing wave and for the RMS phase jitter are derived as a function of the bandwidth of the postfilter for a given set of input parameters representing a particular digital subscriber loop and its noise environment, including such effects as residual echo and crosstalk. Numerical results show that the presence of these disturbing signals can substantially degrade the STR performance. The effect of the excess bandwidth factor of the prefilter on this degradation is investigated     

A new approach for evaluating the performance of a symbol timingrecovery system employing a general type of nonlinearity

A new technique is presented for evaluating the jitter performance of a symbol timing recovery (STR) subsystem for digital data transmission systems. The STR system consists of any even-symmetric zero-memory nonlinear device followed by a narrowband filter tuned to the pulse repetition frequency. Exact analytical expressions are derived for the mean and the mean-square values of the timing wave, based on iterative computations of high-order moments of the input signal. Then, the root mean-square (RMS) jitter performance is determined as a function of various system parameters such as the power series expansion of the zero-memory nonlinear device, the rolloff factor of the input pulse shape, and the postfiltering. Finally, the numerical results obtained from some specific examples serve to illustrate several aspects of the timing recovery problem     

Analysis of a serial symbol timing recovery technique employingExclusive-OR circuit

An analysis is presented of the performance of a serial symbol timing recovery (STR) circuit which employs an Exclusive-OR circuit for conventional coherent digital modulated communication systems. The output of the timing circuit is a nearly sinusoidal wave whose zero crossings indicate the appropriate sampling instants for extraction of the data. Assuming that the data pulses entering the timing path are even symmetric, exact analytical expressions for the mean and mean-squared values of the timing wave and for the RMS phase jitter are derived as a function of various system parameters such as channel band limiting, postfiltering, delay element, and power spectral density of noise. Numerical results, also checked by computer simulations, show that considerable improvement can be obtained in jitter performance, in addition to the advantages over other STR techniques of lower cost and simpler hardware implementation     

A Digital Approach to Symbol Timing Recovery Systems

An analysis of a symbol timing recovery (STR) technique using digital processing is presented. The ratio of the discrete spectral power at the symbol rate frequency to the nearby continuous spectral power is used as a criterion of STR performance. It is shown that this power ratio equals the quality factor of the narrow bandpass filter and that it does not depend on the value of the delay element. The performance of the STR subsystem is consequently determined by the quality factor of the bandpass filter rather than by the specific delay. In addition to this, some experimental evidence that the additive channel noise has little effect on the power ratio is given. A modified phase-locked loop with anLCprefiiter is proposed to extract the symbol timing clock. This prefilter improves the acquisition and synchronization performance of the PLL. The STR technique presented here has the advantages of lower cost and simpler hardware implementation over other serial STR techniques.     

Maximum Likelihood (ML) Symbol Timing Recovery (STR) Techniques for Reconfigurable PAM and QAM Modems

A fast symbol timing recovery (STR) scheme suitable for flexible-symbol-rate, burst-mode M-ary QAM (M-QAM) and PAM (M-PAM) demodulators used in broadband communications is proposed. The maximum- likelihood (ML) estimation is used to derive a feed-forward STR strategy to achieve fast and accurate derivation of the optimum timing instant with a very short training preamble for applications requiring short packet transmission. In addition, the signal sample at the optimum timing instant is reproduced by interpolation. Analysis to derive the ML-based timing estimation algorithm and STR structure is presented. Analytical models are developed to evaluate the effects of imperfect interpolation and channel additive white Gaussian noise (AWGN) on the timing estimation performance. The derived expressions can be used for optimum interpolation filter design and selection of key parameters to achieve the required mean squared timing error. Simulation results are in good agreement with the analytical prediction.     

用声表面波滤波器实现高速光纤传输系统的定时恢复

在高速光纤数字传输系统中,尤其在长中继链路系统中,定时恢复的质量直接影响到传输系统的性能。本文分析了100Mbit/s以上光纤数字传输系统用声表面波滤波器(SAW—F)定时提取电路。首先给出SAW—F的基本原理;然后讨论了SAW—F定时提取实现方案并分析了其抖动积累特性,得出SAW—F定时提取电路的设计依据;最后,根据理论分析的结果,我们设计了一个可用于155.520Mbit/s光纤数字传输系统的SAW—F定时提取电路。分析和实验表明,SAW-F适合用作100Mbit/s以上数字传输系统的定时提取。     

全数字高速OQPSK信号解调技术分析

根据某侦察接收机的需要,基于软件无线电设计思想,分析了影响解调性能的主要因素以及解决方法,提出了一种偏移正交相移键控(OQPSK)解调器的全数字实现结构。介绍了数字下变频滤波抽取、符号同步和载波同步等模块的详细设计与实现。解调器结构简单,具有高度的稳定性、灵活性和可扩展空间,可以应用于通信、侦察接收机中。     

The effect of timing jitter on the performance of a discretemultitone system

The transmission of high-speed data over severely band-limited channels may be accomplished through the use of discrete multitone (DMT) modulation, a modulation technique that has been proposed for a number of new applications. While the performance of a DMT system has been analyzed by a number of authors, these analyses ignore the effect of timing jitter on system performance. Timing jitter becomes an increasingly important concern as higher data rates are supported and larger constellations are allowed on the DMT subchannels. Hence, in this paper, we assume that synchronization is maintained by using a digital phase-locked loop to track a pilot carrier, Given this model, we derive error rate expressions for an uncoded DMT system operating in the presence of timing jitter, and we derive an expression for the interchannel distortion that results from a varying timing offset across the DMT symbol. In addition, we investigate the performance of trellis-coded DMT modulation in the presence of timing jitter. Practical examples from the asymmetric digital subscriber line (ADSL) service are used to illustrate various results     

Timing Jitter Effects on Digital Subscriber Loop Echo Cancellers: Part II--Considerations for Squaring Loop Timing Recovery

The performance of an adaptive echo canceller at the looptimed subscriber end of a digital subscriber loop has been shown to be sensitive to jitter arising from the timing recovery subsystem. We evaluate this degradation for the common timing recovery subsystem consisting of a prefilter, a squarer, and a second-order phase-locked loop. The evaluation shows the influence of equalization, prefilter shape, and phaselocked loop parameters. A narrow-band accurately tuned prefilter, line equalizer, and a narrow-band phase-locked loop are found to be necessary for adequate performance in a 144 kbit/s bipolar-coded digital subscriber loop system employing echo cancellation.     

Investigation of Synchronization Parameters in a Digital Subscriber Loop Transmission System

The degree of echo reduction achieved in a digital subscriber loop (DSL) transceiver employing adaptive echo cancellation has previously been shown to be very sensitive to timing jitter. This paper reports the experimental study, by computer simulation, of a 144 kbit/s DSL timing recovery system incorporating a prefilter, nonlinearity, and second-order phase-locked loop. The simulations were carried out for a wide variety of line lengths, bridged-tap conditions, loop and filter parameters, and choice of nonlinearity. The results showed that a properly designed timing recovery system with a 20 khzwide prefilter allows satisfactory echo reduction performance, even for long loops with bridged taps. For shorter loops the achievable echo reduction is less, but is still sufficient to yield satisfactory performance.     

16QAM symbol timing recovery in the upstream transmission of DOCSIS standard

This paper investigates the performance of the digital symbol timing recovery schemes for 16QAM upstream transmission of the DOCSIS standard. Two forms of nonlinearity are considered: the magnitude square operation and the delay multiplication operation, both of which generate the output signal that contains the symbol timing information. The detailed analysis for the magnitude square timing recovery is given in the digital domain, and consequently the symbol timing estimate can be directly obtained by the discrete Fourier transform. The simulation results show that the magnitude square timing recovery and delay multiplication timing recovery algorithms suffer from the same problem that the estimation error is reduced slowly at high signal-to-noise ratios due to the effect of self-noise. To this end, the third scheme, which is the magnitude square timing recovery with prefilter, is examined. This scheme shows a superior performance and a comparison with the results of the other two schemes is made.     

Optimization of baud-rate timing recovery for equalization

This paper suggests the use of a prefilter before baud-rate timing recovery (Mueller and Muller 1976). It is shown that the timing phase of the baud-rate timing synchronizer can be set to a desirable timing phase, at which point a digital equalizer performs best, by proper prefiltering. The procedure for the optimal design of such a prefilter is developed under the assumption that the channel impulse response and desirable timing phase for equalization are known. Application of the proposed scheme to the gigabit Ethernet system demonstrated that prefiltering can improve receiver performance     

A 1.6 Mbps digital-QAM system for DSL transmission

An all digital-QAM system is studied here for high-speed data transmission on digital subscriber loops. All elements of the system have been fully investigated and their effects on overall system performance documented. In particular, the following issues have been explicitly addressed: utility of an adaptive error-prediction (noise-prediction) filter; equalizer size and convergence; blind equalization; choice of constellation size and center frequency; combined timing/carrier recovery; and the oversampling requirements of a numerically-controlled-oscillator (NCO) for potential use in the timing and carrier recovery loop. The paper relies on simulation results to investigate and quantify the overall interactions of the various blocks. Throughout the paper emphasis has been placed on reducing the complexity of the system for implementation on an integrated circuit (IC). It is expected that the information provided here will serve as a good starting point for an IC designer to start the implementation of a transceiver ASIC     

Passband Timing Recovery in an All-Digital Modem Receiver

The performance of conventional modem receivers, where adaptive equalization is achieved by a digital transversal filter with tap gains spaced at the symbol interval, depends critically on the choice of the sampling phase. In this paper, a digital timing recovery loop is described and analyzed in the case of passband quadrature amplitude modulated data signals. Under conditions likely to be encountered on actual voiceband communication channels, the clock phase derived is shown to prevent spectral nulls and to accurately approximate the optimum timing phase for an infinite equalizer. Computer simulations show that the proposed system is capable of fast timing acquisition.     

Feedforward symbol timing recovery technique using two samples per symbol

In this paper, a new feedforward symbol timing recovery technique using timing estimation followed by interpolation is presented for digital receivers with two samples/symbol or higher sampling rate. A few timing estimation algorithms are proposed to estimate the timing offset accurately. The basic algorithm uses only the in-phase (I) or quadrature (Q) signal for timing detection, which applies to a BPSK communication system. It is shown that the basic algorithm, when applied in quadrature modulation systems where both I and Q signals are available, can be modified slightly to yield an improved estimation precision. The mean and variance of the resulting timing estimate are analyzed and simulated, supporting a satisfactory estimation performance. It is also shown that by applying a postprocessing scheme, such as the Kalman filter, the variance can be further reduced, resulting in a smoothed timing estimate. Some of the issues concerning the implementation of the proposed technique are also addressed.     

Gardner定时同步环路参数设计及性能分析

以数字锁相环理论为依据,对Gardner定时误差检测器反馈定时环路参数的设计进行了深入研究,基于MATLAB对一阶、二阶环路性能进行了仿真,重点分析了环路阶数和等效噪声带宽对系统性能的影响,得到了等效噪声带宽与定时同步环路性能的关系,为定时同步环路的设计提供了理论依据。     

A performance lower bound for quadratic timing recovery accounting for the symbol transition density

The symbol transition density in a digitally modulated signal affects the performance of practical synchronization schemes designed for timing recovery. This paper focuses on the derivation of simple performance limits for the estimation of the time delay of a noisy linearly modulated signal in the presence of various degrees of symbol correlation produced by the various transition densities in the symbol streams. The paper develops high- and low-signal-to-noise ratio (SNR) approximations of the so-called (Gaussian) unconditional Crame/spl acute/r-Rao bound (UCRB), as well as general expressions that are applicable in all ranges of SNR. The derived bounds are valid only for the class of quadratic, non-data-aided (NDA) timing recovery schemes. To illustrate the validity of the derived bounds, they are compared with the actual performance achieved by some well-known quadratic NDA timing recovery schemes. The impact of the symbol transition density on the classical threshold effect present in NDA timing recovery schemes is also analyzed. Previous work on performance bounds for timing recovery from various authors is generalized and unified in this contribution.     

Timing recovery scheme for CV-CCMA receiver

The authors describe a baud-rate timing recovery scheme for a multiuser technique known as complex valued collaborative coding multiple access (CV-CCMA). This synchronisation scheme is suitable for digital signal processing implementation and integrates efficiently within the overall reception system. The timing function is directly derived from the samples of the received signal and adaptively employs the complex gain coefficients which are estimated by the detection process. The statistical performance of this timing function is derived by simulation for various values of E_b/N₀. It is shown that it has a low variance at the desired sampling instant     

Novel carrier recovery scheme in multicarrier digital TV system

This work is aimed at researching and analyzing the performance of carrier recovery (CR) with two transmit antennas on a multicarrier digital TV system operating in time‐selective fading channel. It is shown in the paper that CR can correct the performance degradation caused by Doppler effect when the terminal is receiving high resolution digital TV signals in a fast moving environment. To have the ability to cover a large frequency range, the CR system should do a frequency sweep first. Then the coarse and fine frequency offset estimation is introduced. Both the theoretical and simulated results give valuable insight that the CR is able to perform well with a certain amount of channel fading. The phase and noise effect on the CR performance is also studied. The CR system and the working procedure concerning CR and timing recovery are also researched to give a full solution on synchronization. Copyright © 2012 John Wiley & Sons, Ltd.     

Timing Jitter Effects on Digital Subscriber Loop Echo Cancellers: Part I--Analysis of the Effect

We analyze the effect of Subscriber-end timing recovery Circuit jitter on the performance of two types of adaptive echo cancellers that can be used for full-duplex digital transmission on two-wire subscriber loops. Under severe echo-to-far-end signal ratios, echo canceller performance is found to be quite sensitive to high-frequency jitter components. Satisfactory performance with respect to jitter requires that a narrow-band phase-locked loop, rather than a single-tuned high-Qfilter, be employed for timing recovery.