Clocked CMOS adiabatic logic with integrated single-phasepower-clock supply

The design and experimental evaluation of a clocked adiabatic logic (GAL) is described in this paper. CAL is a dual-rail logic that operates from a single-phase AC power-clock supply. This new low-energy logic makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution. CAL can also be operated from a DC power supply in a nonenergy-recovery mode compatible with standard CMOS logic. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in a 1.2 μm CMOS technology. Experimental results show that energy savings are achieved at clock frequencies up to about 40 MHz as compared to the nonadiabatic mode. Since CAL can operate both in adiabatic and nonadiabatic modes, power management strategies may be based upon switching between modes when necessary     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

QSERL: quasi-static energy recovery logic

A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8×8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz     

High-speed CMOS circuit technique

It is shown that clock frequencies in excess of 200 MHz are feasible in a 3-μm CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz     

A 16-bit carry-lookahead adder using reversible energy recoverylogic for ultra-low-energy systems

In this paper, we describe an energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic. We also describe an eight-phase, clocked power generator that requires an off-chip inductor. For the energy-efficient design of reversible logic, we explain how to control the overhead of reversibility with a self-energy-recovery circuit. A test chip was implemented with a 0.8 μm CMOS technology, which included two 16-bit carry-lookahead adders to allow fair comparison: an RERL one and a static CMOS one. Experimental results showed that the RERL adder had substantial advantages in energy consumption over the static CMOS one at low operating frequencies. We also confirmed that we could minimize the energy consumption in the RERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal     

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.     

Pushing the limits of standard CMOS

An improved clocking scheme and sharper circuit design and logic selection, which have yielded a five-to-tenfold increased in the speed of standard CMOS ICs, are discussed. The clocking strategy relies on a true single-phase clock, device sizes are varied to optimize their speed, and a precharged logic style reduces capacitive loads. The tradeoff is roughly a doubling of circuit area. The high-speed CMOS technique has been demonstrated experimentally, with good results. For example, ripple counters in 3 and 2 μm CMOS processes reached input frequencies of 400 and 750 MHz, respectively, or nearly 80 and 70% of the intrinsic speeds of these processes. Pipelined accumulators in 2 and 1.2 μm CMOS processes operated at up to 430 and 700 MHz clock frequencies, respectively. The data rate of an error correcting encoder designed for an optical fiber communication link was measured as 1.2 Gb/s, while the corresponding decoder was simulated at the same speed. In general, the circuits were found to be as robust as CMOS circuits designed in a conventional way     

采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路--complementary pass-transistor adiabatic logic(CPAL).电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MOSIS的0.25μm CMOS工艺,在50～200MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2N-2N2P电路的50%和35%.     

Ultralow-power adiabatic circuit semi-custom design

This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom PFAL carry lookahead adders and parallel multipliers were designed in a 0.6-/spl mu/m CMOS technology and verified. Post-layout simulations show that semi-custom adiabatic arithmetic units can save energy a factor 17 at 10 MHz and about 7 at 100 MHz, as compared to a logically equivalent static CMOS implementation. The energy saving obtained is also better if compared to other custom adiabatic circuit realizations and maintains high values (3/spl divide/6) even when the losses in power-clock generation are considered.     

能量回收阈值逻辑及其功率时钟产生电路

提出了能量回收阈值逻辑电路(ERTL).该电路把阈值逻辑应用到绝热电路中,降低能耗的同时也降低了电路的门复杂度.并且提出了一种高效率的功率时钟产生电路.该功率时钟电路能够根据逻辑的复杂度和工作频率,调整电路中MOS开关的开启时间,以取得最优的能量效率.为了便于功率时钟的优化设计,推导出了闭式结果.基于0.35μm的工艺参数,设计并且仿真了ERTL可编程逻辑阵列(PLA)和普通结构PLA.在20～100MHz的工作频率范围内,提出的功率时钟电路的能量效率可以达到77%～85%.仿真结果还显示,ERTL是一个低能耗的逻辑.ERTL PLA与普通结构的PLA相比,包括功率时钟电路的功耗在内,ERTL PLA仍节省65%～77%的功耗.     

基于绝热逻辑的低功耗乘法器电路设计

基于绝热开关理论的能量回收逻辑与传统的静态CMOS逻辑相比,能够大大减少电路的功率消耗。这里介绍了一种使用单相正弦电源时钟的能量回收逻辑,分别用静态CMOS逻辑和这种能量回收逻辑设计,并仿真了一个两位乘法器电路,比较了这两种电路的性能。研究表明,采用能量回收逻辑设计的乘法器显著降低了电路的功率消耗。     

All-N-logic high-speed true-single-phase dynamic CMOS logic

In this paper, a novel all-N-logic single-phase high speed dynamic CMOS logic is introduced and analyzed. The circuits achieve high speed by eliminating the need for the low-speed P-logic blocks. The use of all-N-logic allows the speed of the proposed circuits to be two to three times the speed of conventional CMOS dynamic circuits. An 2:1 frequency divider, using proposed ANL2 circuits, is simulated using 0.8 μm CMOS technology with the operating clock frequency reaching as high as 1.5 GHz. A pipelined 8-b carry generator of five-stacked NMOS transistors, which operates at a clock rate of over 710 MHz, has also been simulated. Experimental results show that the proposed circuits operate over 910 MHz implemented in a 1.2 μm CMOS technology     

A true single-phase energy-recovery multiplier

In this paper, we present the design and experimental evaluation of an 8-bit energy-recovery multiplier with built-in self-test logic and an internal single-phase sinusoidal power-clock generator. Both the multiplier and the built-in self-test have been designed in SCAL-D, a true single-phase adiabatic logic family. Fabricated in a 0.5-/spl mu/m standard n-well CMOS process, the chip has an active area of 0.47 mm/sup 2/. Correct chip operation has been verified for clock rates up to 140 MHz. Moreover, chip dissipation measurements correlate well with HSPICE simulation results. For a selection of biasing conditions that yield correct operation at 140 MHz, total measured average dissipation for the multiplier and the power-clock generator is 250 pJ per operation.     

Positive feedback in adiabatic logic

An adiabatic logic family is presented, which makes use of a CMOS positive feedback amplifier. The gate is based on dual rail logic and a cascade of such gates only needs three power/clock lines to operate. The positive feedback amplifier ensures high noise immunity and takes part in the energy recovery process     

A low-power microprocessor based on resonant energy

We describe AC-1, a CMOS microprocessor that derives most of its operating power from the clock signals rather than from dc supplies. Clock-powered circuit elements are selectively used to drive high-fan-out nodes. An inductor-based, all-resonant clock-power generator allows us to recover 85% of the clock-drive energy. The measured top frequency for the microprocessor was 58.8 MHz at 26.2 mW. The resulting overall decrease in dissipation ranges from four to five times at clock frequencies from 35 to 54 MHz. We also compare the performance of the processor to a reimplementation in static logic     

采用交流能源的低功耗CPL电路

从改变CM O S电路中能量转换模式的观点出发,研究CPL电路在采用交流能源后的低功耗特性。在此基础上提出了一种仅由nM O S构成的低功耗绝热电路——nM O S Com p lem en tary Pass-trans istor A d iabaticLog ic(nCPAL)。该电路利用nM O S管自举原理对负载进行全绝热驱动,从而减小了电路整体功耗和芯片面积。nCPAL能耗几乎与工作频率无关,对负载的敏感程度也较低。采用TSM C的0.25μm CM O S工艺,设计了一个8-b it超前进位加法器和功率时钟产生器。版图后仿真表明,在50~200 MH z频率范围内,nCPAL全加器的功耗仅为PAL-2N电路和2N-2N 2P电路的50%和35%。研究表明nCAPL适合于在VLS I设计中对功率要求较高的应用场合。     

Design of a 3-V 300-MHz low-power 8-b×8-b pipelinedmultiplier using pulse-triggered TSPC flip-flops

This paper describes the design of a low-power pipelined multiplier. It is illustrated in this paper that the power consumption of the clocking system cannot be overlooked and the design of the storage element is the key to low power. A new pulse-triggered true single-phase clocking (TSPC) flip-flop (PTTFF) is proposed for this purpose in this design. The PTTFF features true single-phase clocking, simple structure, and high performance. One PTTFF comprises only five transistors with only one controlled by the clock. Using the PTTFF together with the 14-transistor pseudo-NMOS full adder, an 8-b×8-b pipelined multiplier has been designed and implemented, employing a 0.6-μm CMOS process. When the multiplier operates at the operating frequency of 300 MHz with VDD equal to 3.3 V, it dissipates only 53% of the power of the multiplier designed with nine-transistor TSPC flip-flops under the same operating conditions. When the supply voltage for the core array is reduced to 2.5 V, the multiplier can still work up to 300 MHz with only 47% of the power of the multiplier designed using the S and D full adders and C²MOS latches with VDD equal to 3.3 V. The chip has been fabricated, and the measured power is 52.4 mW when operated at 300 MHz and 3.3 V     

LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier

As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development—of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity are common approaches used in conventional CMOS. In adiabatic switching circuits, the current flow through transistors can be significantly reduced by ensuring uniform charge transfer over the entire available time. This paper presents the simulation of this current in two-phase clocked adiabatic static CMOS logic (2PASCL) and conventional CMOS. From the SPICE simulations, at transition frequencies from 1 to 12 MHz, a 4×4-bit array 2PASCL multiplier shows a maximum reduction in power dissipation of 77% relative to that of a static CMOS. The measurement results of a 4×4-bit array 2PASCL multiplier demonstrate a 57% reduction compared to a 4×4-bit array two-phase clocked adiabatic dynamic CMOS logic (2PADCL). These results indicate that 2PASCL technology can be advantageous when applied to low-power digital devices operated at low frequencies, such as radio-frequency identification (RFID) tags, smart cards, and sensors.     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W