Low-power on-chip communication based on transition-aware global signaling (TAGS)

In this paper, we propose a new circuit structure, the transition aware global signaling (TAGS) receiver, that detects transitions at arbitrary switch points. The major performance advantage of this circuit occurs when it switches before the 50% point in the input transition. The TAGS receiver stores the next state of the line while quiet. Upon detection of a transition at the end of the line the output is temporarily driven by the stored next state. Transitions at the output of the receiver are much faster than at the end of the line since they are generated locally. Its ability to detect transitions before a standard inverter and locally generate them at its output, allows its use at the end of long interconnects with fewer repeaters for the same delay as the standard repeater paradigm. The need for fewer repeaters with the TAGS scheme results in lower power consumption for on-chip global communication, while also reducing the placement overhead involved with large buffer blocks. This is shown in the context of bus optimizations, where TAGS achieves up to 50% reduction in power compared to standard repeaters. In an industrial 0.13-/spl mu/m CMOS process, TAGS receivers enable 8-mm-long buses at 1.5-GHz clock rates without repeaters, while the traditional scheme required three repeaters on the line. An extensive analysis of crosstalk noise in the bus environment shows that TAGS can handle the noise levels produced in typical bus structures. Also, the variation of delay in the bus structure under worst-case power supply noise for the TAGS scheme is typically smaller than the delay variation using the standard repeater scheme.     

Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects

In this paper, hybrids based on current-sensing and repeaters are proposed for on-chip interconnects in an effort to overcome the limitations of these techniques. A novel receiver for current-sensing results in static power savings and allows an easier transition from current-sensing to traditional full rail voltage signals. Measurements of hybrids on a 0.18-m CMOS technology show significant gains over repeater insertion in delay across wire lengths. Hybrids can also be used in placement constrained and low-noise scenarios to achieve delay and power benefits.     

Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits

In this paper, the impact of thermal effects on low-power repeater insertion methodology is studied. An analytical methodology for thermal-aware repeater insertion that includes the electrothermal coupling between power, delay, and temperature is presented, and simulation results with global interconnect repeaters are discussed for 90- and 65-nm technology. Simulation results show that the proposed thermal-aware methodology can save 17.5% more power consumed by the repeaters compared to a thermal-unaware methodology for a given allowed delay penalty. In addition, the proposed methodology also results in a lower chip temperature, and thus, extra leakage power savings from other logic blocks.     

基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion

/sup A/ new approach to handle inductance effects for multiple signal lines is presented. The worst-case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (L/sub eff/) for multiple lines. Based on a look-up table for L/sub eff/, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlists for multiple lines, this approach greatly improves the computational efficiency and maintains accuracy for timing and signal integrity analysis. We apply these models to repeater insertion in critical paths and find that, for a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC models.     

Repeater Fault Location for a Submarine Optical Fiber Cable Transmission System

This paper introduces a repeater fault location system for a repeated submarine optical fiber transmission system of 400 Mbits/ s at 1.3μm. The repeater fault location system is used in an out-of-service test. The fault locator transmits a test signal via a main optical fiber line, in order to make a loop-back path in one of the repeaters for returning the test signals via another main optical fiber line and to measure the bit error rate (BER) of the interrogated repeater. The test signal is a kind of pseudorandom signal that includes a low frequency component, which is assigned to the repeater as a supervisory frequency tone (SVT) signal. The BER is measured by counting the number of low frequency signal phase inversions in a time. This paper first describes the test signal generating method, SVT frequency allocation, and the filter design installed in a repeater. Next, there is a discussion of how the capability of the repeater fault locator has been experimentally verified by using two submarine repeaters, including four regenerative repeater units and three submarine optical fiber cables. As a result, a BER of less than5 times 10^{-6}is accurately measured.     

Optimal interconnection circuits for VLSI

The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi2, and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.     

Simple formulas for jitter accumulation in a chain of regenerative repeaters in optical-fibre transmission systems

Simple formulas are derived for evaluating the timing-jitter accumulation in a chain of regenerative repeaters for optical-fibre transmissions. The timing circuit in each repeater is modelled as a phase-locked loop. An example of the use of these formulas is reported with reference to a 140 Mbit/s transmission system.     

11-GHz MIC QPSK Modulator for Regenerative Satellite Repeater

An 11-GHz MIC QPSK modulator for a 14/11-GHz, 120-Mbit/s regenerative satellite repeater is described. The modulator consists of cascaded 90° and 180° phase switches, realized with circulators and PIN diodes. The static and the dynamic behavior are presented. It is shown how the bit-error-rate performance is deteriorated by slow switching transients and timing errors.     

S/N performance of an AlGaAs laser preamplifier and a linear repeater system

Baseband signal-to-noise-ratio characteristics in an AlGaAs laser preamplifier and a linear repeater system were studied theoretically and experimentally. The AlGaAs laser preamplifier improved the minimum detectable power by 1.6 dB over the level achieved by direct detection with an Si APD. 37 dB regenerative repeater gain was experimentally obtained in the system with two optical repeaters at 100 Mbit/s data rate.     

Communication satellite processing repeaters

Two kinds of processing repeaters which may find application on communication satellites in the near future are described. The type I repeater allows access only if the transmitted signal contains a predetermined code structure. This serves three purposes: first, unauthorized users are excluded, second, co-channel interfering signals are not retransmitted on the downlink, so as not to waste a portion of the satellite transmitter power, and, third, removal of the interference signal at the satellite avoids having to do this at the ground receiving terminal. Thus such a repeater would find particular application where there are a large number of ground receiving stations. The type 2 repeater routes signals received at its N input terminals to be transmitted at N output terminals, thus acting as a "switchboard in the sky." Two purposes are served: first, the satellite capacity is more fully utilized in the presence of fluctuating traffic demands, and, second, single-frequency transmission and reception are possible for user ground stations, thus simplifying these stations and still allowing communication to any station in the network. It is established when the type 1 repeater is able to increase the satellite communication capability beyond that of a simple repeater and further that fairly simple filtering is sufficient on the satellite. For the type 2 repeater, a proposed frequency control plan minimizes the filtering required on the satellite where frequency division multiplex is used and reduces the amount of switching required on the satellite to N single-pole N-throw switches where time division multiplex is used without the requirement of any memory on the satellite. A summary of present-day translating repeaters, as used in the Intelsats III and IV and DSCS II satellites, is included.     

Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion

Signal propagation delay on a multi-source multi-sink bidirectional bus has a dominant effect on high-performance chips. This work presents a novel greedy algorithm that minimizes the critical propagation delay of an RLC-based bus. Based on the topology of a multi-source multi-sink bus and the RLC delay model, the proposed algorithm inserts signal repeaters into the critical path of the RLC-based bus and adjusts their sizes to minimize the maximal propagation delay. This procedure is repeated until no additional improvement is needed. Several buses with various topologies are tested using the proposed algorithm in deep submicron technologies. Experimentally, the critical delay in an RLC-based bus can be reduced dramatically by up to 62.4% with inserted repeater sizes of 24 and execution time of 1.65 s on average. Moreover, average delay reduction, repeater sizes, and running time for 0.18 μm technology are 5.8%, 6.4%, and 26.2%, respectively, better than those of 0.35 μm. Additionally, the topologies of all of the RLC-based buses with inserted repeaters in deep submicron technologies are simulated using HSPICE. The error ratio in the critical delay of a bus with inserted repeaters determined by comparison with HSPICE is 2.7% on average. The proposed algorithm is simple and extremely practical.     

一种基于目标延迟约束缓冲器插入的互连优化模型

基于分布式RLC传输线,提出在互连延迟满足目标延迟的条件下,利用拉格朗日函数改变插入缓冲器数目与尺寸来减小互连功耗和面积的优化模型. 在65nm CMOS工艺下,对两组不同类型的互连线进行计算比较,验证该模型在改善互连功耗与面积方面的优点. 此模型更适合全局互连线的优化,而且互连线越长,优化效果越明显,能够应用于纳米级SOC的计算机辅助设计和集成电路优化设计.     

Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints

Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints determine a design space for the number and size of the repeaters. The minimum power is shown to occur at the edge of the design space. With delay constraints, closed form solutions for the minimum power are developed, where the average error is 7% as compared with SPICE. With bandwidth constraints, the minimum power can be achieved with minimum-sized repeaters. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are also analyzed. By including inductance, the minimum interconnect power under a delay or bandwidth constraint decreases as compared with an RC interconnect.     

S/N and error rate performance in AlGaAs semiconductor laser preamplifier and linear repeater systems

The applications of AlGaAs semiconductor laser preamplifier and linear repeaters in single mode optical fiber transmission systems were studied through the baseband signal-to-noise ratio and bit error rate performance measurement. Experiments were carried out with the Fabry-Perot cavity laser amplifiers whose characteristics are improved by reducing the input mirror reflectivity to 6 percent. The use of a preamplifier improves the minimum detectable power by 7.4 dB over the Si-APD direct detection level when the received signal is amplified by 30 dB before photodetection. The use of two linear repeaters increases the regenerative repeater gain by 37 dB. These experimental results are in good agreement with theoretical predictions based on the photon statistic master equation analysis.     

Automatic on-off switching repeater for DS/CDMA reverse linkcapacity improvement

We propose an automatic on-off switching (AOS) repeater that is switched off automatically when there is no active user within its coverage. With the AOS repeater, we can reduce the unnecessary noise enhancement. The reverse link capacity of a DS/CDMA system with AOS repeaters is analyzed mathematically and compared with that of a system with conventional repeaters. Also, the AOS circuit in a repeater can protect the reverse link capacity of a DS/CDMA system from excessive noise enhancement by abnormal repeaters. From the numerical results, noticeable improvement with the AOS repeaters is shown     

An analysis of interconnect delay minimization by low-voltage repeater insertion

The effect of voltage-scaling on interconnect delay minimization by CMOS-repeater insertion is analyzed. Analytical models are developed to calculate the optimum number of repeaters as function of CMOS supply voltage. The analytically obtained results are in good agreement with SPICE extracted results. Analysis shows that voltage-scaling decreases power dissipation and the optimum number of repeaters required for delay minimization in long interconnects. Both resistive and inductive interconnects have been considered. At highly scaled voltages, the inductive interconnect has the advantage of lower power-delay product. It is also seen that voltage-scaling affects delay improvement due to repeater insertion.     

S/N and Error Rate Performance in AlGaAs Semiconductor Laser Preamplifier and Linear Repeater Systems

The applications of AlGaAs semiconductor laser preamplifier and linear repeaters in single mode optical fiber transmission systems were studied through the baseband signal-to-noise ratio and bit error rate performance measurement. Experiments were carried out with the Fabry-Perot cavity laser amplifiers whose characteristics are improved by reducing the input mirror reflectivity to 6 percent. The use of a preamplifier improves the minimum detectable power by 7.4 dB over the Si-APD direct detection level when the received signal is amplified by 30 dB before photodetection. The use of two linear repeaters increases the regenerative repeater gain by 37 dB. These experimental results are in good agreement with theoretical predictions based on the photon statistic master equation analysis.     

Delay-spread considerations of same-frequency repeaters in widebandchannels

In current analog cellular systems, same-frequency repeaters are very often used as gap fillers. With digital wideband systems, the use of a repeater, with its inherent group delay added to the differential propagation delay, may yield a degradation in the performance in view of the resulting delay spread. An approach to estimate the statistics of the delay spread when each link is subjected to lognormal shadowing and each channel's power-delay profile follows an exponential decay is presented. Expressions for the cumulative density function (CDF), mean value, mean-square value, and standard deviation for the RMS delay spread are derived, and their accuracy is verified through simulation