High-Performance MWIR/LWIR Dual-Band 640 × 480 HgCdTe/Si FPAs

HgCdTe grown on large-area Si substrates allows for larger array formats and potentially reduced focal-plane array (FPA) cost compared with smaller, more expensive CdZnTe substrates. The goal of this work is to evaluate the use of HgCdTe/Si for mid-wavelength/long-wavelength infrared (MWIR/LWIR) dual-band FPAs. A series of MWIR/LWIR dual-band HgCdTe triple-layer n-P-n heterojunction (TLHJ) device structures were grown by molecular-beam epitaxy (MBE) on 100-mm (211)Si substrates. The wafers showed low macrodefect density (<300 cm⁻²) and was processed into 20-μm-unit-cell 640 × 480 detector arrays which were mated to dual-band readout integrated circuits (ROICs) to produce FPAs. The measured 80-K cutoff wavelengths were 5.5 μm for MWIR and 9.4 μm for LWIR, respectively. The FPAs exhibited high pixel operabilities in each band, with noise equivalent differential temperature (NEDT) operabilities of 99.98% for the MWIR band and 99.6% for the LWIR band demonstrated at 84 K.     

An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors

This work proposes a 12 b 10 MS/s 0.11 μm CMOS successive-approximation register ADC based on a C-R hybrid DAC for low-power sensor applications. The proposed C-R DAC employs a 2-step split-capacitor array of upper seven bits and lower five bits to optimize power consumption and chip area at the target speed and resolution. A V_CM-based switching method for the most significant bit and reference voltage segments from an insensitive R-string for the last two least significant bits minimize the number of unit capacitors required in the C-R hybrid DAC. The comparator accuracy is improved by an open-loop offset cancellation technique in the first-stage pre-amp. The prototype ADC in a 0.11 μm CMOS process demonstrates the measured differential nonlinearity and integral nonlinearity within 1.18 LSB and 1.42 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 63.9 dB and a maximum spurious-free dynamic range of 77.6 dB at 10 MS/s. The ADC with an active die area of 0.34 mm² consumes 1.1 mW at 1.0 V and 10 MS/s, corresponding to a figure-of-merit of 87 fJ/conversion-step.     

A 10 b 120 MS/s 108 mW 0.18 μm CMOS ADC with a PVT-insensitive current reference

This paper proposes a 10 b 120 MS/s CMOS ADC with a PVT-insensitive current reference. The designed current reference shows a mean temperature drift of 35.2 ppm/°C in the temperature range from −25 to 100°C and a supply rejection of 1.1%/V between 1.6 and 2.0 V. The prototype ADC fabricated in a 0.18 μm 1P6M CMOS technology demonstrates a measured DNL and INL of 0.18LSB and 0.53LSB with a maximum SNDR and SFDR of 53 and 68 dB at 120 MS/s. The ADC with an active chip area of 1.8 mm² consumes 108 mW at 120 MS/s and 1.8 V while the proposed on-chip current reference consumes 0.35 mW with a die area of 0.02 mm².     

A 0.6 V 100 KS/s 8–10 b resolution configurable SAR ADC in 0.18 μm CMOS

A resolution configurable ultra-low power SAR ADC in 0.18 μm CMOS process is presented. The proposed ADC has maximum sampling rate of 100 KS/s with configurable resolution from 8 to 10 b and operates at a supply of 0.6 V. Two-stage bootstrapped switch and voltage boosting techniques are introduced to improve the performance of the ADC at low voltage. To reduce the power consumption of the analog components of the ADC, monotonic capacitor switching procedure and fully dynamic comparator are utilized. The implementation of dynamic logic further reduces the power of the digital circuits. Post-layout simulation results show that the proposed SAR ADC consumes 521 nW and achieves an SNDR of 60.54 dB at 10 b mode, resulting in an ultra-low figure-of-merit of 6.0 fJ/conversion-step. The ADC core occupies an active area of only 350 × 280 μm².     

8 Gbits/s inductorless transimpedance amplifier in 90 nm CMOS technology

This work presents the design and the measured performance of a 8 Gb/s transimpedance amplifier (TIA) fabricated in a 90 nm CMOS technology. The introduced TIA uses an inverter input stage followed by two common-source stages with a 1.5 kΩ feedback resistor. The TIA is followed by a single-ended to differential converter stage, a differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows a measured optical sensitivity of ?18.3 dBm for a bit error rate = 10^?9. A gain control circuitry is integrated with the TIA to increase its input photo-current dynamic range (DR) to 32 dB. The TIA has an input photo-current range from 12 to 500 μA without overloading. The stability is guaranteed over the whole DR. The optical receiver achieves a transimpedance gain of 72 dBΩ and 6 GHz bandwidth with 0.3 pF total input capacitance for the photodiode and input PAD. The TIA occupies 0.0036 mm² whereas the complete optical receiver occupies a chip area of 0.46 mm². The power consumption of the TIA is only 12 mW from a 1.2 V single supply voltage. The complete chip dissipates 60 mW where a 1.6 V supply is used for the output stages.     

基于 GSVD 的分布式 MIMO 雷达测向算法

针对分布式多输入多输出（multi-input multi-output, MIMO）雷达测向中存在的数据信息提取不充分、运算量偏大等问题，开展了基于广义奇异值分解（generalized singular value decomposition, GSVD）的测向算法研究，以提高低信噪比条件下的角度估计性能。首先，建立了分布式阵列MIMO雷达回波信号的统一化表征模型；其次，将分布式MIMO雷达系统接收阵列数据的多线程GSVD问题转换为一个联合优化问题，运用交替最小二乘（alternating least squares, ALS）技术实现阵列信号流行矩阵的拟合，并引入子空间类算法实现目标角度联合估计；最后，对优化问题增加l1范数约束，避免了每次迭代中进行的奇异值分解运算，降低了算法运算量。仿真实验从角度联合估计、均方误差、运算时间等方面验证了所提算法的有效性。     

A 10 Gb/s 0.25 μm SiGe modulator driver for photonic-integration

A 10 Gb/s modulator driver in SiGe 0.25 μm BiCMOS technology with a chip area of only 0.54 mm² is presented. The intentions of designing this modulator driver are to amplify small incoming data signals at 10 Gb/s and to integrate the driver together with a silicon optical phase modulator (Mach–Zehnder modulator in push–pull configuration) on the same chip. The driver is designed to have a low power-consumption of 0.68 W but a high gain (S₂₁ = 37 dB). It consists of a differential pre-amplifier with common-mode feedback and automatic gain control, which is supplied by 2.5 V. The differential output stage is supplied with 3.5 V. The driver is designed to drive a Mach–Zehnder modulator, which uses in his arms carrier depletion in a reverse biased pn junction to adjust the refractive index. The differential output (5V_pp) delivers two times a voltage between 0 and 2.5 V. Therefore no bias-T is needed at the output to assure that the diodes of the interferometer arms are in the reverse biased mode. In addition to the low-power design, a passive network instead of an additional amplifier circuit for driving the cascode transistors, which reduce the collector–emitter voltage of each transistor in the output stage below breakdown, is presented. According to bit-error-ratio (BER) measurements with a pseudo-random-bit-sequence with the length of 2³¹ ? 1 the BER is better than 10^?12 for input voltage differences down to 50 mV_pp. The rise/fall time (20–80 %) is 45/30 ps respectively.     

An 8-bit 208 MS/s SAR ADC in 65 nm CMOS

An 8-bit low-power 208MS/s SAR analog-to-digital converter is presented. To achieve a high-speed and low-power operation, a reused terminating capacitor switching procedure is proposed. The proposed switching procedure halves the capacitors leading to a significant power saving over the conventional one. Moreover, the proposed architecture relaxes the settling time of DAC and subsequently improves the conversion rate. The ADC has been simulated in SMIC 65 nm 1.2 V CMOS technology. At a 1.2-V supply and 208 MS/s, the ADC consumes 2.7 mW and achieves an SNDR of 49.6 dB, an SFDR of 61.0 dB with 100 MHz inputs.     

A mismatch-error minimized four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC

This work proposes a four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC based on various analog techniques to minimize mismatches between channels without any calibration scheme. The proposed ADC eliminates an input SHA to reduce offset mismatches, while the pipelined SAR architecture solves the problem of limited input bandwidth as observed in conventional SHA-free ADCs. In addition, a shared residue amplifier between four channels minimizes various mismatches caused by amplifiers in the first-stage MDACs. Two types of references for the residue amplifier and the SAR ADCs isolate the reference instability problem due to different functional requirements, while the shared residue amplifier uses only a single reference during the amplifying mode of each channel to reduce a gain mismatch. For high performance of the SAR ADC, high-frequency clocks with a controllable duty cycle are generated on chip without external, complicated, high-speed multi-phase clocks. The prototype 11 b ADC in a 0.13 μm CMOS shows a measured DNL and INL of 0.31 LSB and 1.18 LSB, respectively, with an SNDR of 59.3 dB and an SFDR of 67.7 dB at 100 MS/s, and an SNDR of 54.5 dB and an SFDR of 65.5 dB at 150 MS/s. The ADC with an active die area of 2.42 mm² consumes 46.8 mW at 1.2 V and 150 MS/s.     

A remotely-powered, 20 Mb/s, 5.35 pJ/bit impulse-UWB WSN tag for cm-accurate-localization sensor networks

This paper presents an ultra-low-power, low-voltage sensor node for wireless sensor networks. The node scavenges RF energy out of the environment, resulting in a limited available power budget and causing an unstable supply voltage. Hence, accurate and extensive power management is needed to achieve proper functionality. The fully integrated, autonomous system is described, including the scavenging circuitry with integrated antenna, the power detection and power control circuits, the on-chip clock reference, the UWB transmitter and the digital control circuitry. The wireless sensor node is implemented in \(0.13 \,\upmu \hbox {m}\) CMOS technology. The only external components are a storage capacitor and a UWB transmit antenna. The system consumes only \(113\, \upmu \hbox {W}\) during burst mode, while only 8 nW is consumed during the scavenging operation, enabling an efficiency of 5.35 pJ/bit which is significantly better than current state-of-the-art UWB tags. Due to the use of impulse-radio UWB, also cm-accurate localization of the tag can be achieved.     

Current-Mode Universal Biquadratic Filter with Five Inputs and Two Outputs Using Two Multi-Output CCIIs

A current-mode universal biquadratic filter with five input terminals and two output terminals is presented. The proposed circuit uses two multi-output second generation current conveyors, two grounded capacitors and three resistors. The new circuit offers the following advantages: use of the minimum number of active components, orthogonal controllability of resonance angular frequency and quality factor, use of grounded capacitors and the versatility to synthesize any type of active filter transfer functions.     

A 9-bit 2 MS/s 1 mW CMOS cyclic folding A/D converter for battery management system

In this paper, a 9-bit 2 MS/s CMOS cyclic folding A/D converter (ADC) for a battery management system is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding–interpolation architecture. The prototype ADC is implemented with a 0.35 μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48 and 60 dB, respectively, and the power consumption is about 1 mW at 3.3 V.     

A 7-bit 40 MS/s single-ended asynchronous SAR ADC in 65 nm CMOS

This paper presents a 7-bit 40 MS/s single-ended asynchronous SAR ADC intended for in-probe use in medical applications, which requires small area and good power efficiency. A single-ended architecture is proposed for a moderate resolution for its simplicity. Together with a double reference technique, the architecture reduces the area of the technology-limited large capacitors. The speed is optimized by an asymmetric delay line embedded in the asynchronous digital logic, enabling a sampling frequency of 40 MS/s. The prototype is fabricated in a 65 nm CMOS technology. Measurement shows that at 1 V supply and 40 MS/s, the ADC achieves an SNDR of 39.73 dB and an ENOB of 6.3 bit, while consuming 298.6 µW, resulting in an energy efficiency of 94.74 fJ/conversion-step. The core circuit layout only occupies 0.017 mm².     

Design, implementation and measurement of a 120 GHz 10 Gb/s phase-modulating transmitter in 65 nm LP CMOS

A novel mm-wave phase modulating transmit architecture, capable of achieving data rates as high as 10 Gb/s is presented at 120 GHz. The circuit operates at a frequency of 120 GHz. The modulator consists of a differential branchline coupler and a high speed 4-to-1 analog multiplexer with direct digital input. Both a QPSK as well as a 8QAM constellation are supported. To achieve high output power, a 9-stage power amplifier is designed and connected to the multiplexer output. The complete chip is integrated in a 65 nm low power CMOS technology. Capacitive neutralization is used to achieve high gain and good stability for the MOS devices. Also, various differential transmission line topologies are investigated to achieve high performance in terms of loss and area consumption.     

A 132 Mb/s, 1bit 4224 M samples/s sub-sampling, low-complexity and energy-efficient BPSK transceiver for all-digital 3–5 GHz IR-UWB

In this paper, a 3–5 GHz impulse radio ultra wideband BPSK transceiver is presented. A new all-digital architecture is applied in the proposed transceiver. The transceiver has no mixer and low complexity. The transmitter employs a RLC network response filter to achieve the adjustable pulse parameters, which includes pulse width, pulse bandwidth and pulse amplitude. Considering the low duty ratio, a proposed on/off output buffer in the transmitter is applied to save the power consumption. To simplify the receiver, the radio frequency input signal is amplified and sampled directly by a 1bit 4224 MHz sub-sampling ADC. The ADC comprises by 16 paralleled comparators for low power. Each comparator operates at 264 MHz and can be self-calibrated. The transceiver is implemented in SMIC 0.13 μm CMOS process at the supply of 1.2 V. The measured results show the adjustable parameters: the pulse amplitude is from 110 to 370 mV, the pulse width is from 900 to 1,600 ns and the pulse bandwidth is from 2.0 to 2.78 GHz. The data rate is 132 Mb/s between the transceiver. The transmitter and the receiver only consume 18.2 and 330 pJ/pulse, respectively. The receiver sensitivity is ?75 dBm at the bit error rate of 10^?3.     

An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS

Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm². The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm² fJ/conversion-step.     

An Analysis of the Blockcipher-Based Hash Functions from PGV

Preneel, Govaerts, and Vandewalle (1993) considered the 64 most basic ways to construct a hash function $H{:\;\:}\{0,1\}^{*}\rightarrow \{0,1\}^{n}Preneel, Govaerts, and Vandewalle (1993) considered the 64 most basic ways to construct a hash function H:   {0,1}^*? {0,1}ⁿH{:\;\:}\{0,1\}^{*}\rightarrow \{0,1\}^{n} from a blockcipher E:   {0,1}ⁿ×{0,1}ⁿ? {0,1}ⁿE{:\;\:}\{0,1\}^{n}\times \{0,1\}^{n}\rightarrow \{0,1\}^{n}. They regarded 12 of these 64 schemes as secure, though no proofs or formal claims were given. Here we provide a proof-based treatment of the PGV schemes. We show that, in the ideal-cipher model, the 12 schemes considered secure by PGV really are secure: we give tight upper and lower bounds on their collision resistance. Furthermore, by stepping outside of the Merkle–Damg?rd approach to analysis, we show that an additional 8 of the PGV schemes are just as collision resistant (up to a constant). Nonetheless, we are able to differentiate among the 20 collision-resistant schemes by considering their preimage resistance: only the 12 initial schemes enjoy optimal preimage resistance. Our work demonstrates that proving ideal-cipher-model bounds is a feasible and useful step for understanding the security of blockcipher-based hash-function constructions.     

An Extended-AMATA Indoor Propagation Model for GSM 900/1800 MHz and Wi-Fi 2.4 GHz Frequencies

In a previous article, we reported on a novel indoor propagation model; we called the AMATA model, which we applied at 900 MHz and 2.4 GHz frequencies. The model could be applied at both GSM and wireless LAN frequencies. The developed formula merits, on its own, as a novel fourth power effective attenuation equation, which relies on the number of wall separations within the floor. This paper reports an extended-AMATA indoor propagation model that generally describes university and office type buildings. A sample of four different multi-floor building structures that have a stone block type outer wall was chosen. Those flat roofed, stone built, multi floor buildings are very common, not only in Palestine, but probably in vast areas in the Middle East region. The new model benefits over the previous one, applied at 900 MHz, in that it can be extended to cellular base-stations, transmitting at 1800 MHz frequency and outdoor Wi-Fi basestations, as opposed to indoor access points, transmitting at 2.4 GHz. The work is of paramount importance to cellular and Wi-Fi network operators, transmitting at 900/1800 MHz and 2.4 GHz frequency bands. Our new model can be applied with a high confidence level to buildings, similar to the sample of buildings, we measured.     

Proportional Plus Integral Control for Set-Point Regulation of a Class of Nonlinear RLC Circuits

In this paper we identify graph-theoretic conditions which allow us to write a nonlinear RLC circuit as port-Hamiltonian with constant input matrices. We show that under additional monotonicity conditions on the network’s components, the circuit enjoys the property of relative passivity, an extended notion of classical passivity. The property of relative passivity is then used to build simple, yet robust and globally stable, proportional plus integral controllers. This work was partially supported by CONACyT, México.     

Low-power 10 Gb/s inductorless inverter based common-drain active feedback transimpedance amplifier in 40 nm CMOS

This study presents an inductorless 10 Gb/s transimpedance amplifier (TIA) implemented in a 40 nm CMOS technology. The TIA uses an inverter with active common-drain feedback (ICDF-TIA). The TIA is followed by a two-stage differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows measured optical sensitivities of ?17.7 and ?16.2 dBm at BER = 10^?12 for data rates of 8 and 10 Gb/s, respectively. The TIA has a simulated transimpedance gain of 47 dBΩ, 8 GHz bandwidth with 0.45 pF total input capacitance for the photodiode, ESD protection and input PAD. The TIA occupies 0.0002 mm² whereas the complete optical receiver occupies a chip area of 0.16 mm². The power consumption of the TIA is only 2.03 mW and the complete chip dissipates 17 mW for a 1.1 V single supply voltage. The complete optical receiver has a measured transimpedance gain of 57.5 dBΩ.