传感器网络时钟同步中基于多父节点的卡尔曼滤波算法

指出了节点每接收一个来自父节点的同步包等效于获得一个全局参考时钟的观测值,提出了使用矢量卡尔曼滤波器对来自多个父节点的观测值进行融合的算法.在多跳的无线传感器网络中,缓解了由于同步误差的逐层传递使全局时钟同步精度发生的恶化,避免网络边缘的节点产生较大的时钟误差,从而放宽了由误差传递导致的对网络规模的限制.硬件实现与数值仿真均表明相比现有协议,该算法能大幅度减小全局时钟误差,且随着节点跳数的增加而越发显著,有效地减轻了同步误差的传递问题.     

正弦波脉冲调制在空间用感应同步器驱动技术中的应用

通过对SPWM(Sine Pulse Width Modulation,正弦波脉冲宽度调制)波形的频率成分地分析,提出了SPWM波双相绕组激磁鉴相型的驱动方案,成功地将原先用于电机驱动的SPWM方法应用于空间用感应同步器的驱动上.在此驱动的基础上,对感应信号做了进一步分析,采用了Chebyshey低通滤波的信号处理方法,并用开环鉴相型处理方式得到了角度信息.试验验证了该方案的可行性.试验数据表明:该方案降低了普通双相激磁方式的功耗,测角分辨率达到了±0.45″,能够满足航天载荷设备中角度测量的需求.     

TI携手联合信源推出业界首款基于达芬奇技术的IPTV机顶盒单芯片方案

日前,德州仪器(TI)与联合信源数字音视频技术(北京)有限公司宣布推出业界首款同时支持AVS和H.264双解码的IPTV机顶盒(STB)单芯片解决方案—HM2006。该方案基于TI创新技商营     

一种电子式互感器误差校验装置的设计

本文介绍了一种针对数字量输出的便携式电子式互感器误差校验装置。该装置采用绝对测差、数字锁相环的设计方案;按照标准通信协议解码合并单元的数字量输出信号;硬件采用微处理器系统设计;软件采用微软C#语言编写;信号处理采用准同步算法。较好的解决了数字量输出电子式互感器的误差校验。     

一种19.6～27.8 GHz宽带低噪声锁相环设计

为给超高速数模转换器提供稳定的时钟信号,该文基于TSMC 40 nm CMOS工艺设计一款宽带低噪声的锁相环芯片。该芯片设计由二分频和计数器构成的分频器电路,减小吞脉冲带来的时钟抖动,从而优化噪声性能;此外,设计3位差分开关电容阵列,实现宽范围调谐的同时确保相邻调谐区间互相重叠,从而避免工艺误差导致的调谐盲区;最后还设计三阶环路滤波器及改进型差分电荷泵的电路。仿真结果表明,该锁相环具有19.6～27.8 GHz的宽带调谐范围,整体功耗为30 mW,输出频率频偏1 MHz处的相位噪声为–95.6 dBc/Hz。与其他文献的锁相环对比,在其他指标相当的前提下,该锁相环在调谐范围上具有先进性,可作为高性能的时钟信号。     

基于0.12微米CMOS技术10GHz压控振荡器的设计

基于0.12微米CMOS技术10GHz环形电压控制振荡器(VCO)可用于SDH(STM-64)和SONET(OC-192)光接收机的时钟恢复电路。该振荡器设计的关键是采用了容性源极耦合电流放大器(SC3A)。由于带通特性的SC3A的特点,该压控振荡器有较大的调谐范围及较低的噪声,其中心频率为10GHz,可以在8.4GHz至10.6GHz的频率范围内工作,在偏离中心频率1MHz处的单边带相位噪声约为-85dBc/Hz。     

一种数字温度计的设计和校准

设计了一种数字温度计,由单片机STC89C52、温度传感器DS18B20、四位一体共阳极数码管、按键、报警模块、升(降)温模块及电源模块组成.提出了由单片机与温度传感器组成的硬件设计方案,软件系统包括主函数、LED驱动子程序、温度设置子程序、报警处理子程序以及DS18B20温度采集子程序等部分.利用恒温槽和二等标准铂电阻温度计对数字温度计做了静态校准.最后评定了温度示值校准结果的不确定度.     

一种用于SDH 2Mb／s支路输出口的全数字锁相环

提出了一种具有极低通带宽度的二阶全数字锁相环，并采用了一些非线性的改进措施，从而使其具有一个相对较宽的牵出范围，以恢复Ｅ１支路信号的时钟。硬件实验证实，它完全可以满足ＩＴＵ－Ｔ对拌动抑制特性的要求。同时由于数字集成电路技术成熟，其集成度远远高于模拟集成电路；因而采用全数字锁相环对系统的集成有明显的益处。     

基于MSP430单片机的高精度转台角速率校准系统设计

为了对转台进行现场校准,设计了一套基于MSP430单片机的高精度转台角速率校准系统,实现了对速率转台的高准确度角速率测量校准,并给出了测试实例.该系统采用定时测角法,用高准确度恒温温补晶振作为时间基准时钟,用单片机控制正交解码芯片HCTL-2032,对圆光栅传感器输出的正交信号进行解码计数,同时设计了硬件周期同步电路,...     

多带超宽带OFDM系统射频频率合成器的研制

针对通信系统中使用的传统锁相式频率合成器难同步的缺点,提出了采用直接数字频率合成器(DDS)和锁相环(PLL)技术设计应用于多带.正交频分复用超宽带(MB-OFDM UWB)系统的射频频率合成器方案,并研制了用于试验的合成器.该方案可有效解决系统射频电路的同步问题,提高频率分辨率,降低相位噪声,改善载波频偏对 OFDM 系统影响,提高系统性能,同时还可以降低基带算法的复杂度.仿真与测试结果表明,该频率合成器指标满足 MB-OFDM UWB 系统要求,可应用于实用系统中.     

Optimal Synchronization of Local Clocks by GPS 1PPS Signals Using Predictive FIR Filters

In this paper, we discuss optimal synchronization of local clocks using Global Positioning System (GPS) one-pulse-per-second (1PPS) timing signals. To eliminate sawtooth errors that are peculiar to the 1PPS signals and optimally steer the clock errors each $M$ seconds, we propose the use of a ramp-predictive finite-impulse-response (FIR) filter that is known to be optimal for clock models on large averaging horizons. A low-pass filter is used to smooth the hold filter output between the optimally predicted points. A GPS-locked crystal clock has been investigated in detail in terms of the time interval error, Allan deviation, and precision time protocol (PTP) variance. A high-efficiency implementation of the proposed synchronization algorithm is experimentally demonstrated.      

高速光纤通信用定时恢复判决电路

对光纤通信用定时恢复判决电路进行了研究,设计了由1μm耗尽型GaAs金属－半导体势垒场效应晶体管（MESFET）器件构成的判决电路和时钟提取电路。判决电路的基本单元为源耦合场效应晶体管逻辑（SCFL）电路,时钟提取电路由预处理器和锁相环构成。模拟分析表明,时钟提取电路可从输入信号中提取判决电路所需的时钟脉冲,频率达2．5GHz,判决电路可对输入信号进行正确的“0”、“1”判决,并经时钟抽样后,输出正确的数字信号,传输速率达2．5Gbit/s。实测电路可正确判决,时钟抽样后,输出正确的数字信号,传输速率达2．5Gbit/s。     

A synchronized two-phase sinewave generator for AC metrology systemcompensations

A slave audio two-phase sinewave generator, which can be directly synchronized to a master generator, is described here. It can be used in ac metrology setups to provide additional “compensation” signals, traditionally derived with expensive multidecade inductive voltage divider networks. The generator is based on two direct digital synthesis (DDS) chips, programmed via the parallel printer PC interface; their clock is provided by a phase-locked loop circuit, which ensures frequency and phase synchronization of the DDS outputs with the master generator. The synchronization reference signal can be provided via an optical link reference channel, which avoids interference and ground loops. In its present implementation, the output voltage is V_peak =10 V, frequency range 500 Hz-4 kHz. Total harmonic distortion is contained to -65 dB, and amplitude stability is better than 500 μV/V over 24 h     

Novel on-chip circuit for jitter testing in high-speed PLLs

We propose a novel on-chip circuit to measure the jitter present at the output of phase-locked loops (PLLs) used for generating phase-synchronous, frequency-multiplied clocks. This measure is performed at every period of the PLL reference clock, and a digital output encoded by means of a thermometer code is obtained. Such a digital output is then analyzed in order to confirm on-chip whether or not the jitter is within specifications. Our proposed circuit is able to test PLLs providing an output frequency in the gigahertz range. Compared to alternate techniques, that proposed here requires lower costs in terms of area overhead (requiring an area <12% of the PLLs' area) and circuit complexity, while featuring higher or comparable accuracy and lower or comparable test time.     

幅值可调的EMCCD倍增时钟驱动电路设计

针对EMCCD——CCD97的应用,本文在分析其增益曲线特点和倍增时钟功耗的基础上,给出了CCD97倍增时钟的驱动电路设计。该电路由隔离推挽电路和可调电源组成:隔离推挽电路产生倍增时钟的波形;可调电源可以调节倍增时钟的幅值,且调节精度随着幅值的增加而增加,可以部分抵消CCD97倍增增益曲线的非线性。文章最后给出了驱动电路的输出波形以及CCD97的倍增图像。结果表明所设计的驱动电路能够产生符合要求的倍增时钟,可以实现CCD97的倍增成像和增益调整。     

基于FPGA和DSP的激光陀螺信号处理电路设计

研究机械抖动激光陀螺的信号读出系统,设计激光陀螺的信号处理电路。光电转换后的微弱电流信号经过前置放大电路转化为电压方波信号,在FPGA中进行鉴相解调以及可逆计数,最后由DSP实现机抖偏频解噪和低通数字滤波。与激光陀螺联合测试并将结果输出至上位机,结果表明设计的电路实现了对激光陀螺输出信号的有效采集,满足激光陀螺功能测试的需要。     

Placement of clock gates in time-of-flight optoelectronic circuits

Time-of-flight synchronized optoelectronic circuits capitalize on the highly controllable delays of optical waveguides. Circuits have no latches; synchronization is achieved by adjustment of the lengths of waveguides that connect circuit elements. Clock gating and pulse stretching are used to restore timing and power. A functional circuit requires that every feedback loop contain at least one clock gate to prevent cumulative timing drift and power loss. A designer specifies an ideal circuit, which contains no or very few clock gates. To make the circuit functional, we must identify locations in which to place clock gates. Because clock gates are expensive, add area, and increase delay, a minimal set of locations is desired. We cast this problem in graph-theoretical form as the minimum feedback edge set problem and solve it by using an adaptation of an algorithm proposed in 1966 [IEEE Trans. Circuit Theory CT-13, 399 (1966)]. We discuss a computer-aided-design implementation of the algorithm that reduces computational complexity and demonstrate it on a set of circuits.     

Research on Time Synchronization Method Under Arbitrary Network Delay in Wireless Sensor Networks

To cope with the arbitrariness of the network delays, a novel method, referred to as the composite particle filter approach based on variational Bayesian (VB-CPF), is proposed herein to estimate the clock skew and clock offset in wireless sensor networks. VB-CPF is an improvement of the Gaussian mixture kalman particle filter (GMKPF) algorithm. In GMKPF, Expectation-Maximization (EM) algorithm needs to determine the number of mixture components in advance, and it is easy to generate overfitting and underfitting. Variational Bayesian EM (VB-EM) algorithm is introduced in this paper to determine the number of mixture components adaptively according to the observations. Moreover, to solve the problem of data packet loss caused by unreliable links, we propose a robust time synchronization (RTS) method in this paper. RTS establishes an autoregressive model for clock skew, and calculates the clock parameters based on the established autoregressive model in case of packet loss. The final simulation results illustrate that VB-CPF yields much more accurate results relative to GMKPF when the network delays are modeled in terms of an asymmetric Gaussian distribution. Moreover, RTS shows good robustness to the continuous and random dropout of time messages.     

基于模式识别的自适应时钟重置检测算法

为解决网络测量中因测量主机的时钟重置导致单向时延测量误差的问题,根据时钟重置发生的不定时性和发生次数未知的特征,提出了一种基于模式识别的自适应时钟重置检测算法（PRBA）。该算法基于模式识别中的最大最小距离聚类算法对单向时延测量值进行聚类,同时利用时间序列技术中的一种低通滤波器过滤出噪声区间,从而有效识别网络行为特征,自适应地检测时钟值瞬时调整方式的时钟重置。实验结果表明,与现有同类算法相比,该算法具有较高准确性和自适应性。     

Soft-decision array decoding for volume holographic memory systems

We study the use of soft-decision array decoding in a volume holographic memory (VHM) system that is corrupted by interpixel interference (IPI) and detector noise. Soft-decision methods can unify equalization and error decoding. A highly parallel array decoder is presented in the context of two-dimensional low-pass channel mitigation and error correction. The new decoding algorithm is motivated by iterative turbo-decoding methods and is capable of incorporating a priori knowledge of the corrupting IPI channel during decoding. The resulting joint detection decoding algorithm is shown to offer VHM capacity and density performance superior to that of hard-decision n = 255 Reed-Solomon codes in concatenation with a Wiener filter.