Pentacene organic thin-film transistors-molecular ordering andmobility

Pentacene-based organic thin-film transistors (TFT's) with field-effect mobility as large as 0.7 cm²/V·s and on/off current ratio larger than 10⁸ have been fabricated. Pentacene films deposited by evaporation at elevated temperature at low-to-moderate deposition rates have a high degree of molecular ordering with micrometer-sized and larger dendritic grains. Such films yield TFT's with large mobility. Films deposited at low temperature or by flash evaporation have small grains and poor molecular ordering and yield TFT's with low mobility     

Dependence of thin film transistor characteristics on thedeposition conditions of silicon nitride and amorphous silicon

The systematic relation between thin film transistors' (TFT's) characteristics and the deposition conditions of amorphous silicon nitride (a-SiN) films and hydrogenated amorphous silicon (a-Si:H) films is investigated. It is observed that field effect mobility μ_FE and threshold voltage V_th of the TFT's strongly depend on the deposition conditions of these films. The maximum μ_FE of 0.88 cm²/V·s is obtained for the TFT of which a-SiN film is deposited at a pressure of 85 Pa. This phenomenon is due to the variation of the interface states density between a-Si:H film and a-SiN film     

The effects of NH3 plasma passivation on polysiliconthin-film transistors

The NH₃ plasma passivation has been performed for the first time on the polycrystalline silicon (poly-Si) thin-film transistors (TFT's). It is found that the TFT's after the NH₃ plasma passivation achieve better device performances, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability as well as thermal stability than the H₂-plasma devices. These improvements were attributed to not only the hydrogen passivation of the grain-boundary dangling bonds, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films     

Low-temperature polysilicon thin-film transistors fabricated fromlaser-processed sputtered-silicon films

In an effort to develop a simple low-temperature high-performance polysilicon thin-film transistor (TFT) technology, we report a fabrication process featuring laser-crystallized sputtered-silicon films. This top Al-gate coplanar TFT process subjects the substrate to a maximum temperature of 300°C, and produces devices with mobilities up to 450 cm²/Vs, on/off current ratios greater than 10⁷ , without using a post-hydrogenation step. We believe these results represent the highest performance TFT's to date fabricated from sputtered silicon films     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

Characteristics of polysilicon thin-film transistor with thin-gatedielectric grown by electron cyclotron resonance nitrous oxide plasma

Polysilicon thin-film transistors (poly-Si TFT's) with thin-gate oxide grown by electron cyclotron resonance (ECR) nitrous oxide (N₂ O)-plasma oxidation is presented. ECR N₂O-plasma oxidation successfully incorporates nitrogen atoms at the SiO₂/poly-Si interface, consequently forms a nitrogen-rich layer with Si≡N bonds at a binding energy of 397.8 eV. ECR N₂ O-plasma oxide grown on poly-Si films shows higher breakdown fields than thermal oxide. The fabricated poly-Si TFT's with N₂ O-plasma oxide show better performance than those with ECR O₂ -plasma oxide, which results not only from the smooth interface but also oxygen- and nitrogen-plasma passivation     

Effects of NH3 plasma passivation on N-channelpolycrystalline silicon thin-film transistors

The NH₃-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH₃-plasma passivation achieve better device performance, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability than the H₂-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH₃-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's     

Enhanced H2-plasma effects on polysilicon thin-filmtransistors with thin ONO gate-dielectrics

This letter reports that passivation effects of the H₂-plasma on the polysilicon thin-film transistors (TFT's) were greatly enhanced if the TFT's have a thin Si₃N₄ film on their gate-dielectrics. Compared to the conventional devices with only the SiO₂ gate dielectric, the TFT's with Si ₃N₄ have much more improvement on their subthreshold swing and field-effect mobility after H₂-plasma treatment     

Characteristics of top-gate thin-film transistors fabricated onnitrogen-implanted polysilicon films

The electrical characteristics of top-gate thin-film transistors (TFT's) fabricated on the nitrogen-implanted polysilicon of the doses ranging from 2×10¹²-2×10¹⁴ ions/cm² were investigated in this work. The experimental results showed that nitrogen implanted into polysilicon followed by an 850°C 1 h annealing step had some passivation effect and this effect was much enhanced by a following H₂-plasma treatment. The threshold voltages, subthreshold swings, ON-OFF current ratios, and field effect mobilities of both n-channel and p-channel TFT's were all improved. Moreover, the hot-carrier reliability was also improved. A donor effect of the nitrogen in polysilicon was also found which affected the overall passivation effect on the p-channel TFT's     

Performance improvement obtained for thin-film transistorsfabricated in prepatterned laser-recrystallized polysilicon

Thin-film transistors (TFT's) are fabricated in polysilicon films that are laser recrystallized either before or after active-area definition. We find the the performance of TPT's fabricated in active areas that are prepatterned before laser recrystallization is dramatically improved. For example, the field-effect mobility is increased by a factor of three, the threshold voltage is reduced from 5.32 V to 0.07 V, and the subthreshold slope is cut in half for W/L = 10 μm/10 μm TFT's. All TFT's discussed utilize gas-immersion laser-doped source and drain junctions and are unhydrogenated     

High-performance thin-film transistors in low-temperature crystallized LPCVD amorphous silicon films

Thin-film transistors (TFT's) were fabricated in low-temperature (550°C) crystallized amorphous LPCVD silicon films. The performance of these devices was found to depend upon the deposition temperature. Low threshold voltages and effective mobilities as high as 32 cm²/V.s are reported for devices fabricated in 150-nm-thick films with maximum processing temperature of 860°C. The performance of these devices is shown to be far superior to devices fabricated in as-deposited polycrystalline silicon films.     

Fabrication of thin film transistors by chemical mechanicalpolished polycrystalline silicon films

A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm²/V-s, ON/OFF current ratio of 1.1 10⁷, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's     

High performance low temperature polysilicon thin film transistorusing ECR plasma thermal oxide as gate insulator

Electron cyclotron resonance (ECR) plasma thermal oxide has been investigated as a gate insulator for low temperature (⩽600°C) polysilicon thin-film transistors based on solid phase crystallization (SPC) method. The ECR plasma thermal oxide films grown on a polysilicon film has a relatively smooth interface with the polysilicon film when compared with the conventional thermal oxide and it shows good electrical characteristics. The fabricated poly-Si TFT's without plasma hydrogenation exhibit field-effect mobilities of 80 (60) cm²/V·s for n-channel and 69 (48) cm²/V·s for p-channel respectively when using Si₂ H₆(SiH₄) source gas for the deposition of active poly-Si films     

Laser-recrystallized polycrystalline-silicon thin-film transistors with low leakage current and high switching ratio

Laser-recrystallized polycrystalline-silicon thin-film transistors (poly-Si TFT's) with offset-gate structures have been fabricated on quartz substrates. Offset-gate structures make it possible to reduce leakage currents to as low as 5 × 10^-14A/µm at VD= 10 V, more than two orders of magnitude lower than that in conventional-structure poly-Si TFT's. Optimization of the dopant concentration in offset-gate regions minimizes degradation of drive current, enabling high switching ratios exceeding 10⁸. Calculations based on the quasi-two-dimensional model indicate that the reduction in leakage current is due to a decrease in lateral electric field strength in the drain depletion region.     

Single-crystal silicon transistors in laser-crystallized thin films on bulk glass

High-performance thin-film transistors (TFT) have been fabricated in single-crystal silicon thin films on bulk fused silica. Deposited films of polycrystalline silicon were patterned to control nucleation and growth of single-crystal material in pre-selected areas and encapsulated with a dielectric layer (e.g., SiO2) in preparation for laser crystallization. Patterning also minimized microcracking during crystallization. The patterned silicon layer was crystallized with a scanning CO2laser, which produced islands with preferred crystal orientation. The single crystallinity of the islands was established with transmission electron microscopy after transistor evaluation. The silicon islands were processed with conventional microelectronic techniques to form metal-oxide-semiconductor-field-effect transistors operating in the n-channel enhancement mode. The devices display exceptional electrical characteristics with "low-field" channel mobilities > 1000 cm²/V sec and leakage currents < 10 pA, for a Channel length of 12 µm and width of 20 µm. Achievement of high-performance TFT's with the combined features of microcrack suppression, preferred orientation, and selected-area crystallization render CO2- laser processing of silicon films a viable and versatile basis for a silicon-on-insulator technology.     

p-Channel TFT's using magnetron-sputtered Ta2O5films as gate insulators

Metal-gate thin-film transistors (TFT's) have been fabricated in layers of laser-recrystallized polycrystalline silicon on fused quartz substrates at processing temperatures below 625°C. Tantalum pentoxide (Ta2O5) was used as a gate insulator instead of a conventional thermally grown silicon dioxide (SiO2). Ta2O5gate insulator was deposited onto the recrystallized silicon layer at room temperature, using an RF-magnetron sputtering system. The reactive ion etching method, using CF4as a reactive gas, was employed in patterning deposited Ta2O5. These TFT's have exhibited p-channel depletion-mode characteristics with a threshold voltage of 2.5 V and a transconductance of 70 µS at Vg= - 2 V. An on-off current ratio exceeding 10⁵has been obtained.     

Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO2 gate insulator

Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO₂) gate insulator were realized by low-temperature processes (<620°C). The physical, chemical, and electrical properties of the new dielectric layer were clarified. The low-temperature processed (LTP) poly-Si TFT's with W/L=200 μm/10 μm had an on-off current ratio of 4.95×10 ⁶ at V_D=5 V, a field effect mobility of 25.5 cm ²/V·s at V_D=0.1 V, a threshold voltage of 6.9 V, and a subthreshold swing of 1.28 V/decade at V_D=0.1 V. Effective passivation of defects by plasma hydrogenation can improve the characteristics of the devices. The off-state current (I_L) mechanisms of the LTP poly-Si TFT's were systematically compared and clarified. The I_L is divided into three regions; the I_L is attributable to a resistive current in region I (low gate bias), to pure thermal generation current in region II (low drain bias), and to Frenkel-Poole emission current in region III (high gate bias and drain bias)     

High-performance p-channel poly-Si TFT's using electron cyclotronresonance hydrogen plasma passivation

This letter presents a summary of the first detailed investigation of electron cyclotron resonance (ECR) hydrogen plasma exposure treatments of p-channel poly-Si thin film transistors (TFT's). It is shown that ECR hydrogenation can be much more efficient than RF hydrogenation. Poly-Si p-channel TFT's fabricated at low temperatures (⩽625°C) and passivated with the ECR hydrogenation treatment are shown to exhibit ON/OFF current ratios of 7.6×10⁷, subthreshold swings of 0.62 V/decade, threshold voltages of -4.6 V, and hole mobilities over 18 cm²/V.s     

A new technology for fast switching circuits on glass

A low-temperature self-aligned photolithographic process is described to fabricate fast switching digital poly-CdSe thin-film transistors (TFT's) on glass, The use of sintered CdSe-In2Se3mixtures as an evaporation source for the semiconductor resulted in TFT's with attractive static and dynamic characteristics. The measured inverter delay for a 20-µm technology was 75 ns.     

A high-performance polysilicon thin-film transistor using XeClexcimer laser crystallization of pre-patterned amorphous Si films

A high-performance polysilicon thin-film transistor (TFT) fabricated using XeCl excimer laser crystallization of pre-patterned amorphous Si films is presented. The enhanced TFT performance over previous reported results is attributed to pre-patterning before laser crystallization leading to enhanced lateral grain growth. Device performance has been systematically investigated as a function of the laser energy density, the repetition rate, and the number of laser shots. Under the optimal laser energy density, poly-Si TFT's fabricated using a simple low- temperature (⩽600°C) process have field-effect mobilities of 91 cm²/V·s (electrons) and 55 cm²/V·s (holes), and ON/OFF current ratios over 10 ⁷ at V_Ds=10 V. The excellent overall TFT performance is achieved without substrate heating during laser crystallization and without hydrogenation. The results also show that poly-Si TFT performance is not sensitive to the laser repetition rate and the number of laser shots above 10