Characterization of ageing failures on power MOSFET devices by electron and ion microscopies

Extreme electro-thermal fatigue tests have been performed to failure on power MOSFET devices that were later observed using electron and ion microcopy. At variance with devices from the former technology generation, fatigue-induced ageing of these components is observed only in the source metallization zone. An increase in drain–source resistance may originate from both a loss of contact between the wire bondings and the Al layer and/or an extensive decohesion between the metal grains. Failure modes include local melting of the Al and creation of eutectic alloys.     

Universal mechanisms of Al metallization ageing in power MOSFET devices

Power MOSFET devices are extensively used in the automotive industry, but their modes of ageing are still poorly understood. Here we focus on the physical degradation mechanisms that occur in the upper Al-based metallization layer (source). This layer undergoes thermo-mechanical structural modifications due to the combination of electrical pulses and differences between the various coefficients of thermal expansion. Using electronic and ionic microscopy, we show that ageing can be divided in 2 phases where dislocation-based plasticity and then grain boundary diffusion become predominant. As a result, grain boundary grooving and surface roughening follows a partial division of the later in disconnected Al grains. Such a degradation of the metallization has been widely observed in various devices. It may lead to the observed augmentation of resistivity and also to the focusing of the various current paths, promoting hot spots and subsequent failure.     

Power capability limits of power MOSFET devices

With technology progression, power capability becomes a more critical concern in optimizing power device designs in various smart power IC applications. Interaction between the electrical and thermal entities is essential in understanding the power capability limit of the semiconductor devices in both transient and steady-state operations. This paper reports the fundamental mechanisms of the electrical–thermal coupling process during power dissipation and the characteristics of the power capability limits of the power MOSFET devices from the scope of intrinsic and extrinsic factors that affect the power capability. An electrothermally driven snapback breakdown is discussed in detail to investigate the physical mechanism of the power capability limits of an LDMOS power transistor. Both simulation and experimental results are in good agreement, indicating that the electrothermal snapback breakdown would occur at lower junction temperature than the intrinsic junction temperature.     

Optimized trench MOSFET technologies for power devices

Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V_DB =55 V (R_sp=0.2 mΩ-cm², k _D=5.7 Ω-pF) and V_DB=35 V (R_sp=0.15 mΩ-cm², k_D =4.3 Ω-PF) were developed where V_DB is the drain-source avalanche breakdown voltage, R_sp is the specific on-state resistance, and k_D=R _spC_sp is the input device technology factor where C_sp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model     

Cosmic ray induced failures in high power semiconductor devices

Recently it was discovered that cosmic rays can induce failures in large area, high voltage power semiconductors. The effect is of considerable practical significance and has caused a series of equipment malfunctions in the field. We show that earlier attempts to model the physical process of failure are inadequate and introduce a new model. From the new model we derive a phenomenological law for the failure rate as a function of simple design parameters. The law has only two adjustable parameters and the parameters have a simple physical interpretation. In particular the parameter which describes the slope of the extrapolation curve from test to field conditions can be calculated from first principles and shows good agreement with the experimentally found value. This gives high confidence in the validity of the extrapolation law. We give mathematical expressions and diagrams to quantify the safe operating conditions with respect to the cosmic ray failure mode for all high voltage power devices. This allows the user to design reliable power electronic equipment and the semiconductor manufacturer to design devices virtually immune against this failure mode.     

A new approach for physical-based modelling of bipolar power semiconductor devices

This paper presents a hybrid approach for accurate modelling and simulation of power bipolar semiconductor devices. Model’s core is a numerical module that solves ambipolar diffusion equation (ADE) trough a variational formulation followed by an approximate solution with a finite element approach. The approach enables easy implementation of physics-based power semiconductor models into standard SPICE circuit simulators. Implementation is done trough a set of current controlled RC nets describing charge carrier distribution in low-doped zone. Other zones of devices are modelled with classical methods in an analytical module. With this hybrid approach it is possible to describe dynamic and static device behaviour with good accuracy while maintaining low execution times. The methodology is presented and applied for power p–i–n diodes, power bipolar junction transistors and insulated gate bipolar transistors. Models are validated comparing experimental and simulated results.     

Electrical parameters degradation law of MOSFET during ageing

A new method to extract the different electrical parameters lifetime of MOS transistors submitted to hot carriers degradation is proposed. This method leads to error on the lifetime below 15%, even if the parameter variation measurement reaches only 8%. The robustness of this method has been tested for various biases of stress and different technologies representative of different ageing mechanisms. Finally this method is a good indicator of the degradation modes occurring during the stress.     

功率MOSFET寄生振荡的研究

针对MOSFET易产生寄生振荡的问题,在分析振荡与驱动电路各参数之间关系的基础上,通过加入合适的驱动电阻来解决该振荡问题,从而保证MOSFET能在高速应用场合的可靠运行.该方法具有实现简单、成本低廉、安全可靠的特点.经过1000W纯正弦波逆变器设计应用,实验波形表明驱动电路的合理性和有效性.     

Analytical loss model of power MOSFET

An accurate analytical model is proposed in this paper to calculate the power loss of a metal-oxide semiconductor field-effect transistor. The nonlinearity of the capacitors of the devices and the parasitic inductance in the circuit, such as the source inductor shared by the power stage and driver loop, the drain inductor, etc., are considered in the model. In addition, the ringing is always observed in the switching power supply, which is ignored in the traditional loss model. In this paper, the ringing loss is analyzed in a simple way with a clear physical meaning. Based on this model, the circuit power loss could be accurately predicted. Experimental results are provided to verify the model. The simulation results match the experimental results very well, even at 2-MHz switching frequency.     

精确测量功率MOSFET的RDs(on)

电阻值的测量通常比较简单.但是,对于非常小阻值的测量,我们必须谨慎对待我们所做的假定.对于特定的几何形状,如电线,Kelvin方法是非常精确的.可以使用类似的方法来测量均匀样本的体电阻率和面电阻率,但是所使用的公式不同.在这些情况下,必须考虑探针间距和样本厚度.仅仅运用Kelvin法本身无法保证精度.如果布局和连接数发生变化,就很难精确地预测非均匀几何形状的电阻.     

功率MOSFET并联均流仿真分析

研究多个功率MOSFET并联均流问题。由于市场上的MOSFET功率普遍较小,当电路要求大电流时可将多个MOSFET并联,但一些因素会造成并联管电流分配不均从而导致管子损坏。从器件参数、栅极驱动参数、电路布线三方面分析了各参数对并联功率MOSFET电流分配以及功率损耗的影响,对各参数使用Pspice软件进行了仿真并提出了相应的均流措施,通过仿真结果进行对比,结果验证了均流措施的有效性。仿真方法和结论对实际应用有一定的参考价值。     

MOSFET的损耗分析与工程近似计算

根据MOSFET的简化模型,分析了导通损耗和开关损耗,通过典型的修正系数,修正了简化模型的极间电容。通过开关磁铁电源的实例计算了工况下MOSFET的功率损耗,计算结果表明该电源中工况下的MOSFET功率损耗比较小,可以长时间可靠稳定的工作。     

Fault modelling of ECL devices

Logic behaviour of an ECL OR/NOR gate under different physical faults is examined. It is shown that the conventional stuck-at fault modelling may be inadequate for obtaining a sufficiently high fault coverage. A new augmented stuck-at fault model is presented which provides a better coverage of physical failures.<>     

表面贴装功率MOSFET封装的演进

功率MOSFET不仅是一种普遍使用的电子元件,而且也代表着一个众所周知的事实--硅技术的创新已经与满足市场需求的表面贴装封装的创新形影不离.     

Computer-aided simulation of power MOSFET switch-mode convertors

A computer-aided modelling procedure for power MOSFET switching convertors is reported. Results show dynamic turn-on and turn-off device waveforms, peak stresses, switching trajectory and transient switching losses. Excellent agreement is demonstrated between predicted and measured switching characteristics on an experimental high-frequency high-efficiency convertor.     

The threshold-voltage model of MOSFET devices with localizedinterface charge

A new analytic threshold-voltage model for a MOSFET device with localized interface charges is presented. Dividing the damaged MOSFET device into three zones, the surface potential is obtained by solving the two-dimensional (2-D) Poisson's equation. Calculating the minimum surface potential, the analytic threshold-voltage model is derived. It is verified that the model accurately predicts the threshold voltage for both fresh and damaged devices. Moreover, the Drain-Induced Barrier Lowering (DIBL) and substrate bias effects are included in this model. It is shown that the screening effects due to built-in potential and drain bias dominate the impact of the localized interface charge on the threshold voltage. Calculation results show that the extension, position and density of localized interface charge are the main issues influencing the threshold voltage of a damaged MOSFET device. Simulation results using a 2-D device simulator are used to verify the validity of this model, and quite good agreement is obtained for various cases     

A continuous compact MOSFET model for fully- and partially-depletedSOI devices

A fully continuous compact SOI MOSFET model for circuit simulations, that automatically accounts for the for the correct body depletion condition, is presented. Unlike previously reported models that are derived for either fully-depleted (FD) or partially-depleted (PD) devices, our model accounts for the possible transitions between FD and PD behavior during the device operation     

Quantum mechanical influences on short-channel effects inultra-thin MOSFET/SIMOX devices

This paper describes an explicit manifestation of quantum-mechanical influences on the short channel effects (SCE) in the threshold voltage of ultra-thin buried-channel MOSFET/SIMOX devices. The theoretical model predicts an abnormal quantum mechanical SCE (QSCE) in extremely thin SOI layer. It also predicts that the QSCE becomes much salient at low temperatures, which is examined quantitatively by experiments