Characterization of ageing failures on power MOSFET devices by electron and ion microscopies

Extreme electro-thermal fatigue tests have been performed to failure on power MOSFET devices that were later observed using electron and ion microcopy. At variance with devices from the former technology generation, fatigue-induced ageing of these components is observed only in the source metallization zone. An increase in drain–source resistance may originate from both a loss of contact between the wire bondings and the Al layer and/or an extensive decohesion between the metal grains. Failure modes include local melting of the Al and creation of eutectic alloys.     

Universal mechanisms of Al metallization ageing in power MOSFET devices

Power MOSFET devices are extensively used in the automotive industry, but their modes of ageing are still poorly understood. Here we focus on the physical degradation mechanisms that occur in the upper Al-based metallization layer (source). This layer undergoes thermo-mechanical structural modifications due to the combination of electrical pulses and differences between the various coefficients of thermal expansion. Using electronic and ionic microscopy, we show that ageing can be divided in 2 phases where dislocation-based plasticity and then grain boundary diffusion become predominant. As a result, grain boundary grooving and surface roughening follows a partial division of the later in disconnected Al grains. Such a degradation of the metallization has been widely observed in various devices. It may lead to the observed augmentation of resistivity and also to the focusing of the various current paths, promoting hot spots and subsequent failure.     

Power capability limits of power MOSFET devices

With technology progression, power capability becomes a more critical concern in optimizing power device designs in various smart power IC applications. Interaction between the electrical and thermal entities is essential in understanding the power capability limit of the semiconductor devices in both transient and steady-state operations. This paper reports the fundamental mechanisms of the electrical–thermal coupling process during power dissipation and the characteristics of the power capability limits of the power MOSFET devices from the scope of intrinsic and extrinsic factors that affect the power capability. An electrothermally driven snapback breakdown is discussed in detail to investigate the physical mechanism of the power capability limits of an LDMOS power transistor. Both simulation and experimental results are in good agreement, indicating that the electrothermal snapback breakdown would occur at lower junction temperature than the intrinsic junction temperature.     

Gate leakage-current analysis and modelling of planar and trench power SiC MOSFET devices in extreme short-circuit operation

The purpose of this paper is to present a complete analysis of the gate leakage-current behaviour during short-circuit (SC) fault operation of 1200 V SiC MOSFETs from five different manufacturers including planar and trench-gate structures. Ruggedness and gate leakage level are evaluated in function of the chip size. Finally, the gate leakage current is modelled and the robustness tested.     

Optimized trench MOSFET technologies for power devices

Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V_DB =55 V (R_sp=0.2 mΩ-cm², k _D=5.7 Ω-pF) and V_DB=35 V (R_sp=0.15 mΩ-cm², k_D =4.3 Ω-PF) were developed where V_DB is the drain-source avalanche breakdown voltage, R_sp is the specific on-state resistance, and k_D=R _spC_sp is the input device technology factor where C_sp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model     

国产中高压抗辐照功率MOSFET单粒子效应

功率金属-氧化物半导体场效应晶体管(MOSFET)空间使用时易遭受重离子轰击产生单粒子效应(单粒子烧毁和单粒子栅穿)。本文对国产新型中、高压(额定电压250 V,500 V)抗辐照功率MOSFET的单粒子辐射效应进行了研究,并采取了有针对性的加固措施,使器件的抗单粒子能力显著提升。结果表明：对250 V KW2型功率MOSFET器件进行Bi粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到250 V;对500 V KW5型功率MOSFET器件进行Xe粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到400 V,并且当栅压为-15 V时,安全工作的漏极电压也达到400 V,说明国产中、高压功率MOSFET器件有较好的抗单粒子能力。     

Switching times variation of power MOSFET devices after electrical stress

The switching performance of three power MOSFET devices with different oxide thicknesses is studied after several periods of electrical stress. The thickest oxide reveals a large accumulation of positive charges in the oxide bulk after small periods of stress. These charges affect the switching parameters by increasing the rise time and by decreasing the fall time. Larger periods of stress reduce the effect of positive charges by increasing the number of interface states. The threshold voltage is decreased by the effect of a positive oxide charge and increases with the appearance of interface states. All these phenomena are less observable as we reduce the oxide thickness.     

Cosmic ray induced failures in high power semiconductor devices

Recently it was discovered that cosmic rays can induce failures in large area, high voltage power semiconductors. The effect is of considerable practical significance and has caused a series of equipment malfunctions in the field. We show that earlier attempts to model the physical process of failure are inadequate and introduce a new model. From the new model we derive a phenomenological law for the failure rate as a function of simple design parameters. The law has only two adjustable parameters and the parameters have a simple physical interpretation. In particular the parameter which describes the slope of the extrapolation curve from test to field conditions can be calculated from first principles and shows good agreement with the experimentally found value. This gives high confidence in the validity of the extrapolation law. We give mathematical expressions and diagrams to quantify the safe operating conditions with respect to the cosmic ray failure mode for all high voltage power devices. This allows the user to design reliable power electronic equipment and the semiconductor manufacturer to design devices virtually immune against this failure mode.     

An optimized junctionless GAA MOSFET design based on multi-objective computation for high-performance ultra-low power devices

An analytical investigation has been proposed to study the subthreshold behavior ofjunctionless gates all around （JLGAA） MOSFET for nanoscale CMOS analog applications. Based on 2-D analytical analysis, a new subthreshold swing model for short-channel JLGAA MOSFETs is developed. The analysis has been used to calculate the subthreshold swing and to compare the performance of the investigated design and conventional GAA MOSFET, where the comparison of device architectures shows that the JLGAA MOSFET exhibits a superior performance with respect to the conventional inversion-mode GAA MOSFET in terms of the fabrication process and electrical behavior in the subthreshold domain. The analytical models have been validated by 2-D numerical simulations. The proposed analytical models are used to formulate the objectives functions. The overall objective function is formulated by means of a weighted sum approach to search the optimal electrical and dimensional device parameters in order to obtain the better scaling capability and the electrical performance of the device for ultra-low power applications.     

A new approach for physical-based modelling of bipolar power semiconductor devices

This paper presents a hybrid approach for accurate modelling and simulation of power bipolar semiconductor devices. Model’s core is a numerical module that solves ambipolar diffusion equation (ADE) trough a variational formulation followed by an approximate solution with a finite element approach. The approach enables easy implementation of physics-based power semiconductor models into standard SPICE circuit simulators. Implementation is done trough a set of current controlled RC nets describing charge carrier distribution in low-doped zone. Other zones of devices are modelled with classical methods in an analytical module. With this hybrid approach it is possible to describe dynamic and static device behaviour with good accuracy while maintaining low execution times. The methodology is presented and applied for power p–i–n diodes, power bipolar junction transistors and insulated gate bipolar transistors. Models are validated comparing experimental and simulated results.     

Electrical parameters degradation law of MOSFET during ageing

A new method to extract the different electrical parameters lifetime of MOS transistors submitted to hot carriers degradation is proposed. This method leads to error on the lifetime below 15%, even if the parameter variation measurement reaches only 8%. The robustness of this method has been tested for various biases of stress and different technologies representative of different ageing mechanisms. Finally this method is a good indicator of the degradation modes occurring during the stress.     

Semi-numerical modelling of an n-channel irradiated MOSFET

A semi-numerical model of a metal-oxide-semiconductor field effect transistor (MOSFET) has been developed for theoretical examination of the effect of ionizing radiation on the characteristics of the device. The present model utilizes the radiation-induced changes in the flat-band voltage to estimate the change in the surface charge carrier concentration which in turn changes the mobility of the surface channel and affects the source-to-drain current. For the first time a model of an irradiated MOSFET has been presented that incorporates the effect of both transverse and longitudinal electric fields in the transport of the carriers in the surface channel. The present model can also be used to determine the characteristics of the device in the pre-irradiated condition. The validity of the model has been established by comparing and contrasting the results in the preirradiated condition with those obtained using other models, including twodimensional models. The results obtained on the basis of our model are compared with reported experimental results and also a SPICE (Level 3) model in the post-irradiated condition. It is found that our model gives a better fit to the reported experimental results as compared with SPICE models.-The present model is expected to yield fairly accurate results for estimation of I _D V _D characteristics and the transfer characteristics, even for a short channel device.     

功率MOSFET管的热疲劳寿命预测

通过ANSYS有限元分析软件对TO-263器件功率MOSFET管进行电-热-机械耦合分析,并对其热疲劳寿命作出预测。首先进行了瞬态热分析,得出了芯片的热通量变化图,在此基础上进行模拟并通过Coffin-Manson定律预测功率MOSFET管的热疲劳寿命。结果表明,TO-263器件功率MOSFET管的热疲劳失效循环总数为6 113。     

A new thermal model for power MOSFET devices accounting for the behavior in unclamped inductive switching

The main aim of this work was the analysis of the transient thermal behavior of several typologies of power MOSFET devices. The commonly used thermal model has been applied to different device families with different breakdown voltages. The large difference between the experimental results and the simulation runs, performed with the classic approach for some kinds of devices, leads to correct the traditional mathematical thermal model and to build up a new one in which the real size of the epitaxial layer is taken into account. A new model will be shown performing a better fitting with the experimental evidence and confirming its suitability for all the proofed families of devices. The mathematical process developed to build up the model is shown, and a comparison is carried out between the measured temperatures on the device and estimation by the model. The results discussed in the paper show how the developed model allows a better fitting of the achieved model with the experimental measurements and demonstrate the suitability of the proposed approach.     

功率MOSFET寄生振荡的研究

针对MOSFET易产生寄生振荡的问题,在分析振荡与驱动电路各参数之间关系的基础上,通过加入合适的驱动电阻来解决该振荡问题,从而保证MOSFET能在高速应用场合的可靠运行.该方法具有实现简单、成本低廉、安全可靠的特点.经过1000W纯正弦波逆变器设计应用,实验波形表明驱动电路的合理性和有效性.     

Analytical loss model of power MOSFET

An accurate analytical model is proposed in this paper to calculate the power loss of a metal-oxide semiconductor field-effect transistor. The nonlinearity of the capacitors of the devices and the parasitic inductance in the circuit, such as the source inductor shared by the power stage and driver loop, the drain inductor, etc., are considered in the model. In addition, the ringing is always observed in the switching power supply, which is ignored in the traditional loss model. In this paper, the ringing loss is analyzed in a simple way with a clear physical meaning. Based on this model, the circuit power loss could be accurately predicted. Experimental results are provided to verify the model. The simulation results match the experimental results very well, even at 2-MHz switching frequency.     

功率MOSFET并联均流仿真分析

研究多个功率MOSFET并联均流问题。由于市场上的MOSFET功率普遍较小,当电路要求大电流时可将多个MOSFET并联,但一些因素会造成并联管电流分配不均从而导致管子损坏。从器件参数、栅极驱动参数、电路布线三方面分析了各参数对并联功率MOSFET电流分配以及功率损耗的影响,对各参数使用Pspice软件进行了仿真并提出了相应的均流措施,通过仿真结果进行对比,结果验证了均流措施的有效性。仿真方法和结论对实际应用有一定的参考价值。     

精确测量功率MOSFET的RDs(on)

电阻值的测量通常比较简单.但是,对于非常小阻值的测量,我们必须谨慎对待我们所做的假定.对于特定的几何形状,如电线,Kelvin方法是非常精确的.可以使用类似的方法来测量均匀样本的体电阻率和面电阻率,但是所使用的公式不同.在这些情况下,必须考虑探针间距和样本厚度.仅仅运用Kelvin法本身无法保证精度.如果布局和连接数发生变化,就很难精确地预测非均匀几何形状的电阻.     

Fault modelling of ECL devices

Logic behaviour of an ECL OR/NOR gate under different physical faults is examined. It is shown that the conventional stuck-at fault modelling may be inadequate for obtaining a sufficiently high fault coverage. A new augmented stuck-at fault model is presented which provides a better coverage of physical failures.<>