A 0.18 μm CMOS TIA Plus Limiting Amplifier with a 5.3 GHz Overall Bandwidth for Fiber Optic Communications

A shunt series feedback transimpedance amplifier (TIA), based on a current amplifier using a zero–pole cancellation, followed by a 6 stages limiting amplifier (LA), proves to be suitable as receiver front-end for a 8 Gb/s communications over fiber optic. The front-end is realized with a 0.18 μm CMOS technology, and shows the following performances: the TIA has a 50 dBΩ transimpedance gain and 5.5 GHz bandwidth, the LA has a 46 dB gain and 7.9 GHz bandwidth. The differential voltage swing at the output is 300 mV. The total power consumption is 112 mW.     

Design, modeling, and characterization of monolithically integratedInP-based (1.55 μm) high-speed (24 Gb/s) p-i-n/HBT front-endphotoreceivers

High-speed, long-wavelength InAlAs/InGaAs OEIC photoreceivers based on a p-i-n/HBT shared layer integration scheme have been designed, fabricated and characterized. The p-i-n photodiodes, formed with the 6000 Å-thick InGaAs precollector layer of the HBT as the absorbing layer, exhibited a responsivity of ~0.4 A/W and a -3 dB optical bandwidth larger than 20 GHz at λ=1.55 μm. The fabricated three-stage transimpedance amplifier with a feedback resistor of 550 Ω demonstrated a transimpedance gain of 46 dBΩ and a -3 dB bandwidth of 20 GHz. The monolithically integrated photoreceiver with a 83 μm p-i-n photodiode consumed a small dc power of 35 mW and demonstrated a measured -3 dB optical bandwidth of 19.5 GHz, which is the highest reported to date for an InAlAs/InGaAs integrated front-end photoreceiver. The OEIC photoreceiver also has a measured input optical dynamic range of 20 dB. The performance of individual devices and integrated circuits was also investigated through detailed CAD-based analysis and characterization. Transient simulations, based on a HSPICE circuit model and previous measurements of eye diagrams for a NRZ 2³¹-1 pseudorandom binary sequence (PRBS), show that the OEIC photoreceiver is capable of operation up to 24 Gb/s     

应用于10Gb/s光接收机的全差分CMOS跨阻前置电路设计

设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 mVpp的差分电压信号。该全差分前置放大电路采用0.18 m CMOS工艺进行设计,当光电二极管电容为250 fF时,该光接收机前置放大电路的跨阻增益为92 dB,-3 dB带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 pA/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 mW,限幅放大器功耗为80 mW,输出缓冲器功耗为40 mW,其芯片面积为800 m1 700 m。     

7.1 GHz bandwidth monolithically integratedIn0.53Ga0.47As/In0.52Al0.48As PIN-HBT transimpedance photoreceiver

A monolithically integrated photoreceiver using an InAlAs/InGaAs HBT-based transimpedance amplifier has been fabricated and characterized. The p-i-n photodiode is implemented using the base-collector junction of the HBT. The 5 μm×5 μm emitter area transistors have self-aligned base metal and non-alloyed Ti/Pt/Au contacts. Discrete transistors demonstrated f_T and f_max of 54 GHz and 51 GHz, respectively. The amplifier demonstrated a -3 dB transimpedance bandwidth of 10 GHz and a gain of 40 dBΩ. The integrated photoreceiver with a 10 μm×10 μm p-i-n photodiode showed a -3 dB bandwidth of 7.1 GHz     

27-GHz bandwidth high-speed monolithic integrated optoelectronicphotoreceiver consisting of a waveguide fed photodiode and anInAlAs/InGaAs-HFET traveling wave amplifier

A monolithic integrated photoreceiver for 1.55-μm wavelength has been designed for operation in a 20-Gb/s synchronous digital hierarchy system (SDH/SONET), based on a new integration concept. The optoelectronic integrated circuit (OEIC) receiver combines a waveguide-integrated PIN-photodiode and a traveling wave amplifier in coplanar waveguide layout with four InAlAs/InGaAs/InP-HFETs (0.7-μm gate length). The receiver demonstrates a bandwidth of 27 GHz with a low frequency transimpedance of 40 dBΩ. This is, to our knowledge, the highest bandwidth ever reported for a monolithic integrated photoreceiver on InP. Furthermore, a receiver sensitivity of -12 dBm in the fiber (20 Gb/s, BER=10^-9) and an overall optical input dynamic range of 27 dB is achieved. Optical time domain multiplex (TDM) system experiments of the receiver packaged in a module show an excellently shaped eye pattern for 20 Gb/s and an overall sensitivity of -30.5 dBm (BER=10^-9) [including erbium doped fiber amplifiers (EDFA)]     

DC-40 GHz光通信系统用GaAs PHEMT驱动放大器。

利用0.2μmGaAsPHEMT工艺研制了40Gb/s光通信系统中的光调制器驱动放大器。该放大器芯片采用有源偏置的七级分布放大器结构,工作带宽达到40GHz,输入输出反射损耗约-10dB,功率增益14dB,功耗700mW,最大电压输出幅度达到7V。两级芯片级连后,功率增益约27dB,在40Gbit/s速率下得到清晰的眼图。     

（英）D波段InP基高增益、低噪声放大芯片的设计与实现

利用90-nm InAlAs/InGaAs/InP HEMT工艺设计实现了两款D波段（110~170 GHz）单片微波集成电路放大器。两款放大器均采用共源结构,布线选取微带线。基于器件A设计的三级放大器A在片测试结果表明：最大小信号增益为11.2 dB@140 GHz,3 dB带宽为16 GHz,芯片面积2.6×1.2 mm2。基于器件B设计的两级放大器B在片测试结果表明：最大小信号增益为15.8 dB@139 GHz,3dB带宽12 GHz,在130~150 GHz频带范围内增益大于10 dB,芯片面积1.7×0.8 mm2,带内最小噪声为4.4 dB、相关增益15 dB@141 GHz,平均噪声系数约为5.2 dB。放大器B具有高的单级增益、相对高的增益面积比以及较好的噪声系数。该放大器芯片的设计实现对于构建D波段接收前端具有借鉴意义。     

10Gb/s GaAs PHEMT电流模跨阻抗光接收机前置放大器

采用0.5μm GaAs PHEMT工艺研制了一种单电源共栅电流模跨阻抗前置放大器(TIA).测量得到放大器-3dB带宽为7.5GHz,跨阻增益为45dBΩ;输入输出电压驻波比(VSWR)均小于2;等效输入噪声电流谱密度在14.3～22pA/ Hz之间,平均值为17.2pA/ Hz.在输入10Gb/s非归零(NRZ)伪随机二进制序列(PRBS)信号下,放大器输出眼图清晰,具有14ps的定时抖动和138mV的峰峰电压.     

Very-high-speed InP/InGaAs HBT ICs for optical transmission systems

High-speed ICs for 20-40-Gbit/s time-division multiplexing (TDM) optical transmission systems have been designed and fabricated by using InP/InGaAs heterojunction-bipolar-transistor (HBT) technology. This paper describes four analog ICs and four digital ICs: a five-section cascode distributed amplifier with a gain of 9.5 dB and a bandwidth of 50 GHz, a three-section single-end-to-differential converter with a bandwidth of 40 GHz, a cascode differential amplifier with a gain of 10.5 dB and a bandwidth of 64 GHz, a preamplifier with a gain of 41.9 dBΩ and a bandwidth of 39 GHz, a modulator driver with an output voltage swing of 3.2 V peak-to-peak and rise and fall times of 16 and 15 ps, a 40-Gbit/s selector, a 20-Gbit/s D-type flip-flop, and a static frequency divider with an operating range of 2.0-44.0 GHz. All the ICs were measured with on-wafer RF probes     

A 3 GHz transimpedance OEIC receiver for 1.3-1.55 μm fiber-opticsystems

A high-performance metal-semiconductor-metal high-electron-mobility transistor (MSM-HEMT) transimpedance photoreceiver fabricated using OMCVD-grown InAlAs/InGaAs heterostructures on an InP substrate is discussed. This is the first demonstration of a monolithically integrated receiver amplifier that incorporates a cascode amplifier stage and a Schottky diode level-shifting stage implemented on InP-based optoelectronic integrated circuit (OEIC) photoreceivers. The transimpedance amplifier has an open-loop gain of 5.7 and a bandwidth of 3.0 GHz, which represent the highest gain and the highest speed performance reported for 1.3-1.55-μm-wavelength OEIC receivers     

DC to 2.5 Gb/s×4 p-i-n/HBT optical receiver array with lowcrosstalk

A multichannel optical receiver with an In_0.53Ga_0.47As p-i-n photodetector array and a monolithic transimpedance amplifier array fabricated in AlGaAs/GaAs HBT (heterojunction bipolar transistor) technology were demonstrated. Both flip-chip rear-illuminated and wire-bonded front-illuminated detector configurations were implemented. The transimpedance was 65 dBΩ, and the 3-dB bandwidth was measured to be 2.3 GHz. By using series feedback, the transimpedance gain of each cell was matched to within 0.5 dB, and the entire array operated from a single 5-V supply. A low interchannel crosstalk of less than -40 dB was measured up to a data rate of 2 Gb/s     

A Si BiCMOS transimpedance amplifier for 10-Gb/s SONET receiver

A transimpedance amplifier packaged with an InP p-i-n photodiode has been demonstrated for 10-Gb/s SONET receiver. The shunt feedback transimpedance amplifier is fabricated in 0.25-μm modular Si BiCMOS technology. The transimpedance of 55 dBΩ is achieved at a bandwidth of 9 GHz by applying shunt peaking and filter termination at the input. The optical sensitivity of -17 dBm was measured at 10 Gb/s for a bit-error rate of 10^-12     

20GHz宽带GaAs PHEMT分布式前置放大器

采用0.5μm GaAs PHEMT工艺研制了一种光接收机分布式前置放大器.该放大器-3dB带宽接近20GHz,跨阻增益约46dBΩ;在50MHz~16GHz范围内,输入、输出电压驻波比(VSWR)均小于2;带内噪声系数在3.03~6.5dB之间,平均等效输入噪声电流密度约为14.6pA/ Hz ;在输入10Gb/s非归零(NRZ)伪随机二进制序列(PRBS)信号下,放大器输出眼图清晰,具有12ps的定时抖动和166mV峰峰电压.     

Fabrication of 40 Gb/s Front‐End Optical Receivers Using Spot‐Size Converter Integrated Waveguide Photodiodes

We fabricated 40 Gb/s front‐end optical receivers using spot‐size converter integrated waveguide photodiodes (SSC‐WGPDs). The fabricated SSC‐WGPD chips showed a high responsivity of approximately 0.8 A/W and a 3 dB bandwidth of approximately 40 GHz. A selective wet‐etching method was first adopted to realize the required width and depth of a tapered waveguide. Two types of electrical pre‐amplifier chips were used in our study. One has higher gain and the other has a broader bandwidth. The 3 dB bandwidths of the higher gain and broader bandwidth modules were about 32 and 42 GHz, respectively. Clear 40 Gb/s non‐return‐to‐zero (NRZ) eye diagrams showed good system applicability of these modules.     

108 GHz 功率放大器模块研制

介绍了105～108 GHz 频段功率放大器模块的设计和制作。模块由波导微带转换、功率芯片及芯片偏置电路组成。讨论了放大模块的设计及加工测试过程,并对模块中的关键技术波导-微带转换进行详细阐述。波导-微带转换采用E面微带探针激励完成。通过理论分析及仿真优化后设计出转换模型并制作出实物进行测试。单个转换在100～110GHz 频段内插入损耗小于0.6 dB,回波小于-10 dB。测试结果表明设计的波导-微带转换具有插入损耗小,工作频段宽的优点。采用此转换制作的功率放大模块在105～108GHz频段上增益大于13dB,输出功率大于200mW,达到预期设计指标。     

10Gb/s GaAs PHEMT高增益光接收机前置放大器

基于南京电子器件研究所0.5μm GaAs PHEMT工艺,研制了一种高增益级联式光接收机前置放大器.作为前级的跨阻抗放大器的-3dB带宽为10GHz,小信号增益为9dB;作为后级的分布式放大器的-3dB带宽接近20GHz,小信号增益为12dB;级联前置放大器小信号增益达21.3dB,跨阻增益为55.3dBΩ,在输入10Gb/s非归零伪随机二进制序列下,放大器输出眼图清晰、对称、信噪比优于跨阻放大器,分布放大器不能校正的输入波形失真也得到显著改善.     

Design of a 32.7-GHz bandwidth AGC amplifier IC with wide dynamicrange implemented in SiGe HBT

A wide-bandwidth automatic gain control (AGC) amplifier IC was developed using a self-aligned selective-epitaxial SiGe heterojunction bipolar transistor (HBT). A transimpedance load circuit was used, and its damping factor was optimized to achieve a wide bandwidth of 32.7 GHz. Capacitor peaking was introduced to the second variable-gain amplifier in order to obtain a wide gain dynamic range of 19 dB. The amplifier IC has a noise figure of 18 dB and an eye pattern at 25 Gb/s     

GaAs-based high-gain direct-coupled distributed preamplifier using active feedback topology

A single-chip ultra-high gain distributed amplifier (DA) was developed using commercial GaAs PHEMT foundry for 40-Gb/s base band applications. Two seven-section DAs are directly coupled using a lumped dc level-shift circuit. The dc bias level of the second-stage DA can be tuned using the level-shift circuit for optimum gain. The gain of each DA stage has been optimized using a novel active feedback cascode topology, which allows the gain bandwidth product to be maximized while avoiding instability problems. The fabricated single-chip DA with a size of 2.1 mm /spl times/ 2.3 mm showed a high gain of 28 dB, and an average noise figure of 4.6 dB with a 41 GHz bandwidth. The corresponding transimpedance gain was 62 dB/spl Omega/ and the input noise current density was 14.5 pA//spl radic/Hz. The gain bandwidth product (GBWP) is 1030 GHz, which corresponds to the highest performance using GaAs technology for 40 Gb/s applications.     

50-GHz-bandwidth baseband amplifiers using GaAs-based HBTs

Baseband amplifiers of 50 GHz, using high-performance AlGaAs/InGaAs HBTs with regrown base contacts, have been demonstrated. The transimpedance amplifier achieved a bandwidth of 50.8 GHz with a gain of 11.6 dB. The transimpedance characteristics were of 49.3-GHz bandwidth with a 43.7-dBΩ transimpedance gain. The resistive and mirror Darlington feedback amplifiers, respectively, achieved a bandwidth of 54.7 GHz with a gain of 8.2 dB and a bandwidth of more than 60.0 GHz with a gain of 6.3 dB. To date, these are the widest bandwidths reported for lumped-circuit-design amplifiers. These results suggest the great potential of these amplifiers for use in future optical communication, microwave and millimeter-wave applications     

1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS tech nology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capaci tance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resis tance is 50 Ω, and the average input noise current spectral density is 9.7 pA/(Hz)~(1/2). Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.