Effect of Oxygen Binding Energy on the Stability of Indium‐Gallium‐Zinc‐Oxide Thin‐Film Transistors

From a practical viewpoint, the topic of electrical stability in oxide thin‐film transistors (TFTs) has attracted strong interest from researchers. Positive bias stress and constant current stress tests on indium‐gallium‐zinc‐oxide (IGZO)‐TFTs have revealed that an IGZO‐TFT with a larger Ga portion has stronger stability, which is closely related with the strong binding of O atoms, as determined from an X‐ray photoelectron spectroscopy analysis.     

Top Interface Engineering of Flexible Oxide Thin‐Film Transistors by Splitting Active Layer

The effect of active layer (amorphous indium–gallium–zinc oxide, a‐IGZO) splitting on the performances of back‐channel‐etched (BCE) and etch‐stopper (ES) thin‐film transistors (TFTs) on polyimide substrate is studied. While the performance of BCE TFT is independent of active layer splitting, the performance of ES TFT is improved significantly by splitting the active layer into 2–4 µm width along the channel. The saturation mobility is enhanced from 24.3 to 76.8 cm² V^?1 s^?1 and this improvement is confirmed by the operation of a ring oscillator made of the split TFTs also. X‐ray photoelectron spectroscopy (XPS) analysis of the split a‐IGZO indicates the incorporation of F at the island interface and thus improves the top interface quality, leading to a significant improvement of the top channel TFT mobility from 0.25 to 24.22 cm² V^?1 s^?1. This improvement is correlated with bonding of In with F at the top interface according to XPS results. The bias stability, hysteresis, and mechanical stability of the ES a‐IGZO TFT are also remarkably improved by splitting a‐IGZO active layer.     

Design of Novel Dielectric Surface Modifications for Perylene Thin‐Film Transistors

Dielectric surface modifications (DSMs) can improve the performance of organic thin‐film transistors (OTFTs) significantly. In order to gain a deeper understanding of this performance enhancement and to facilitate high‐mobility transistors, perylene based devices utilizing novel dielectric surface modifications have been produced. Novel DSMs, based on derivates of tridecyltrichlorosilane (TTS) with different functional end‐groups as well as polymeric dielectrics have been applied to tailor the adhesion energy of perylene. The resulting samples were characterized by electronic transport measurements, scanning probe microscopy, and X‐ray diffraction (XRD). Measurements of the surface free energy of the modified dielectric enabled the calculation of the adhesion energy of perylene upon these novel DSMs by the equation‐of‐state approach. These calculations demonstrate the successful tailoring of the adhesion energy. With these novel DSMs, perylene thin‐films with a superior film quality were produced, which enabled high‐performance perylene‐based OTFTs with high charge‐carrier mobility.     

Organic Thin‐Film Transistors with Anodized Gate Dielectric Patterned by Self‐Aligned Embossing on Flexible Substrates

An upscalable, self‐aligned patterning technique for manufacturing high‐ performance, flexible organic thin‐film transistors is presented. The structures are self‐aligned using a single‐step, multi‐level hot embossing process. In combination with defect‐free anodized aluminum oxide as a gate dielectric, transistors on foil with channel lengths down to 5 μm are realized with high reproducibility. Resulting on‐off ratios of 4 × 10⁶ and mobilities as high as 0.5 cm² V^?1 s^?1 are achieved, indicating a stable process with potential to large‐area production with even much smaller structures.     

Impact of Morphology on Printed Contact Performance in Carbon Nanotube Thin‐Film Transistors

Silver nanoparticles (NPs) are the most widely used conductive material throughout the printed electronics space due to their high conductivity and low cost. However, when interfacing with other prominent printed materials, such as semiconducting carbon nanotubes (CNTs) in thin‐film transistors (TFTs), silver is suboptimal when compared to more expensive or less conductive materials. Consequently, there would be significant value to improving the interface of printed silver to CNT films. In this work, the impact of nanostructure morphology on the electrical properties of printed silver and nanotube junctions in CNT‐TFTs is investigated. Three distinct silver morphologies (NPs, nanoflakes – NFs, and nanowires – NWs) are explored with top‐ and bottom‐contact configurations for each. The NF morphology in a top‐contact configuration is found to yield the best electrical interface to CNTs, resulting in an average contact resistance of 1.2 MΩ ? µm. Beyond electrical performance, several trade‐offs in morphology selection are revealed, including print resolution and process temperature. While NF inks produce the best interfaces, NP inks produce the smallest features, and NW inks are compatible with low processing temperatures (<80 °C). These results outline the trade‐offs between silver contact morphologies in CNT‐TFTs and show that contact morphology selection can be tailored for specific applications.     

Gate Capacitance‐Dependent Field‐Effect Mobility in Solution‐Processed Oxide Semiconductor Thin‐Film Transistors

Solution‐processed oxide semiconductors (OSs) used as channel layer have been presented as a solution to the demand for flexible, cheap, and transparent thin‐film transistors (TFTs). In order to produce high‐performance and long‐sustainable portable devices with the solution‐processed OS TFTs, the low‐operational voltage driving current is a key issue. Experimentally, increasing the gate‐insulator capacitances by high‐k dielectrics in the OS TFTs has significantly improved the field‐effect mobility of the OS TFTs. But, methodical examinations of how the field‐effect mobility depends on gate capacitance have not been presented yet. Here, a systematic analysis of the field‐effect mobility on the gate capacitances in the solution‐processed OS TFTs is presented, where the multiple‐trapping‐and‐release and hopping percolation mechanism are used to describe the electrical conductivity of the nanocrystalline and amorphous OSs, respectively. An intuitive single‐piece expression showing how the field‐effect mobility depends on gate capacitance is developed based on the aforementioned mechanisms. The field‐effect mobility, depending on the gate capacitances, of the fabricated ZnO and ZnSnO TFTs clearly follows the theoretical prediction. In addition, the way in which the gate insulator properties (e.g., gate capacitance or dielectric constant) affect the field‐effect mobility maximum in the nanocrystalline ZnO and amorphous ZnSnO TFTs are investigated.     

金属氧化物IGZO薄膜晶体管的最新研究进展

最近几年,金属氧化物IGZO薄膜晶体管成为研究热点,具有高迁移率、稳定性好、制作工艺简单等优点,备受人们关注。文章综述了制作金属氧化物IGZO晶体管的结构及其优缺点,总结了影响金属氧化物IGZO薄膜晶体管性能的因素,并提出了制作高性能金属氧化物IGZO薄膜晶体管的方法。     

Skin‐Like Oxide Thin‐Film Transistors for Transparent Displays

Flexible transparent display is a promising candidate to visually communicate with each other in the future Internet of Things era. The flexible oxide thin‐film transistors (TFTs) have attracted attention as a component for transparent display by its high performance and high transparency. The critical issue of flexible oxide TFTs for practical display applications, however, is the realization on transparent and flexible substrate without any damage and characteristic degradation. Here, the ultrathin, flexible, and transparent oxide TFTs for skin‐like displays are demonstrated on an ultrathin flexible substrate using an inorganic‐based laser liftoff process. In this way, skin‐like ultrathin oxide TFTs are conformally attached onto various fabrics and human skin surface without any structural damage. Ultrathin flexible transparent oxide TFTs show high optical transparency of 83% and mobility of 40 cm² V^?1 s^?1. The skin‐like oxide TFTs show reliable performance under the electrical/optical stress tests and mechanical bending tests due to advanced device materials and systematic mechanical designs. Moreover, skin‐like oxide logic inverter circuits composed of n‐channel metal oxide semiconductor TFTs on ultrathin, transparent polyethylene terephthalate film have been realized.     

Anodized ITO Thin‐Film Transistors

This paper reports that the electrical, optical and structural properties of ITO film can be significantly modulated by an anodization treatment. An ITO TFT technology based on the anodization approach is then proposed and demonstrated, which results in an ideal homo‐junction device structure with the source/drain/pixel electrodes and channel region made of one single ITO layer. A preliminary device fabrication at room temperature shows the resulting TFT has an on/off current ratio exceeding 1 × 10⁸, a saturation mobility of 29.0 cm² V^?1 s^?1, and a subthreshold swing of 0.20 V per decade. This technology also allows a feasible V_T adjustment and muti‐V_T implementation.     

非晶氧化物半导体薄膜晶体管沟道层的研究进展

薄膜晶体管(TFT)作为开关元件广泛应用于平板显示领域,沟道层材料的选择直接影响了TFT的性能.近年来,基于非晶氧化物半导体(AOS)沟道层材料的TFT已成为具有潜力替代传统硅材料(非晶硅或多晶硅)沟道层TFT的新一代技术,有望应用于超大屏显示、3D显示、柔性显示以及透明显示等新一代显示领域.综述了AOS TFT沟道层的研究进展,重点介绍了AOS TFT用AOS沟道层在材料体系、成膜技术、薄膜的后续处理工艺、材料体系中各元素含量以及掺杂等方面的研究成果,并分析了AOS沟道层对AOS TFT性能的影响以及存在的问题,对AOS TFT的未来发展趋势进行了预测和展望.     

Highly Robust Bendable Oxide Thin‐Film Transistors on Polyimide Substrates via Mesh and Strip Patterning of Device Layers

Advancement in thin‐film transistor (TFT) technologies has extended to applications that can withstand extreme bending or folding. The changes of the performances of amorphous‐indium‐gallium‐zinc‐oxide (a‐IGZO) TFTs on polyimide substrate after application of extreme mechanical bending strain are studied. The TFT designs include mesh and strip patterned source/drain metal lines as well as strip patterned a‐IGZO semiconductor layer. The robustness of the a‐IGZO TFTs with the strain of 2.17% corresponding to the radius of 0.32 mm is tested and no crack generation even after 60 000 bending cycles is found. The split of source/drain electrodes and semiconductor layer can improve the mechanical bending stability of the TFTs. This can be possible by using conventional TFT manufacturing process so that this technology can be easily applied to build robust TFT array for foldable displays.     

Low‐Temperature,Nontoxic Water‐Induced Metal‐Oxide Thin Films and Their Application in Thin‐Film Transistors

Here, a simple, nontoxic, and inexpensive “water‐inducement” technique for the fabrication of oxide thin films at low annealing temperatures is reported. For water‐induced (WI) precursor solution, the solvent is composed of water without additional organic additives and catalysts. The thermogravimetric analysis indicates that the annealing temperature can be lowered by prolonging the annealing time. A systematic study is carried out to reveal the annealing condition dependence on the performance of the thin‐film transistors (TFTs). The WI indium‐zinc oxide (IZO) TFT integrated on SiO₂ dielectric, annealed at 300 °C for 2 h, exhibits a saturation mobility of 3.35 cm² V^?1 s^?1 and an on‐to‐off current ratio of ≈10⁸. Interestingly, through prolonging the annealing time to 4 h, the electrical parameters of IZO TFTs annealed at 230 °C are comparable with the TFTs annealed at 300 °C. Finally, fully WI IZO TFT based on YO_x dielectric is integrated and investigated. This TFT device can be regarded as “green electronics” in a true sense, because no organic‐related additives are used during the whole device fabrication process. The as‐fabricated IZO/YO_x TFT exhibits excellent electron transport characteristics with low operating voltage (≈1.5 V), small subthreshold swing voltage of 65 mV dec^?1 and the mobility in excess of 25 cm² V^?1 s^?1.     

Water‐Induced Scandium Oxide Dielectric for Low‐Operating Voltage n‐ and p‐Type Metal‐Oxide Thin‐Film Transistors

Solution‐processed metal‐oxide thin films based on high dielectric constant (k) materials have been extensively studied for use in low‐cost and high‐performance thin‐film transistors (TFTs). Here, scandium oxide (ScO_x) is fabricated as a TFT dielectric with excellent electrical properties using a novel water‐inducement method. The thin films are annealed at various temperatures and characterized by using X‐ray diffraction, atomic‐force microscopy, X‐ray photoelectron spectroscopy, optical spectroscopy, and a series of electrical measurements. The optimized ScO_x thin film exhibits a low‐leakage current density of 0.2 nA cm^?2 at 2 MV cm^?1, a large areal capacitance of 460 nF cm^?2 at 20 Hz and a permittivity of 12.1. To verify the possible applications of ScO_x thin films as the gate dielectric in complementary metal oxide semiconductor (CMOS) electronics, they were integrated in both n‐type InZnO (IZO) and p‐type CuO TFTs for testing. The water‐induced full oxide IZO/ScO_x TFTs exhibit an excellent performance, including a high electron mobility of 27.7 cm² V^?1 s^?1, a large current ratio (I_on/I_off) of 2.7 × 10⁷ and high stability. Moreover, as far as we know it is the first time that solution‐processed p‐type oxide TFTs based on a high‐k dielectric are achieved. The as‐fabricated p‐type CuO/ScO_x TFTs exhibit a large I_on/I_off of around 10⁵ and a hole mobility of 0.8 cm² V^?1 at an operating voltage of 3 V. To the best of our knowledge, these electrical parameters are among the highest performances for solution‐processed p‐type TFTs, which represents a great step towards the achievement of low‐cost, all‐oxide, and low‐power consumption CMOS logics.     

Printable Organic‐Inorganic Nanoscale Multilayer Gate Dielectrics for Thin‐Film Transistors Enabled by a Polymeric Organic Interlayer

Here, a new approach to the layer‐by‐layer solution‐processed fabrication of organic/inorganic hybrid self‐assembled nanodielectrics (SANDs) is reported and it is demonstrated that these ultrathin gate dielectric films can be printed. The organic SAND component, named P‐PAE, consists of polarizable π‐electron phosphonic acid‐based units bound to a polymeric backbone. Thus, the new polymeric SAND (PSAND) can be fabricated either by spin‐coating or blade‐coating in air, by alternating P‐PAE, a capping reagent layer, and an ultrathin ZrOx layer. The new PSANDs thickness vary from 6 to 15 nm depending on the number of organic‐ZrOx bilayers, exhibit tunable film thickness, well‐defined nanostructures, large electrical capacitance (up to 558 nF cm^?2), and good insulating properties (leakage current densities as low as 10^?6 A cm^?2). Organic thin‐film transistors that are fabricated with representative p‐/n‐type organic molecular/polymeric semiconducting materials, function well at low voltages (<3.0 V). Furthermore, flexible TFTs fabricated with PSAND exhibit excellent mechanical flexibility and good stress stability, offering a promising route to low operating voltage flexible electronics. Finally, printable PSANDs are also demonstrated and afford TFTs with electrical properties comparable to those achieved with the spin‐coated PSAND‐based devices.     

Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

A Review of Low‐Temperature Solution‐Processed Metal Oxide Thin‐Film Transistors for Flexible Electronics

Solution processing, including printing technology, is a promising technique for oxide thin‐film transistor (TFTs) fabrication because it tends to be a cost‐effective process with high composition controllability and high throughput. However, solution‐processed oxide TFTs are limited by low‐performance and stability issues, which require high‐temperature annealing. This high thermal budget in the fabrication process inhibits oxide TFTs from being applied to flexible electronics. There have been numerous attempts to promote the desired electrical characteristics of solution‐processed oxide TFTs at lower fabrication temperatures. Recent techniques for achieving low‐temperature (<350 °C) solution‐processed and printed oxide TFTs, in terms of the materials, processes, and structural engineering methods currently in use are reviewed. Moreover, the core techniques for both n‐type and p‐type oxide‐based channel layers, gate dielectric layers, and electrode layers in oxide TFTs are addressed. Finally, various multifunctional and emerging applications based on low‐temperature solution‐processed oxide TFTs are introduced and future outlooks for this highly promising research are suggested.     

宽带隙ZnMgO的电学特性及其透明薄膜场效应晶体管

首次提出了用六方相晶体结构的宽带隙ZnMgO作为薄膜场效应晶体管（TFT）的沟道层，用立方相ZnMgO纳米晶体薄膜作为栅绝缘层，在实验中用透明的ITO导电玻璃作为衬底，通过连续沉积六方和立方相结构的纳米ZnMgO晶体薄膜，并通过光刻、电极工艺等，研制了透明的ZnO基TFT, TFT的电流开关比达到1E4，场效应迁移率为0.6cm2/(V·s).在偏压2.5MV/cm下漏电流为1E-8A.     

High‐Mobility ZnO Thin Film Transistors Based on Solution‐processed Hafnium Oxide Gate Dielectrics

The properties of metal oxides with high dielectric constant (k) are being extensively studied for use as gate dielectric alternatives to silicon dioxide (SiO₂). Despite their attractive properties, these high‐k dielectrics are usually manufactured using costly vacuum‐based techniques. In that respect, recent research has been focused on the development of alternative deposition methods based on solution‐processable metal oxides. Here, the application of the spray pyrolysis (SP) technique for processing high‐quality hafnium oxide (HfO₂) gate dielectrics and their implementation in thin film transistors employing spray‐coated zinc oxide (ZnO) semiconducting channels are reported. The films are studied by means of admittance spectroscopy, atomic force microscopy, X‐ray diffraction, UV–Visible absorption spectroscopy, FTIR, spectroscopic ellipsometry, and field‐effect measurements. Analyses reveal polycrystalline HfO₂ layers of monoclinic structure that exhibit wide band gap (≈5.7 eV), low roughness (≈0.8 nm), high dielectric constant (k ≈ 18.8), and high breakdown voltage (≈2.7 MV/cm). Thin film transistors based on HfO₂/ZnO stacks exhibit excellent electron transport characteristics with low operating voltages (≈6 V), high on/off current modulation ratio (～10⁷) and electron mobility in excess of 40 cm² V^?1 s^?1.     

Printed Neuromorphic Devices Based on Printed Carbon Nanotube Thin‐Film Transistors

Hardware implementation of artificial synapse/neuron by electronic/ionic hybrid devices is of great interest for brain‐inspired neuromorphic systems. At the same time, printed electronics have received considerable interest in recent years. Here, printed dual‐gate carbon‐nanotube thin‐film transistors with very high saturation field‐effect mobility (≈269 cm² V^?1 s^–1) are proposed for artificial synapse application. Some important synaptic behaviors including paired‐pulse facilitation (PPF), and signal filtering characteristics are successfully emulated in such printed artificial synapses. The PPF index can be modulated by spike width and spike interval of presynaptic impulse voltages. The results present a printable approach to fabricate artificial synaptic devices for neuromorphic systems.     

Ultrathin,Organic, Semiconductor/Polymer Blends by Scanning Corona‐Discharge Coating for High‐Performance Organic Thin‐Film Transistors

A new thin‐film coating process, scanning corona‐discharge coating (SCDC), to fabricate ultrathin tri‐isopropylsilylethynyl pentacene (TIPS‐PEN)/amorphous‐polymer blend layers suitable for high‐performance, bottom‐gate, organic thin‐film transistors (OTFTs) is described. The method is based on utilizing the electrodynamic flow of gas molecules that are corona‐discharged at a sharp metallic tip under a high voltage and subsequently directed towards a bottom electrode. With the static movement of the bottom electrode, on which a blend solution of TIPS‐PEN and an amorphous polymer is deposited, SCDC provides an efficient route to produce uniform blend films with thicknesses of less than one hundred nanometers, in which the TIPS‐PEN and the amorphous polymer are vertically phase‐separated into a bilayered structure with a single‐crystalline nature of the TIPS‐PEN. A bottom‐gate field‐effect transistor with a blend layer of TIPS‐PEN/polystyrene (PS) (90/10 wt%) operated at ambient conditions, for example, indeed exhibits a highly reliable device performance with a field‐effect mobility of approximately 0.23 cm² V^?1 s^?1: two orders of magnitude greater than that of a spin‐coated blend film. SCDC also turns out to be applicable to other amorphous polymers, such as poly(α‐methyl styrene) and poly(methyl methacrylate) and, readily combined with the conventional transfer‐printing technique, gives rise to micropatterned arrays of TIPS‐PEN/polymer films.