Surface passivation of multicrystalline silicon wafers by porous silicon combined with an ultrathin nanoparticles aluminum coating film

In this paper, we demonstrate that we may efficiently improve surface passivation of multi-crystalline silicon (mc-Si) while combining formation of porous silicon (PS) and deposition of ultrathin aluminum (Al) film. Aluminum Nanoparticles were deposited by thermal evaporation onto PS formed on mc-Si wafers. Optoelectronic properties of Al/PS/mc-Si and Al/mc-Si treated samples were investigated before and after annealing in the 400–700 °C temperature range. The surface passivation effectiveness was pointed out based on minority carrier lifetime and photoluminescence measurements. It was found that, at a minority carrier density Δn = 10¹⁵ cm^?3, the effective minority carrier lifetime increases from 1.5 μs (for the bare mc-Si wafer) to about 6 and 14 μs before and after thermal annealing, respectively. FTIR analyses show strong correlation between the minority carrier lifetime values and hydrogen and Al passivation. Major beneficial effect of the co-presence of Al and Al–O on the optoelectronic properties is also demonstrated. The reflectivity of Al/PS treated mc-Si decrease significantly at 500 nm as compared to untreated mc-Si (from 31 % for untreated mc-Si wafers to 8 % for Al/PS treated ones), which is due to the roughly ordered structure and to the Al nanoparticles.     

Application of photoconductivity decay and photocurrent generation methods for determination of minority carrier lifetime in silicon

Minority carrier lifeline, τ, is one of the most important parameters which has a decisive effect on the performance of silicon devices based on excess carriers. The value of τ is greatly affected by the presence of impurities and defects in silicon and its value provides a fair indication of quality of the material. Photoconductivity decay (PCD) and photocurrent generation (PCG) methods are simple and low cost methods of measurement of minority carrier lifetime in silicon wafers. However, their application requires care. The PCD method can give quite misleading results in case of polycrystalline wafers if there exists potential barriers at the grain boundaries which may affect majority carrier mobility significantly. PCG needs creation of an inducedp ₊-p-n ₊ structure of substantially good quality that should not degrade with time. For PCG method the T measurement under vacuum conditions provides correct and consistent results.     

Comparison of surface passivation of crystalline silicon by a-Si:H with and without atomic hydrogen treatment using hot-wire chemical vapor deposition

We compared surface passivation of c-Si by a-Si:H with and without atomic hydrogen treatment prior to a-Si:H deposition. The atomic hydrogen is produced by hot-wire chemical vapor deposition (HWCVD). For this purpose, we deposited a-Si:H layers onto both sides of n-type FZ c-Si wafers and measured the minority carrier effective lifetime and implied V_OC for different H treatment times ranging from 5 s to 30 s prior to a-Si:H deposition. We found that increasing hydrogen treatment times led to lower effective lifetimes and implied V_OC values for the used conditions. The treatments have been performed in a new virgin chamber to exclude Si deposition from the chamber walls. Our results show that a short atomic hydrogen pretreatment is already detrimental for the passivation quality which might be due to the creation of defects in the c-Si. AFM measurements do not show any change in the surface roughness of the different samples.     

硅表面钝化及对异质结太阳电池特性的影响

研究了不同的晶体硅表面钝化方法,测试分析了硅片的少数载流子寿命以及对晶体硅/非晶硅异质结(HIT)太阳电池性能的影响。发现适当时间的HF溶液处理、氢等离子体处理和表面覆盖约3nm的本征非晶硅层能有效提高硅片的少子寿命,从而提高HIT太阳电池的开路电压。对电池制备工艺综合优化后,得到了基于n型晶体硅的光电转换效率为16.75%(Voc=0.596V,Jsc=41.605mA/cm2,FF=0.676,AM1.5,25℃)的HIT太阳电池。     

Fast,high resolution,inline contactless electrical semiconductor characterization for photovoltaic applications by microwave detected photoconductivity

The state-of-the art lifetime measurement technique MDP (microwave detected photoconductivity) is presented with its latest developments in sensitivity, measurement speed and data simulation. Several applications and examples in the field of inline material characterization, defect recognition and real time statistical process control in silicon bricks and wafers are presented, demonstrating the practical use of MDP measurements and of the data obtained by it. The measured lifetime itself combined with its spatial distribution and the measured steady state photoconductivity enable a good correlation to the cell efficiency. Furthermore, the paper presents a detailed summary of the properties of steady state and non-steady state microwave based minority carrier lifetime measurement techniques to complete this extensive study.     

Linearity of Response of Ultrafast Photoconductive Switches: Critical Dependence Upon Ion-implantation and Fabrication Conditions

We have measured the responsivity of photoconductive switches as a function of electrical bias and optical intensity. The switches were fabricated using standard 50 z microstrip transmission line technology on silicon-on-sapphire wafers. Picosecond photoconductive response was produced by self-implanting the silicon to reduce the carrier lifetime. Although all of the switches tested possessed ultrafast response, the linearity of response with electrical bias and optical intensity was dependent on the order of the metallization and ion-implantation processing steps during the fabrication procedure. Switches fabricated using processes reported in the literature to yield switches with linear response (Ohmic contacts) instead yielded switches with nonlinear response (Schottky contacts). Furthermore switches fabricated using processes reported in the literature to yield switches with nonlinear response (Schottky contacts) instead yielded switches with linear response (Ohmic contacts). We discuss the effects of photo-generation-recombination dynamics, carrier transport, charge screening, the build-up of space charge, and switch geometry on the photo-conductive response. Further, we discuss the effects of the observed nonlinear response on the use of ultrafast photoconductive switches to generate and to sample ultrafast electrical waveforms. We also discuss possible applications of both linear and nonlinear switches.     

Formation of subsurface cracks in silicon wafers by grinding

Single-crystal silicon is an important material in the semiconductor and optical industries.However,being hard and brittle,a silicon wafer is vulnerable to subsurface cracks(SSCs)during grinding,which is detrimental to the performance and lifetime of a wafer product.Therefore,studying the formation of SSCs is important for optimizing SSC-removal processes and thus improving surface integrity.In this study,a statistical method is used to study the formation of SSCs induced during grinding of silicon wafers.The statistical results show that grinding-induced SSCs are not stochastic but anisotropic in their distributions.Generally,when grinding with coarse abrasive grains,SSCs form along the cleavage planes,primarily the{111}planes.However,when grinding with finer abrasive grains,SSCs tend to form along planes with a fracture-surface energy higher than that of the cleavage planes.These findings provide a guidance for the accurate detection of SSCs in ground silicon wafers.     

半导体材料少子寿命测试仪的研制开发

少数载流子寿命(简称少子寿命)是半导体材料的一项重要参数，它对半导体器件的性能、太阳能电池的效率都有重要的影响。我们采用微波反射光电导衰减法研制了一台半导体材料少子寿命测试仪，本文将对测试仪的实验装置、测试原理及程序计算进行了较详细的介绍，并与国外同类产品的测试进行比较，结果表明本测试仪测试结果准确、重复性高，适合少子寿命的实验室研究和工业在线测试。     

Correlation between spatially resolved solar cell efficiency and carrier lifetime of multicrystalline silicon

The correlation between the spatially resolved carrier lifetime of multicrystalline silicon and the spatially resolved monochromatic solar cell efficiency is investigated by means of microwave-detected photoconductance decay (MW-PCD) measurements and illuminated lock-in thermography (ILIT). Local monochromatic solar cell efficiencies are determined from ILIT measurements under short-circuit conditions and at the maximum power point of the cell. The resulting efficiency images are compared with efficiency images obtained from MW-PCD lifetime images of unprocessed neighbouring wafers using PC1D simulations. We observe a qualitative correlation between the measured and the simulated efficiency images. Areas with reduced efficiency are found in the same locations using both methods. However, the dynamic range in the monochromatic efficiency is larger for the images obtained from ILIT measurements. Possible explanations for this difference are a change in carrier lifetime during cell processing and varying lifetimes on microscopic scales, leading to averaging faults in the lifetime images.     

Effect of transparency within a semiconductor on emissivity mapping for thermal profile measurements of a semiconductor device

The paper reports on infra-red (IR) measurements made on silicon and gallium arsenide substrates which are transparent to IR radiation. The work showed that the measured emissivity is dependent on the wafer back-face technology, for example, a gold heat-sink or epoxy attachment. The work also indicated that the measured emissivity for the thermal mapping of a device is a function of the emitted radiation from the front, back face and layer interfaces, as well as internally reflected radiation and will be dependent on the thickness of the semiconductor wafer. Experimental work has shown that the two-temperature emissivity correction method will give a very accurate value of the total surface emissivity received from the sample     

The optical properties of porous silicon produced by metal-assisted anodic etching

Porous silicon (PS) was obtained from n-type (100) mono-crystalline silicon wafers with different metal using two different illumination conditions. The visible photoluminescence (PL) may come from defect-related radiative centers on PS surface and adsorbed hydrogen atoms may be associated to the elimination of irradiative centers on PS surface, which can be proved by the infrared absorption spectra. The metal can be used as catalytic role to increase the etching rate under back illumination, but under front illumination, the metal can cancel light-generated carrier leading to the decrease of etching rate during anodic etching. Furthermore, the change of minority carrier lifetime is opposite to the change of PL efficiency of PS, which can be Confirmed by the results of μ-PCD measurements.     

Large-area nanoimprinting on various substrates by reconfigurable maskless laser direct writing

Laser-assisted, one-step direct nanoimprinting of metal and semiconductor nanoparticles (NPs) was investigated to fabricate submicron structures including mesh, line, nanopillar and nanowire arrays. Master molds were fabricated with high-speed (200?mm?s(-1)) laser direct writing (LDW) of negative or positive photoresists on Si wafers. The fabrication was completely free of lift-off or reactive ion etching processes. Polydimethylsiloxane (PDMS) stamps fabricated from master molds replicated nanoscale structures (down to 200?nm) with no or negligible residual layers on various substrates. The low temperature and pressure used for nanoimprinting enabled direct nanofabrication on flexible substrates. With the aid of high-speed LDW, wafer scale 4?inch direct nanoimprinting was demonstrated.     

A run-to-run controller for product surface quality improvement

In semiconductor manufacturing, the surface quality of silicon wafers has a significant impact on the subsequent processes that produce devices using the wafers as a component. The surface quality of a wafer is characterised by a two-dimensional (2-D) data structure: the geometric requirement for the wafer surface is smooth and flat and the thickness should fall within certain specification limits. Therefore, both low deviation and high uniformity are desirable for control over the wafer quality. In this work, we develop a run-to-run control algorithm for improving wafer quality. Considering the unique 2-D data structure, we first construct a model that encompasses the spatial correlation of the observations on the wafer surface to link the wafer quality with the process variables, and subsequently develop a recursive algorithm to generate optimal set points for the controllable factors. More specifically, a Gaussian-Kriging model is used to characterise the spatial dependence of the thickness measures of the wafer and a recursive least square method is employed to update the estimates of the model parameters. The performance of the new controller is studied via simulation and compared with existing controllers, which demonstrates that the newly proposed controller can effectively reduce the surface variations of the silicon wafers.     

Non-destructive determination of step coverage on semiconductor wafers

As the dimensions of semiconductor devices are reduced, the resistance of conductor lines becomes a critical property in determining the minimum linewidth allowed. Often these conductor lines must traverse substantial topography from prior processing, becoming thinner at the corners or along vertical walls. This creates high resistance or hot spots, which affect the power loss, timing and lifetime of the device. Although considerable emphasis is being placed on planarization techniques such as chemical mechanical polishing, which eliminate hot spots, there are still many processes using little or no planarization. Traditionally wafers are cross-sectioned and viewed by scanning electron microscopy to verify step coverage, or special test structures are patterned and their resistance checked at a later step in the processing. A method of determining relative step coverage changes would be advantageous for process control or identifying the effects of process changes. Data will be presented supporting the use of the mutual inductance test method to measure and map the resistance of conductor films on product wafers immediately after metal deposition. This method allows for rapid detection of process problems, as well as reducing or eliminating the need for separate monitor wafers. Step coverage over the entire wafer can be evaluated quickly and easily during process or equipment characterization, identifying the conditions which give optimum step coverage.     

High‐Temperature Ionic Epitaxy of Halide Perovskite Thin Film and the Hidden Carrier Dynamics

High‐temperature vapor phase epitaxy (VPE) has been proved ubiquitously powerful in enabling high‐performance electro‐optic devices in III–V semiconductor field. A typical example is the successful growth of p‐type GaN by VPE for blue light‐emitting diodes. VPE excels as it controls film defects such as point/interface defects and grain boundary, thanks to its high‐temperature processing condition and controllable deposition rate. For the first time, single‐crystalline high‐temperature VPE halide perovskite thin film has been demonstrated—a unique platform on unveiling previously uncovered carrier dynamics in inorganic halide perovskites. Toward wafer‐scale epitaxial and grain boundary‐free film is grown with alkali halides as substrates. It is shown the metal alkali halides could be used as universal substrates for VPE growth of perovskite due to their similar material chemistry and lattice constant. With VPE, hot photoluminescence and nanosecond photo‐Dember effect are revealed in inorganic halide perovskite. These two phenomena suggest that inorganic halide perovskite could be as compelling as its organic–inorganic counterpart regarding optoelectronic properties and help explain the long carrier lifetime in halide perovskite. The findings suggest a new avenue on developing high‐quality large‐scale single‐crystalline halide perovskite films requiring precise control of defects and morphology.     

Surface blistering of low temperature annealed hydrogen and helium co-implanted germanium and its application to splitting of bonded wafer substrates

Applications involving transfer of germanium layers to silicon-based substrates often require a process involving a restricted thermal budget. The use of relatively low temperatures has a major advantage in reducing stresses when thermal splitting of implanted germanium wafers bonded to silicon-based substrates is used to create germanium-on-oxide (GeOI) layers. The present study investigates the phenomenon of blistering of hydrogen and helium co-implanted germanium over the temperature range 250–400 °C, optical microscopy being used to detect the initial appearance of the blisters. Results showed that plots of Ln(time) vs. blister initiation temperature consisted of several straight-line regions yielding an activation energy for each region. The plots showed similarities to those observed in previous work with silicon co-implanted and annealed under similar conditions. At temperatures below the blister initiation temperature, transmission electron microscopy (TEM), revealed the presence of spherical bubbles at a depth below the surface estimated to be approximately that of the hydrogen implant projected range. GeOI layers were produced by thermal splitting of co-implanted germanium wafers bonded to oxide-coated silicon substrates wafers at a temperature of 300 °C. The RMS roughness of the split germanium surface measured by atomic force microscopy (AFM) was about 11 nm averaged over the wafer surface. In addition there were isolated and randomly distributed regions of 27 nm roughness covering about 20% of the total surface area of the wafer.     

Efficient n-GaAs photoelectrodes grown by close-spaced vapor transport from a solid source

n-GaAs films were grown epitaxially on n(+)-GaAs substrates by a close-spaced vapor transport method and their photoelectrochemical energy conversion properties studied. Under 100 mW cm(-2) of ELH solar simulation, conversion efficiencies up to 9.3% for CSVT n-GaAs photoanodes were measured in an unoptimized ferrocene/ferrocenium test cell. This value was significantly higher than the 5.7% measured for similarly doped commercial n-GaAs wafers. Spectral response experiments showed that the higher performance of CSVT n-GaAs films relative to the commercial wafers was due to longer minority carrier diffusion lengths (L(D)), up to 1,020 nm in the CSVT films compared to 260 nm in the commercial n-GaAs wafers. Routes to improve the performance of CSVT GaAs and the implications of these results for the development of scalable GaAs-based solar energy conversion devices are discussed.     

Porous silicon and aluminum co-gettering experiment in p-type multicrystalline silicon substrate

The lifetimes of non-equilibrium minority carriers, which bound with the diffusion length, are considered as two important parameters of the low-quality multicrystalline silicon (mc-Si) substrate. Its value defines the quality of the initial substrate. It is also subjected to change as a result of many high-temperature operations during the device fabrication. Therefore, it is necessary to incorporate certain processing steps that either improve or preserve the electronic quality of the mc-Si substrate. In this study, a novel porous silicon and aluminum co-gettering experiment has been applied as a beneficial approach to improve the electronic quality of the low-resistivity mc-Si substrates. Porous silicon layers were prepared by anodization of the n⁺ silicon region by a simple electrochemical etching process using an aqueous HF-based electrolyte, which leads to the creation of porous silicon microcavities. Besides making porous silicon and aluminum co-gettered samples, both phosphorous and aluminum alloy-gettered samples and reference samples were made. The gettering-induced lifetime enhancement in the test samples was monitored by measuring the lifetime/diffusion length of the test samples using two independent methods such as photoconductivity decay (PCD) measurement and the photocurrent generation method (PCM), respectively. The result in both the measurements has shown a reasonably good agreement with each other. Therefore, it is inferred that the applied co-gettering experiment has a synergetic effect to improve the lifetime of the mc-Si substrate.     

Porous silicon and aluminum co-gettering experiment in p-type multicrystalline silicon substrate

The lifetimes of non-equilibrium minority carriers, which bound with the diffusion length, are considered as two important parameters of the low-quality multicrystalline silicon (mc-Si) substrate. Its value defines the quality of the initial substrate. It is also subjected to change as a result of many high-temperature operations during the device fabrication. Therefore, it is necessary to incorporate certain processing steps that either improve or preserve the electronic quality of the mc-Si substrate. In this study, a novel porous silicon and aluminum co-gettering experiment has been applied as a beneficial approach to improve the electronic quality of the low-resistivity mc-Si substrates. Porous silicon layers were prepared by anodization of the n⁺ silicon region by a simple electrochemical etching process using an aqueous HF-based electrolyte, which leads to the creation of porous silicon microcavities. Besides making porous silicon and aluminum co-gettered samples, both phosphorous and aluminum alloy-gettered samples and reference samples were made. The gettering-induced lifetime enhancement in the test samples was monitored by measuring the lifetime/diffusion length of the test samples using two independent methods such as photoconductivity decay (PCD) measurement and the photocurrent generation method (PCM), respectively. The result in both the measurements has shown a reasonably good agreement with each other. Therefore, it is inferred that the applied co-gettering experiment has a synergetic effect to improve the lifetime of the mc-Si substrate.     

Accuracy Improvement of Multi-parameter Estimation in Combined Photocarrier Radiometry and Free Carrier Absorption for Characterization of Silicon Wafers

Numerical simulations are performed to investigate the effect of experimental parameters on the simultaneous determination of the electronic transport properties (namely, the carrier lifetime, the carrier diffusion coefficient, and the surface recombination velocities) of semiconductor wafers in the combined photocarrier radiometry (PCR) and free carrier absorption (FCA) technique via a multi-parameter estimation procedure. The uncertainties of the fitted parameter values are analyzed by investigating the dependence of a mean square variance including both amplitude and phase errors on the corresponding transport parameters. Simulation results show that the optimal experimental conditions with a combination of an appropriate pump?Cprobe-beam separation and a small (comparable to or slightly larger than the pump beam radius) detection radius in FCA, as well as a large (1?mm) detection radius in PCR, can noticeably reduce the uncertainties of the simultaneously fitted transport properties of wafers.