A 5 Gb/s multi-mode transmitter with de-emphasis for PCI Express 2.0/USB 3.0

A versatile transmitter compatible SERDES system was fabricated in 55 nm CMOS technology. The proposed transmitter comprises a low-power and low-area driver with de-emphasis and a 10:1 serializer, meanwhile it supports power management to reduce the unnecessary dissipation and to complete the mode transition among four power modes. Furthermore, the transmitter is compatible with PCI Express 2.0/1.0 and also meets the USB 3.0 standard. The experimental results show this test chip passes PCI Express 2.0/1.0 TX compliance test and USB 3.0 TX compliance test. The chip occupies 0.033 mm² and consumes 33 mA at 5 Gb/s.     

A 10 Gb/s 0.25 μm SiGe modulator driver for photonic-integration

A 10 Gb/s modulator driver in SiGe 0.25 μm BiCMOS technology with a chip area of only 0.54 mm² is presented. The intentions of designing this modulator driver are to amplify small incoming data signals at 10 Gb/s and to integrate the driver together with a silicon optical phase modulator (Mach–Zehnder modulator in push–pull configuration) on the same chip. The driver is designed to have a low power-consumption of 0.68 W but a high gain (S₂₁ = 37 dB). It consists of a differential pre-amplifier with common-mode feedback and automatic gain control, which is supplied by 2.5 V. The differential output stage is supplied with 3.5 V. The driver is designed to drive a Mach–Zehnder modulator, which uses in his arms carrier depletion in a reverse biased pn junction to adjust the refractive index. The differential output (5V_pp) delivers two times a voltage between 0 and 2.5 V. Therefore no bias-T is needed at the output to assure that the diodes of the interferometer arms are in the reverse biased mode. In addition to the low-power design, a passive network instead of an additional amplifier circuit for driving the cascode transistors, which reduce the collector–emitter voltage of each transistor in the output stage below breakdown, is presented. According to bit-error-ratio (BER) measurements with a pseudo-random-bit-sequence with the length of 2³¹ ? 1 the BER is better than 10^?12 for input voltage differences down to 50 mV_pp. The rise/fall time (20–80 %) is 45/30 ps respectively.     

Design, implementation and measurement of a 120 GHz 10 Gb/s phase-modulating transmitter in 65 nm LP CMOS

A novel mm-wave phase modulating transmit architecture, capable of achieving data rates as high as 10 Gb/s is presented at 120 GHz. The circuit operates at a frequency of 120 GHz. The modulator consists of a differential branchline coupler and a high speed 4-to-1 analog multiplexer with direct digital input. Both a QPSK as well as a 8QAM constellation are supported. To achieve high output power, a 9-stage power amplifier is designed and connected to the multiplexer output. The complete chip is integrated in a 65 nm low power CMOS technology. Capacitive neutralization is used to achieve high gain and good stability for the MOS devices. Also, various differential transmission line topologies are investigated to achieve high performance in terms of loss and area consumption.     

A 1.8 V low power 5 Gbps PMOS-based LVDS output driver with good return loss performance

This paper presents a novel design topology of a 5 Gbps PMOS-based low voltage differential signaling (LVDS) voltage mode output driver. The topology is designed to meet the requirements of low power consumption and high data rates applications. The driver consists of an output stage and a pre-driver stage where the driver’s swing and common-mode output voltage are set. The pre-driver and the output stage consume only 13.1 mW of power at 5 Gbps speed while operating from a 1.8 V voltage supply. Further, the design achieved ?21 dB return loss performance at DC. The driver was extracted and simulated using Mentor Graphics CAD tools and implemented in 180 nm CMOS technology. The output signal is fully compliant with the LVDS standard output swing and common-mode voltage specifications.     

A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications

This paper presents the design and Silicon verification of a 2.488–11.2 Gbps multi-standard SerDes transceiver in a 40 nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. A system modeling approach is described, which is used for optimizing the architectural trade-offs. The transceiver makes use of a low-jitter LC phase locked loop to enable high-reliability system design. The design has 420 fs RJ_rms and consumes 30.1 mW/Gbps at 11.2 Gbps.     

A 10 b 120 MS/s 108 mW 0.18 μm CMOS ADC with a PVT-insensitive current reference

This paper proposes a 10 b 120 MS/s CMOS ADC with a PVT-insensitive current reference. The designed current reference shows a mean temperature drift of 35.2 ppm/°C in the temperature range from −25 to 100°C and a supply rejection of 1.1%/V between 1.6 and 2.0 V. The prototype ADC fabricated in a 0.18 μm 1P6M CMOS technology demonstrates a measured DNL and INL of 0.18LSB and 0.53LSB with a maximum SNDR and SFDR of 53 and 68 dB at 120 MS/s. The ADC with an active chip area of 1.8 mm² consumes 108 mW at 120 MS/s and 1.8 V while the proposed on-chip current reference consumes 0.35 mW with a die area of 0.02 mm².     

A Canonical Voltage-Controlled VM-APS with a Grounded Capacitor

A new canonical first order voltage-mode all-pass section (VM-APS) employing a single grounded capacitor as the only passive element and two differential voltage current conveyors as the active elements is proposed. The circuit, with its attractive features of resistorless realization, voltage-controlled pole frequency and low impedance voltage output is a novel and unique offering to the field and an addition to the rich literature on the subject. PSPICE simulations are carried out in 0.5 μ CMOS technology to validate the utility of the proposed circuit.     

轻松升级Gb/s以太网

本文对Ｇｂ／ｓ以太网的技术背景、与ＡＴＭ技术的比较、应用方式等内容作介绍，同时介绍目前市场中的主要Ｇｂ／ｓ以太网解决方案。     

A high-speed rail-to-rail output buffer with push–pull dual-path and dynamic-bias for LCD driver ICs

The design of a low-power high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time; the proposed output buffer thus has a push–pull dual-path function for high-speed operation. Since a conventional class-AB output stage requires two bias voltages, the proposed output buffer provides two dynamic bias voltages to increase the transient response of the class-AB output stage. The two dynamic biases use only two transistors and do not increase the quiescent current. The proposed output buffer is implemented on standard 0.35 μm CMOS 2-poly 4-metal process technology and simulated using HSPICE. The power consumption is 23.1 μW, with settling times of 0.7 and 0.68 μs for rising and falling edges, respectively, under a 1000 pF load. The active area of the output buffer amplifier is only 48 × 48 μm².     

A small area 8 bits 50 MHz CMOS DAC for Bluetooth transmitter

This paper presents a small-area CMOS current-steering segmented digital-to-analog converter (DAC) design intended for RF transmitters in 2.45 GHz Bluetooth applications. The current-source design strategy is based on an iterative scheme whose variables are adjusted in a simple way, minimizing the area and the power consumption, and meeting the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy to attain a small-area current-steering DAC are included. The DAC was designed and implemented in 0.35 μm CMOS technology, requiring an active area of just 200 μm × 200 μm. Experimental results, with a full-scale output current of 700 μA and a 3.3 V power supply, showed a spurious-free dynamic range of 58 dB for a 1 MHz output sine wave and sampling frequency of 50 MHz, with differential and integral nonlinearity of 0.3 and 0.37 LSB, respectively.     

250Gb/s路由器研制成功

光纤通信网络中的光电交换节点成了现今高速率传输的“瓶颈”地段。美国普林斯顿大学最近的研制成功了一种称之为“全光分组交换法”的路由器，速率高达250Gb／S。经测试表明，这种分组交换的比特误码率优于10－‘。这种路由器的研制成功，解决了当前高速率传输交换系统的难题。250Gb/s路由器研制成功     

10Gb/s OEIC光接收机前端及3.125Gb/s限幅放大器

摘要：基于南京电子器件研究所Φ76mm GaAs pHEMT工艺,研制了10Gb/s OEIC光接收机前端,并首次采用耗尽型PHEMT设计并实现了限幅放大器。借助模拟软件ATLAS建立并优化了器件模型,组成形式为MSM光探测器和电流模跨阻放大器,探测器带宽超过10GHz,电容约3fF/μm,光敏面积50×50μm2,整个芯片面积1511μm×666μm。限幅放大器采用无源电感扩展带宽,并借助三维电磁仿真软件HFSS进行模拟仿真。限幅放大器芯片面积1950μm×1910μm,在3.125Gb/s传输速率下,分别输入10mVpp和500mVpp,可以得到500mVpp恒定输出摆幅。     

A CMOS 3.2?Gb/s serial link transceiver, using a new PWAM scheme

In this article, a 3.2?Gb/s serial link transceiver, that can be implemented in 0.35???m CMOS technology is presented. In this transceiver a new multi-level pulse-width-amplitude modulation technique is used. The symbol rate is reduced, while the minimum pulse width (PW) is increased considerably, using the proposed modulation. The PW is larger than the conventional NRZ data format, with PW of Tb, so the ISI will be improved. The multiphase output of a three stage ring oscillator VCO in the PLL is used to modulate and to demodulate the signal. A new charge pump circuit is also introduced to decrease the mismatch between up and down paths. The peak to peak jitter of recovered clock is 21?ps at 800?MHz. The recovered data has the peak to peak jitter of 51?ps. The transmitter and receiver power consumption is 220 and 35?mW, respectively.     

System simulations of a 1.5 V SiGe 81–86 GHz E-band transmitter

This paper presents simulation results for a sliding-IF SiGe E-band transmitter circuit for the 81–86 GHz E-band. The circuit was designed in a SiGe process with f _T  = 200 GHz and uses a supply of 1.5 V. The low supply voltage eliminates the need for a dedicated transmitter voltage regulator. The carrier generation is based on a 28 GHz quadrature voltage oscillator (QVCO). Upconversion to 84 GHz is performed by first mixing with the QVCO signals, converting the signal from baseband to 28 GHz, and then mixing it with the 56 GHz QVCO second harmonic, present at the emitter nodes of the QVCO core devices. The second mixer is connected to a three-stage power amplifier utilizing capacitive cross-coupling to increase the gain, providing a saturated output power of +14 dBm with a 1 dB output compression point of +11 dBm. E-band radio links using higher order modulation, e.g. 64 QAM, are sensitive to I/Q phase errors. The presented design is based on a 28 GHz QVCO, the lower frequency reducing the phase error due to mismatch in active and passive devices. The I/Q mismatch can be further reduced by adjusting varactors connected to each QVCO output. The analog performance of the transmitter is based on ADS Momentum models of all inductors and transformers, and layout parasitic extracted views of the active parts. For the simulations with a 16 QAM modulated baseband input signal, however, the Momentum models were replaced with lumped equivalent models to ease simulator convergence. Constellation diagrams and error vector magnitude (EVM) were calculated in MATLAB using data from transient simulations. The EVM dependency on QVCO phase noise, I/Q imbalance and PA compression has been analyzed. For an average output power of 7.5 dBm, the design achieves 7.2% EVM for a 16 QAM signal with 1 GHz bandwidth. The current consumption of the transmitter, including the PA, equals 131 mA from a 1.5 V supply.     

2.5 Gb/s 16∶1 MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for Optical fiber communication based on TSMC 0.25 μm CMOS technology is represented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is (1.8) mm~(2).     

基于10 Gb/s传输链路的40 Gb/s光传输实验研究

基于中国自然科学基金网(NSFCNet)的400 km×10 Gb/s光传输链路实现了40 Gb/s光传输,没有出现误码率(BER)平台,说明在常规的中短距离10 Gb/s系统可以直接升级至40 Gb/s系统,而不需要升级传输链路。但是,由于相对10 Gb/s系统而言40 Gb/s系统的色散容限非常小,在升级时必须精确补偿原有链路的色散,在接收机前一般需要加可调色散补偿单元。同时,还分析了光纤注入功率对系统性能的影响,结果表明在设计这种由10 Gb/s向40 Gb/s升级的系统时,不仅要考虑信号带宽增加带来信噪比要求的提高,而且必须充分考虑光纤非线性的影响。     

新高带宽40Gb/s以及20Gb/s并行光纤收发器

安华高科技推出两款符合QSFPMSA的高性能光纤收发器产品,适合短距离并行多线式数据通信和互连应用。Avago的新4通道AFBR-79Q4Z和AFBR-79Q5Z收发器分别可以达到每通道10Gb／s和5Gb／s的速度,主要目标为标准850am波长的多模光纤系统设计。Avago是为通信、工业和消费类等应用领域提供模拟接口零组件的领导厂商。     

新高带宽40Gb/s以及20Gb/s并行光纤收发器

安华高科技推出两款符合QSFP MSA的高性能光纤收发器产品,适合短距离并行多线式数据通信和互连应用。Avago的新4通道AFBR-79Q4Z和AFBR-79Q5Z收发器分别可以达到每通道10 Gb/s和5 Gb/s的速度,主要目标为标准850 nm波长的多模光纤系统设计。Avago是为通信、工业和消费类等应用领域提供模拟接口零组件的领导厂商。     

2.5Gb/s限幅放大器设计

文章采用TSMC 0．35μmSiGe工艺实现了数据率达到2．5Gh／s的光纤通道限幅放大器。限幅放大器信号通道利用多级放大方式，降低了输出信号上升／下降时间，减小了级间驱动能力不匹配对信号完整性的影响：通过负反馈环路消除了信号通道上的偏移电压，采用独特的迟滞技术，使检测电路的迟滞对外接电阻变化不敏感。仿真结果证明设计方法是有效的。     

10Gb/s自适应均衡器设计

提出了一种改进型的自适应均衡器结构,通过在自适应环路中引入频谱均衡技术,分离出随机性二进制数据中的高频与低频分量,并将二者之间的平均功率进行比较,产生表征信道衰减程度的电压信号,据此调整高频增益的大小.本次设计采用SMIC 0.13μm标准CMOS工艺,在1.2V电源电压下,能够对长度达80cm的FR4基板传输线进行有效的补偿,从而完成对10Gb/s随机性二进制数据的最优均衡.