A <Emphasis Type="Italic">G</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript><Emphasis Type="Italic">-C</Emphasis> continuous-time analog filter for IEEE 802.11 a/b/g/n wireless LANs

A CMOS transconductor for multi-mode wireless channel selection filter is presented. The linear transconductor is designed based on the flipped-voltage follower (FVF) circuit and an active resistor to achieve the transconductance tuning. The transconductance tuning can be obtained by changing the bias current of the active resistor. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18-μm CMOS process. The results show that the filter can operate with the cutoff frequency of 10–20 MHz. The tuning range would be suitable for the specifications of IEEE 802.11 a/b/g/n Wireless LANs under the consideration of saving chip areas. In the design, the maximum power consumption is 13 mW with the cutoff frequency of 20 MHz under a 1.8 V supply voltage.     

Multimode $G_{m}$– $C$ Channel Selection Filter for Mobile Applications in 1-V Supply Voltage

A CMOS transconductor for multimode channel selection filter is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier which operates in the weak inversion region provides a wide transconductance tuning range without degrading the linearity. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18 mum CMOS process. The measurement results show that the filter can operate with the cutoff frequency of 135 kHz to 2.2 MHz. The tuning range and the linearity performance would be suitable for the wireless specifications of GSM, Bluetooth, cdma2000, and wide-band CDMA. In the design, the maximum power consumption at the highest cutoff frequency is 2 mW under a 1-V supply voltage.     

一种面向多标准无线收发器的低功耗宽调谐范围基带滤波器设计

本论文提出了一种面向多标准收发器的具有精确片上调谐电路的低功耗宽调谐范围基带滤波器。设计的滤波器是由三级Active-Gm-RC类型的双二次单元级联组成的六阶巴特沃斯低通滤波器。采用改进的线性化技术来提高低通滤波器的线性度。论文提出了一种新的匹配性能与工艺无关的跨导匹配电路和具有频率补偿的频率调谐电路来增加滤波器的频率响应精度。为了验证设计方法的有效性,采用标准的130nm CMOS工艺对滤波器电路进行流片。测试结果表明设计的低通滤波器带宽调谐范围为0.1MHz-25MHz,频率调谐误差小于2.68%。滤波器在1.2V的电源电压下,功耗为0.52mA到5.25mA,同时取得26.3dBm的带内输入三阶交调点。     

A Gm-C continuous-time anti-alias filter for UWB analog front-end

A proposed constant drain-source transconductor topology is designed to keep linearity at high frequency. By using the proposed operational transconductance amplifier as a building block, a fourth-order low-pass filter is realized. The filter was fabricated in 0.18 μm CMOS technology and feathers a 250 MHz cutoff frequency. The measured IM3 performance is ?36 dB at 0.6 V_pp input swing and the power consumption is 22 mW.     

A 2-μm CMOS fifth-order low-pass continuous-time filter forvideo-frequency applications

A fifth-order elliptic low-pass continuous-time filter based on triode transconductors for applications in the video frequency range is presented. Fabricated in a standard 2-μm CMOS technology, the circuit occupies 6 mm² of silicon area including the automatic tuning circuitry. The filter achieves a 7-MHz cutoff frequency using a parasitic pole compensation scheme. The dynamic range is 40 dB and power consumption is 30 mW for a 5-V supply. A transconductor biasing strategy which allows a continuous tuning range for the cutoff frequency of one decade is presented     

Sub 1-V highly-linear low-power class-AB bulk-driven tunable CMOS transconductor

This paper describes the design and realization of a sub 1-V low power class-AB bulk-driven tunable linear transconductor using a 0.18-μm CMOS technology. The proposed transconductor employs a class-AB bulk-driven differential input voltage follower and a passive resistor to achieve highly linear voltage-to-current conversion. Transconductance tuning is achieved by tuning the differential output current of the core transconductor with gain-adjustable current mirrors. With 10.4-μA current consumption from a 0.8-V single power supply voltage, simulation results show that the proposed transconductor achieves the total harmonic distortion (THD) of <?40 dB for a peak differential input voltage range of 800 mV at frequencies up to 10 kHz. The simulated input-referred noise voltage integrated over 10-kHz bandwidth is 100 μV, resulting to an input signal dynamic range of 75 dB for THD <?40 dB. A biquadratic G_m-C filter is designed to demonstrated the performance of the proposed transconductor. At the nominal 10-kHz cut-off frequency, the filter dissipates 34.4 μW from a 0.8-V supply voltage and it achieves an input signal dynamic range of 67.4 dB for the third-order intermodulation distortion of <?40 dB.     

A new design of a linear local-feedback MOS transconductor for low frequency applications

For medical devices, low frequency and low power applications are required, and a transconductor which has a low transconductance is needed. A conventional current division scheme for the low transconductance wastes operating current. This paper proposes an improved local-feedback MOS transconductor operating in subthreshold region. The proposed transconductor is optimally designed using maximally flat approximation method, Newton-Raphson method, and Downhill simplex method. From the optimization, two optimum values are obtained. Characteristics of the proposed transconductor are confirmed by simulation. Transfer characteristics of the proposed transconductor are linear, and the power consumption of the proposed transconductor is 1/60 as compared with the presented transconductor using current division scheme. The CMRR is around 70 dB, and the THD is lower than ?55 dB under a condition of that the frequency of the sinusoidal input is 100 Hz. As a demonstration of an application, the proposed transconductor is applied to a low frequency second order Butterworth filter. A cutoff frequency of the filter is 100 Hz. Simulation results show validities and availability of the proposed transconductor.     

A Wide Tuning Range Gm –C Continuous-Time Analog Filter

A CMOS operational transconductance amplifier (OTA) for low-power and wide tuning range filter application is proposed in this paper. The OTA can work from the weak inversion region to the strong inversion region to maximize the transconductance tuning range. The transconductance can be tuned by changing its bias current. A fifth-order Elliptic low-pass filter implemented with the OTAs was integrated by TSMC 0.18-mum CMOS process. The filter can operate with the cutoff frequency of 250 Hz to 1 MHz. The wide tuning range filter would be suitable for multi-mode applications, especially under the consideration of saving chip areas. The third-order inter-modulation (IM3) of -40 dB was measured over the tuning range with two tone input signals. The power consumption is 0.8 mW at 1-MHz cutoff frequency and 1.8-V supply voltage with the active area less than 0.3 mm²     

An active device based wide tuning range CMOS transconductor

A CMOS transconductor for wide tuning range filter application is presented. The linear transconductor is designed based on the flipped-voltage follower (FVF) circuit and can work in the weak, moderate, and strong inversion regions to maximize the transconductance tuning range. The transconductance tuning can be achieved by changing the bias current of the active resistor, and a ratio of 28 is obtained. The transconductor was evaluated by using TSMC 0.18 μm CMOS process, and the total harmonic distortion (THD) of −56 dB can be obtained by giving a 12 MHz 0.4 Vpp input swing signal. In the design, the maximum power consumption is 2 mW with the transconductance of 1.1 mS under a 1.8 V supply voltage.     

Wide tuning-range CMOS VCO based on a tunable active inductor

In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is –85 dBc/Hz at a 1 MHz frequency offset. The output power is from –3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance.     

A 12-mW 264-MHz high linearity sharp roll-off CMOS opamp-RC low-pass filter for MB-OFDM UWB systems

This paper presents a high linearity wideband sharp roll-off Opamp-RC low-pass filter (LPF) for Ultra wideband (UWB) applications. The proposed LPF is composed of three biquads’ transfer functions with different Q-factors in series. Sharp roll-off is attributed to the steep slope of the peaking of a biquad transfer function with a high Q-factor. The superposition of these biquads also helps extend the bandwidth of the overall LPF transfer function without the cost of extra power dissipation. The effects of biquad arrangements on noise and linearity performances are investigated. A simple operational amplifier (op-amp) is adopted to ensure high frequency characteristics and high linearity performance for the designed filter. The LPF is implemented in 0.13-μm IBM CMOS process from 1.5 V supply. The measured cutoff frequency is 264 MHz with the pass-band ripple of less than 1 dB. Digital frequency tuning is implemented with 40% of tuning range around the cutoff frequency. The amount of out-of-band rejection at 290 MHz and at twice cutoff frequency is 12 dB and about 50 dB, respectively. Good linearity with IIP3 of 23 dBm is obtained. The 6th-order LPF dissipates only 12 mW with the active chip size of 400 × 640 μm².     

A 0.5 V LC-VCO with improved varactor tuning technique for WSN

A 0.5 V LC-VCO implemented in 0.18 μm CMOS technology for wireless sensor network is described in this paper. An improved varactor tuning technique is proposed to decrease low frequency noise up-conversion and AM–FM phase noise of VCO, also it can increase Q of LC tank and reduce power consumption of VCO. For coarse tuning of VCO, it can increase the varactor control voltage variation range. For fine tuning of VCO, it can reduce the varactor nonlinearity. The measured tuning range is 4.58–5.26 GHz and power consumption is 2.2 mW. The measured phase noise is ?114 dBc/Hz at 1 MHz frequency offset from a 4.8 GHz carrier.     

A low-power low-voltage OTA-C sinusoidal oscillator with a large tuning range

A new operational transconductance amplifier and capacitor based sinusoidal voltage controlled oscillator is presented. The transconductor uses two cross-coupled class-AB pseudo-differential pairs biased by a flipped voltage follower, and it exhibits a wide transconductance range with low power consumption and high linearity. The oscillator has been fabricated in a standard 0.8-/spl mu/m CMOS process. Experimental results show a frequency tuning range from 1 to 25 MHz. The amplitude is controlled by the transconductor nonlinear characteristic. The circuit is operated at 2-V supply voltage with only 1.58 mW of maximum quiescent power consumption.     

0.5 V CMOS inverter-based tunable transconductor

A new technique for CMOS inverter-based tunable transconductors is proposed in this paper. The proposed technique employs the master–slave approach and offers large transconductance tuning range using a control current. The transconductor was designed using triple-well 0.13 μm CMOS process under the ultra low supply voltage of 0.5 V. The circuit features 37 dB open loop gain, CMRR = 31 dB at each output node, PSRR = 90 dB and GBW = 530 MHz for 120 μA current consumption.     

A 2.4 GHz 6.6 mA fully differential CMOS PLL frequency synthesiser

A 2.4 GHz 6.6 mA fully differential CMOS phase-locked loop (PLL) frequency synthesiser with an on-chip capacitance-calibrated loop filter is presented. The frequency synthesiser includes a differential-tuning voltage-control oscillator (VCO) and a fully differential charge-pump (CP) to reject the common-mode noise. A combination of analogue tuning and digital tuning techniques (4-bit binary weighted capacitor array) is utilised to extend the tuning range of the VCO. A novel topology and an optimisation strategy are utilised to reduce the power consumption of the frequency divider. The capacitance in the loop filter is on-chip calibrated so that the loop dynamic characteristics are accurately controlled despite the process variation. The frequency synthesiser has been implemented in UMC 0.18 μm CMOS. The measured results show that the VCO achieves a 29% tuning range, from 2.056 to 2.758 GHz. The phase noise of the frequency synthesiser is ? 117.2 dBc/Hz at 1 MHz frequency offset from the 2.3 GHz carrier. The settling time is less than 50 μs, and the capacitance in the loop filter could be on-chip calibrated to ±3.9% precision. The whole frequency synthesiser only consumes 6.6 mA current from a 1.8 V power supply.     

片上自动调谐的可编程有源RC滤波器

研制了一款可编程6阶巴特沃斯有源RC滤波器.为提高滤波器中运算放大器的增益带宽积,设计了一种新型的前馈补偿运算放大器.为消除工艺偏差和环境变化对截止频率的影响,设计了一种片上数字控制频率调谐电路,并采用TSMC 0.18 μm CMOS工艺进行了流片.滤波器采用低通滤波结构,测试结果表明,3 dB截止频率为1～32 MHz,步进1 MHz,带内增益0 dB,带内纹波0.8 dB,2倍带宽处带外抑制不小于24 dBc,5倍带宽处带外抑制不小于68 dBc,滤波器等效输入噪声为340 nV/√Hz@1MHz,调谐误差为±3％.滤波器裸芯片面积0.87 mm×1.05 mm.采用1.8V电源电压,滤波器整体功耗小于20 mW.     

A Zero-Pole Reposition Based, 0.95-mW, 68-dB,Linear-in-dB,Constant-Bandwidth Variable Gain Amplifier

A variable-gain amplifier with very low power consumption and wide tuning range is presented. The operational principle of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by simulation in TSMC 0.18-μm N-well CMOS fabrication process. Owing to the novel zero-pole repositioning technique, the proposed circuit demonstrates very high frequency bandwidth of 79 MHz while drawing only 0.52 mA from 1.8 V power supply. The interesting results such as a very small core area of about 0.0025 mm² as well as a wide linear-in-dB and constant-bandwidth tuning range of 68.2 dB along with a very low power consumption of 0.95 mW are achieved utilizing standard CMOS technology. The stability of the proposed VGA is verified through transient sinusoidal response analysis. Full process, voltage and temperature (PVT) variation analysis of the circuit is also investigated through Monte Carlo and corner case analysis in order to approve the robustness of the structure. Monte Carlo simulations show standard deviation values of 4.6 dB and 78.3 MHz in gain and gain-bandwidth product, respectively. These results show that our zero-pole repositioning method would lend itself well for use in low-power and high-frequency applications, especially in high-speed automatic gain control amplifiers.     

A 900 MHz low power LC-VCO with improved phase noise performance

In this paper, we present the design and development of a low-power LC-VCO with improved phase noise performance by implementing a new capacitor divider varactor configuration and a 2nd order notch filter. We propose a new time-weighted approach to model the effective capacitance experienced by the oscillating signal over the oscillation period. The modeled effective capacitance is used in the calculation of the oscillation frequency, which agrees well with the simulation results. Two VCOs are designed and fabricated in TSMC 0.18 μm technology. The oscillation frequency is tunable from 759 to 910 MHz with a tuning range of 18%. At 900 MHz carrier, the measured phase noise is ?126.1 dBc/Hz at 1 MHz frequency offset with 4.5 mW power consumption.     

A low power Gm-C filter with on-chip automatic tuning for a WLAN transceiver

A sixth-order Butterworth Gm-C low-pass filter(LPF)with a continuous tuning architecture has been implemented for a wireless LAN(WLAN)transceiver in 0.35 μm CMOS technology.An interior node scaling technique has been applied directly to the LPF to improve the dynamic range and the structure of the LPF has been optimized to reduce both the die size and the current consumption.Measurement results show that the filter has 77.5 dB dynamic range,16.3 ns group delay variation,better than 3% cutoff frequency accuracy,and 0 dBm passband IIP3.The whole LPF with the tuning circuit dissipates only 1.42 mA(5 MHz cutoff frequency)or 2.81 mA(10 MHz cutoff frequency)from 2.85 V supply voltage,and only occupies 0.175 mm2 die size.     

A Wide Tuning Range G $ _{rm m}$–C Filter for Multi-Mode CMOS Direct-Conversion Wireless Receivers

A third-order channel selection filter for multi-mode direct-conversion receivers is presented. The filter is designed with a Butterworth prototype and with the target wireless applications of Bluetooth, cdma2000, Wideband CDMA, and IEEE 802.11a/b/g/n wireless LANs. Linear-region MOS transistors are used to perform voltage-to-current conversion. The wide tuning range is achieved by the current multipliers and linear voltage-to-current converters. Implemented in the TSMC 0.18$ muhbox{m}$ CMOS process, the measurement results show that the filter can operate successfully over a cutoff frequency range of 500$~$kHz to 20 MHz, and is compliant with the requirements of different wireless applications. The power consumption is 4.1 mW to 11.1 $~$mW for minimum and maximum cutoff frequencies respectively from a 1.2 V supply voltage. The circuit performance compares favorably with previously reported works.