Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers

Several Miller compensation schemes using a current buffer in series with the compensation capacitor to modify the right-half-plane zero in fully differential two-stage CMOS operational amplifiers are analyzed. One scheme uses a current mirror as a current buffer, while the rest use a common-gate transistor as a current buffer. The gain transfer functions are derived for each topology, and approximate transfer-function coefficients are found that allow accurate estimation of the zero(s) and poles.     

Design procedure for two-stage CMOS operational amplifiers employing current buffer

The design procedure of the two-stage CMOS operational amplifiers employing Miller capacitor in conjunction with the common-gate current buffer is presented. Unlike the previously reported design strategy of the opamp of this type, which results in the opamp with a pair of nondominant complex conjugate poles and a finite zero, the proposed procedure is based upon the design strategy that results in the opamp with only one dominant pole. Design example of the proposed procedure is given.     

Settling time optimisation for two-stage CMOS amplifiers with current-buffer Miller compensation

A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach allows the systematic optimisation of the amplifier time response to be performed avoiding time-consuming trial-and- error design processes. A design example in 0.35 mum CMOS technology is also reported. Circuital and statistical simulations demonstrate the effectiveness of the proposed approach.     

Design approach for fast-settling two-stage amplifiers employing current-buffer Miller compensation

A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach defines a systematic procedure to optimize the amplifier time response, allowing the required speed performances to be achieved without both power wasting and blind efforts for time-consuming trial-and-error design processes. To demonstrate the effectiveness of the methodology, a design example in a commercial 0.35 μm CMOS technology is presented. As shown by circuit and statistical simulations, the proposed strategy proves to be very useful to develop fast-settling operational amplifiers for typical discrete-time applications, such as switched-capacitor filters and ΣΔ analog-to-digital converters.     

Exact design for the settling time of two-stage Miller compensated operational amplifiers

Analog Integrated Circuits and Signal Processing - Most of the currently existed settling time design methods for the Miller-compensated two-stage operational amplifiers are based on the...     

A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors

A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.     

用线性变换运算电流放大器(TOCA)的电流处理电路

本文描述最近引入的新的多功能有源器件—线性变换运算电流放大器的基本性质以及它在电流处理电路中的应用.     

Reversed nested Miller compensation with voltage buffer and ing resistor

This paper presents a new reversed nested Miller compensation technique for multistage operational amplifier (opamp) design. The new compensation technique inverts the sign of the right half complex plane zero and shifts the frequency of the complex conjugate poles to a higher frequency. Simulation results indicate that the gain-bandwidth product and settling time are improved by factors of two and three, respectively, without degrading stability and power consumption. To verify the proposed technique, a three-stage opamp is fabricated with 0.6-/spl mu/m CMOS technology. The measured results of the test circuit agree with the results that are obtained from theoretical analysis and circuit simulation.     

A low-powerlow-voltage slew-rate enhancement circuit for two-stage operational amplifiers

正A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers.The enhancer utilizes the class-AB input stage to improve current efficiency,while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier.During the slewing period,the enhancer detects input differential voltage of the amplifier,and produces external enhancement currents for the amplifier,driving load capacitors to charge/discharge faster.Simulation results show that,fora large input step,the enhancerreduces settling time by nearly 50%.When the circuit is employed in a sample-and-hold circuit,it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB.The proposed circuit is very suitable to operate under a low voltage(1.2 V or below) with a standby current of 200μA.     

Applications of the current feedback operational amplifiers

The current feedback operational amplifiers (CFOAs) are receiving increasing attention as basic building blocks in analog circuit design. This paper gives an overview of the applications of the CFOAs, in particular several new circuits employing the CFOA as the active element are given. These circuits include differential voltage amplifiers, differential integrators, nonideal and ideal inductors, frequency dependent negative resistors and filters. The advantages of using the CFOAs in realizing low sensitivity universal filters with grounded elements will be demonstrated by several new circuits suitable for VLSI implementation. PSPICE simulations using the AD844-CFOA which indicate the frequency limitations of some of the proposed circuits are included.     

一个低功耗低电压的二级运放压摆率增强电路

本文提出了一个新颖的二级运放压摆率增强电路。该电路采用AB类输入级,提高了电流效率。相对于运放,它完全开环工作,因此不会影响运放的稳定性。当运放处于压摆阶段时,电路检测运放输入差分电压,产生外部的动态电流并注入运放,从而使加快负载电容的充/放电过程。电路仿真结果显示：对于大的输入阶跃信号,该电路可以减少50%的建立时间;将电路运用于采样保持电路时,该电路提高了无杂散动态范围44.6dB,降低了总谐波失真43.9dB。本文提出的电路非常适用于低电压（1.2V或更低）工作,并且只消耗200μA的静态电流。     

An automatic offset compensation scheme with ping-pong control forCMOS operational amplifiers

An automatic offset compensation scheme for CMOS operational amplifiers is presented. Offset is reduced by digitally adjusting the bias voltage of a programmable current mirror which is used as the load of the differential input stage. A 100% operating duty cycle is obtained by using a ping-pong structure. The offset compensation scheme is inherently time and temperature stable since the offset compensation is periodically performed with the ping-pong control. The proposed circuit has been fabricated using a 1.0 μm n-well CMOS process. The measured offset voltages of the test circuits are less than 400 μV in magnitude     

Single Miller capacitor frequency compensation technique for low-power multistage amplifiers

Due to the rising demand for low-power portable battery-operated electronic devices, there is an increasing need for low-voltage low-power low-drop-out (LDO) regulators. This provides motivation for research on high-gain wide-bandwidth amplifiers driving large capacitive loads. These amplifiers serve as error amplifiers in low-voltage LDO regulators. Two low-power efficient three-stage amplifier topologies suitable for large capacitive load applications are introduced here: single Miller capacitor compensation (SMC) and single Miller capacitor feedforward compensation (SMFFC). Using a single Miller compensation capacitor in three-stage amplifiers can significantly reduce the total capacitor value, and therefore, the overall area of the amplifiers without influencing their stability. Pole-splitting and feedforward techniques are effectively combined to achieve better small-signal and large-signal performances. The 0.5-/spl mu/m CMOS amplifiers, SMC, and SMFFC driving a 25-k/spl Omega///120-pF load achieve 4.6-MHz and 9-MHz gain-bandwidth product, respectively, each dissipates less than 0.42 mW of power with a /spl plusmn/1-V power supply, and each occupies less than 0.02 mm/sup 2/ of silicon area.     

An improved frequency compensation technique for CMOS operational amplifiers

The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz.     

A floating generalized impedance converter with current feedback operational amplifiers

A novel generalized impedance converter topology realized using current feedback operational amplifiers is introduced in this paper. The main offered benefit, in comparison to the corresponding already published structure, is that frequency dependent negative resistors can now be also realized. Other benefits are the requirement for only grounded capacitors, the lower component count, and the capability of tuning through a grounded resistor. The correct operation of the proposed GIC has been verified through a design example, where a 3rd-order lowpass filter has been topologically simulated.     

A high-precision weak current source using operational amplifiers

An inductor realization scheme with a voltage controlled current source is featured. The types of the passive RC networks necessary in the realization are standard unbalanced two ports. The experimental schemes of the active source are also indicated.     

Novel input stages for current feedback operational amplifiers

This paper considers the trade-offs involved in the design of six new input stages intended to improve the performance of a current feedback operational amplifier (CFOA), over that possible using an established input circuit configuration, with respect to three major characteristics, viz, common mode rejection ratio (CMRR), offset voltage and slew-rate.     

Constant bandwidth current feedback amplifier from two operational amplifiers

In this article, a new constant bandwidth current feedback amplifier is demonstrated using two operational amplifiers and a few components. The circuit is accurate and achieves gains in excess of 20?dB with only a 2.94% change in bandwidth using discrete components in the inverting configuration. The bandwidth can also be accurately defined using two resistors. Experimental results using a dual operational amplifier integrated circuit confirm the measured results.