A power efficient continuous time ΔΣ modulator with 15 MHz bandwidth and 70 dB dynamic range

A state variable block diagram method is given for the realization of universal biquadratic transfer functions employing second-generation current-controlled conveyors (CCCIIs). Using minimum number of passive components and properly adjusting the bias currents of CCCIIs, the proposed circuits can realize all the tunable frequency standard filter functions: high-pass, band-pass, low-pass, notch-pass, and all-pass by choosing appropriate input branches without changing the passive elements. These presented circuits are in current-mode and voltage-mode separately. The non-ideality analyses of these configurations are given. Additionally, a high-order low-pass filter derived from the proposed voltage-mode biquadratic filter is introduced. PSPICE simulation results are included to verify the theory.     

An in-probe receiver amplifier with 3 dB noise figure and 50 dB dynamic range for medical ultrasound imaging using CMUTs

This paper presents the design and measurements of an in-probe receiver amplifier for ultrasound imaging applications using a capacitive micromachined ultrasonic transducer (CMUT). In such applications, the noise and the dynamic range play very important roles, as the former dictates the minimum input signal level and the latter defines the maximum input signal level that can be applied to a system. This work concentrates on both of these specifications. The amplifier consists of a transimpedance amplifier followed by a voltage gain stage implemented using a current feedback amplifier. It is designed and fabricated using a 180 nm CMOS process. A noise figure of 3 dB is measured for a CMUT model with 10–30 MHz frequency range. The amplifier shows a dynamic range of 50 dB with 0.8 % total harmonic distortion for the full scale input current of 7 µA peak-to-peak.     

A 122 TΩ Hz transimpedance bandwidth product BiCMOS optical sensor front-end with a 54.7 dB voltage-controlled photo-sensitivity range

An optical sensor front-end with integrated PIN photodiode in 0.6 μm BiCMOS technology intended for universal optical storage operation is presented. It is based on a mixed current conveyor and voltage amplifiers topology avoiding stability problems. The transimpedance is continuously variable and directly proportional to a voltage-controlled resistance. Another voltage-controlled resistor within a variable-gain voltage amplifier increases the photo-sensitivity range. A fixed-gain voltage amplifier and a current biasing of the current conveyor enable frequency bandwidth enhancement leading to a large transimpedance bandwidth product. A linearity error smaller than 2.8%, a photo-sensitivity range of 541 (54.7 dB) with the largest photo-sensitivity of 2468 mV/μW, an offset voltage <13.7 mV, a frequency bandwidth up to 277 MHz, a slew rate up to 377 V/μs, a transimpedance bandwidth product up to 122 TΩ Hz, and a maximum power consumption of <4.3 mW are achieved.     

A 0.4–3.3 GHz low-noise variable gain amplifier with 35 dB tuning range, 4.9 dB NF,and 40 dBm IIP2

This work presents a low-noise variable gain amplifier (LNVGA) in which the IIP2 is very high, and the gain control is applied to improve the system dynamic range, even with the limitations of the CMOS technology. Two stages compose the LNVGA, a low-noise amplifier, that keeps the noise figure (NF) at low values, and a variable voltage attenuator (VVA), that provides the gain variation. We have applied on the VVA the phase cancellation technique, in which the addition of two out-of-phase signals controls the gain. This technique provides a large gain tuning range only if the paths of the two signalsto be added are well balanced; hence, a precise 180 degrees phase difference is required. In this desing we propose an active balun with small imbalance, which creates those signals. The LNVGA was implemented in 130 nm CMOS with a 1.2 V supply. The measurement results show a 35 dB gain tuning range, varying from 10 to ? 25 dB, a 4.9 dB minimum NF, a ? 10 dBm IIP3, and an IIP2 as high as + 40 dBm.     

A 1 Gsps and 840 µW fully dynamic asynchronous pipelined binary search ADC

In this paper a very low power asynchronous 5-bit ADC in CMOS 45 nm process technology is described which combines the pipeline and binary search architectures. Due to utilization of dynamic non-linear amplifier, power consumption of the converter is very low. The ADC circuit uses digital calibration technique to update the reference voltages of the comparators. The power consumption of ADC is 840 µW, and the ENOB is 4.05 at 1 Gsps with input signal at the Nyquist rate. At sampling rate of 10 0Msps, the power consumption is reduced to 89 µW and the ENOB is equal to 4.6 again at the Nyquist rate.     

A 0.8-3 GHz RF-VGA with 35 dB dynamic range in 0.13μm CMOS

正A wideband variable gain amplifier(VGA) implemented in 0.13μm CMOS technology is presented. To optimize noise performance,an active feedback amplifier with 15 dB fixed gain is put in the front,followed by modified Cherry-Hooper amplifiers in cascade providing variable gain,which adopt dual loop feedback for bandwidth extension.Negative capacitive neutralization and capacitive source degeneration are employed for Miller effect compensation and DC offset cancellation,respectively.Measurement results show that the proposed VGA achieves a 35 dB gain tuning range with an upper 3-dB bandwidth larger than 3 GHz and the input 1 dB compression point of-29 dBm at the lowest gain state,while the minimum noise figure is 9 dB at the highest gain state. The core VGA(without test buffer) consumes 32 mW from 1.2 V power supply and occupies 0.48 mm2 area.     

Design-to-testing: a low-power, 1.25 GHz,single-bit single-loop continuous-time $$\Delta \Sigma$$ modulator with 15 MHz bandwidth and 60 dB dynamic range

Continuous-time Delta-Sigma (CT-\(\Delta \Sigma\)) analog-to-digital converters have been extensively investigated for their use in wireless receivers to achieve conversion bandwidths >15 MHz and higher resolution of 10–14 bits. This paper presents the complete design-to-testing tutorial of a state-of-the-art high-speed single-bit CT-\(\Delta \Sigma\) architecture and its circuit design details in 0.13 μm CMOS technology node sampling at 1.25 GS/s. The designed modulator achieves higher dynamic range of 60 dB in a wide conversion bandwidth of 15 MHz and consumes only 3.5 mW. The proposed modulator achieves a Figure of Merit of 154 fJ/level.     

A 0.18μm CMOS gain-switched LNA and mixer with large dynamic range

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier （LNA） and a passive mixer with no external balun for near-zero-IF （Intermediate Frequency）/RF （Radio Frequency） applications are described. The LNA, fabricated in the 0.18μm 1P6M CMOS technology, adopts a gain-switched technique to increase the linearity and enlarge the dynamic range. The mixer is an IQ-based passive topology. Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω. Combining LNA and mixer, the front-end measured performances in high gain state are： -15dB of Sll, 18.5dB of voltage gain, 4.6dB of noise figure, 15dBm of IIP3, 85dBm to -10dBm dynamic range. The full circuit drains 6mA from a 1.8V supply.     

A 0.5–1 GHz single stage linear-in-decibel VGA with 80 dB gain range in 0.18 μm CMOS

Communication systems require a wide gain range. For example the code-division multiple access system (CDMA) requires more than 80 dB of gain range so that, many variable gain amplifiers (VGAs) must be used, resulting in high power consumption and low linearity because of VGA non-linearity factors. In this paper, a one-stage VGA in 0.18 μm technology is presented. The VGA based on the class AB power amplifier is designed and simulated for a high linearity and an 80 dB tuning range. For the linear-in-decibel tuning range, transistors in sub-threshold region is used. The current control circuit of the VGA changes gain continuously from ?68 to 18 dB at 0.5 GHz and ?60 to 20 dB at 1 GHz with gain error of less than 2 dB. The power consumption enjoys a highest value about 13.5 mW in the maximum gain and P1dB is also about ?3.4 dBm at 0.5 GHz and 2.2 dBm at 1 GHz.     

A selectable-bandwidth 3.5 mW, 0.03?mm2 self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5?MHz and 65 dB at 10?MHz bandwidth

In this paper we present a dual-mode third-order continuous time $\Upsigma\Updelta$ modulator that combines noise-shaping and pulse-width-modulation (PWM). In our 0.18???m CMOS prototype chip the clock frequency equals 1?GHz, but the PWM carrier is only around 125?MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10?MHz. In the 5?MHz mode the peak SNDR equals 64?dB and the dynamic range 71?dB. In the 10?MHz mode the peak SNDR equals 58?dB and the DR 65?dB. This performance is achieved at an attractively low silicon area of 0.03?mm² and a power consumption of 3.5?mW.     

A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-\Updelta\Upsigma ADC with 1.5 cycle quantizer delay and improved STF

A 1 GS/s continuous-time delta-sigma modulator (CT- $\Updelta\Upsigma$ M) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT- $\Updelta\Upsigma$ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT- $\Updelta\Upsigma$ M has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2 V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.     

A 6.4 mW, 4.9 nV/√Hz, 24 dBm IIP3 VGA for a multi-standard (WLAN,UMTS, and Bluetooth) receiver

A low-power high-linearity variable-gain-amplifier (VGA) to be embedded in a multi-standard receiver (WLAN, UMTS and Bluetooth) is reported. The multi-standard receiver architecture presents considerable different VGA requirements (in terms of bandwidth, DC-gain, noise level, and common mode input voltage) for the three telecom standards. The VGA is positioned just after the mixer, and, then, it operates on low- amplitude input signals. This results in stronger noise requirements than linearity ones. Thus a digitally controlled open-loop structure has been used. The prototype VGA is realized in a 0.13 μm CMOS technology and it features gain levels from −10 to 36 dB. For 0 dB DC-gain it exhibits a 25 dBm IIP3 and an input-referred noise voltage lower than 5 nV/√Hz. This gives a 85 dB-DR for the WLAN case. The VGA draws 6.4 mA from a single 2.5 V supply.     

A 22?mW 512?MHz CMOS continuous time sigma delta ADC in 1.2?V with 16?MHz signal bandwidth and 70?dB dynamic range

A wide bandwidth continuous time sigma delta analog-to-digital conversion is implemented in 130?nm process. The circuit is targeted for wide bandwidth applications such as video or wireless base-stations. The third-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512?MHz clock frequency. To reduce the clock jitter sensitivity, nonreturn-to-zero DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer, and the degradation of modulator stability due to excess loop delay is avoided with this architecture. The sigma delta ADC achieves a 60?dB SNR and a 59.3?dB signal-to-noise-plus-distortion ratio over a 16?MHz signal band at an oversampling ratio of 16. The power consumption of the continuous time sigma delta modulator is 22 mW from the 1.2?V supply.     

0–30?V common mode range, 120?dB CMRR, and 10?nV/ \sqrt {\text{Hz}} noise floor current shunt monitor IC with an embedded ΣΔ modulated digital interface

Sensing and controlling current flow is a fundamental requirement for many electronic systems, including power management (DC?CDC converters and LDOs), battery chargers, electric vehicles, solenoid positioning, motor control, and power monitoring. Current shunt monitor (CSM) system enables current measurement across an external sense resistor (R _S ) in series to current flow. Proposed CSM system can sense a system (power supply) current from 1 to 500?mA across a typical board Cu-trace resistance of 1??? with less than 10???V input-referred offset, 150?nV/°C offset drift and 0.1% accuracy. Instead of using a costly zero-TC sense resistor (R _S ) that is used in typical CSM systems; proposed method uses existing Cu board trace for sensing. The sense amplifier uses chopper stabilization in the signal chain of the amplifier to suppress input-referred offset down to less than 10???V. Switching current-mode (SI) FIR filtering is used at the instrumentation amplifier output to filter out the chopping ripple at the harmonics of the chopping frequency. A frequency domain Sigma Delta (????FD) ADC enables a digital interface to processor applications. The CSM is fabricated on a 0.7???m CMOS process with three levels of metal with maximum Vds tolerance of 8?V, and operates across a common mode range of 0?C30?V achieving less than 10?nV/ $ \sqrt {\text{Hz}} $ of flicker noise at 100?Hz. By using a semi-digital SI FIR filter, residual chopper ripple is suppressed by more than 7.5?mV_pp from the base line of 8?mV_pp, which is equivalent to 25?dB suppression.     

A 6–9 GHz UWB balun-LNA employing current-reuse with preamplifier and CCC buffer

This paper presents a high-gain and low-power balun-LNA for ultra-wideband receiver operating in the upper band (6–9 GHz). Common gate (CG) preamplifier in front of the active balun can provide input matching and suppress noise from the follow-up stages. Active balun shares bias current with the CG stage to reduce power consumption. Capacitor-cross-coupled buffer is cascaded for signal amplitude and phase correction. The balun-LNA is fabricated in TSMC 130 nm CMOS technology and it consumes 5.5 mA current from a 1.3-V supply including buffer. This balun-LNA can achieve wideband gain from 6.5 to 9.0 GHz and the maximum gain is 23 dB. The input return loss is better than 20 dB from 6.5 to 9.0 GHz. The core area of the LNA is 0.53 mm². Simulated noise figure of the LNA is under 3.2 dB.     

A 0.8–3GHz RF-VGA with 35dB dynamic range in 0.13μm CMOS* Qin Xi(秦希), Huang Xingli(黄杏丽), Qin Yajie(秦亚杰), Hong Zhiliang(洪志良)?

本文提出了一种使用0.13μm CMOS工艺实现的宽带可变增益放大器（VGA）结构。为了优化该VGA的噪声性能,一个具有15dB固定增益、采用有源反馈结构的预放大器被用来作为第一级,之后采用级联的改进型Cherry-Hooper放大器提供增益调节,双反馈环路在这里被用来扩展Cherry-Hooper放大器的带宽。负容性中和和电容源极退化技术分别被用来进行密勒效应补偿和直流失调取消。测试结果显示,该VGA达到35dB增益调节范围,其高端3dB带宽大于3GHz,在最低增益时,1dB压缩点为-29dBm,在最高增益时,噪声系数达到9dB。该VGA（不包括输出缓冲器）在1.2V电源电压下消耗32mW功率,占用芯片面积为0.48mm₂。