高速数字电路相位噪声测试研究

对高速数字电路相位噪声测试技术进行了探索.利用直接频谱仪法、鉴相器法、鉴频器法等相位噪声测试方法,通过阻抗匹配等合理的测试设计,开发出测试系统,对高速数字电路相位噪声进行了测试研究,获得了准确的测试数据,有效地表征了电路实际性能.     

Controllability of Static CMOS Circuits for Timing Characterization

Timing violations, also known as delay faults, are a major source of defective silicon in modern Integrated Circuits (ICs), designed in Deep Sub-micron (DSM) technologies, making it imperative to perform delay fault testing in these ICs. However, DSM ICs, also suffer from limited controllability and observability, which impedes easy and efficient testing for such ICs. In this paper, we present a novel Design for Testability (DFT) scheme to enhance controllability for delay fault testing. Existing DFT techniques for delay fault testing either have very high overhead, or increase the complexity of test generation significantly. The DFT technique presented in this paper, exploits the characteristics of CMOS circuit family and reduces the problem of delay fault testing of scan based sequential static CMOS circuits to delay fault testing of combinational circuits with complete access to all inputs. The scheme has low overhead, and also provides significant reduction in power dissipation during scan operation.

大规模集成电路相关测试标准的剖析

集成电路测试是保证集成电路质量、发展的关键手段.CMOS器件进入超深亚微米阶段,集成电路继续向高集成度、高速度、低功耗发展,使得IC在测试和可测试性设计上都面临新的挑战.重点研究了纯数字信号、混合信号和片上系统测试的一些问题和相关标准,包括IEEE 1149.1-1990到IEEE 1149.6-2003,IEEE 1450,IEEE 1500,IEEE-ISTO Nexus 5001等测试标准.总结了集成电路测试标准的特点和最新进展,分析了这些标准在实际应用中存在的一些问题及其局限性,并对今后集成电路测试技术标准的发展给出了预测.     

Design of ICs applying built-in current testing

Built-in Current (BIC) sensors have proven to be very useful in testing static CMOS ICs. In a number of experimental ICs BIC sensors were able to detect small abnormal I _DDQ currents. This paper discusses the design of the circuit under test and Built-in Current (BIC) sensors, which provide: maximum level of defect detectability, minimum impact of BIC sensor on the performance of the circuit under test and minimum area overhead needed for BIC sensors implementation.This research was supported by NSF Grant MIP8822805.     

浅谈对集成电路加速寿命试验的认识

老炼、稳态寿命等加速寿命试验是衡量集成电路使用寿命的主要手段。文中简要介绍了集成电路的主要可靠性指标——FIT,呈现集成电路失效特征的"浴盆曲线",以及不同失效阶段的主要影响因素、失效率与时间相关的统计分布特征。在此基础上,文章对老炼和稳态寿命的试验目的进行了说明,并列出稳态寿命试验的等效试验条件表以及通过该试验的集成电路使用寿命的一些参考数据。     

ICCQ: A Test Method for Analogue VLSI Using Local Current Sensors

This paper describes a test method for analogue (parts of) ICs that determines whether an IC is good or not by measuring the currents flowing through its constituent circuits. The ICCQ test method is not a full functional test. It is aimed primarily at finding faulty circuits during wafer testing. Both static and dynamic currents can be tested with this test method.     

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.      

双倍可变观测点的时滞测试

随着高速集成电路的发展,对时滞测试的研究越来越重要了,时滞测试的主要困难来自于与电路的门数成指数增长的庞大通路数,以及大量的时滞不可测通路。本文提供了一种使用双倍可变观测点进行时滞测试的方法,保证了只需要测试少量通路就能完成整个电路的时滞测试,它所付出的代价是：对每一个测试向量对,测试仪需要在原始输出采样两次以确定预期跳变的传输时间,此方法所需测试的通睡数与被测电路的门数成线性增长关系,从而很大程     

Simulating the exposure of ICs to voltage surges caused by nuclear explosions

A uniform strategy is developed for testing discrete semiconductor devices and ICs for voltagesurge hardness, allowing comparison of differing models including ICs of high functional complexity. Performance specifications are defined, justified, and implemented for a voltage-surge simulator intended for electrical-overstress hardness tests of ICs. On this basis, a test bed is designed and built for evaluating the hardness of advanced ICs to voltage-surge effects, whether transient or permanent. A procedure is developed for predicting the electrical-overstress hardness of ICs, which enables one to detect both out-of-tolerance and functional failures during testing. The procedure and the test setup are validated by experiments with specific ICs.     

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using currentmode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-μm CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors     

A Test Methodology for High Performance MCMs

Satellite and avionics applications represent an ideal application for the tremendous performance, cost, space, andreliability benefits of MCMs. These advantages are only realized,however, if accompanied by an efficient test strategy whichverifies defect-free fabrication. This paper describes a methodology developed to test high performance VLSI CMOS ICs thathave been mounted onto a multi-chip silicon substrate. A teststrategy, which addresses testing from the wafer level through tothe populated substrate, is detailed. This strategy uses acombination of LSSD, AC LSSD-On-Chip Self Test, Deterministic Delay Fault Testing, and Design for Partitionability to ensure high testquality at a reasonable cost. The methodology is then contrastedto alternative approaches.     

基于HyperLynx的高速PECL交流耦合时钟设计

随着高速数据传输发展的需求,在高速IC之间的时钟路径变得越来越关键,成为影响系统性能、功耗及噪声的关键因素。PECL(正电压射极耦合逻辑)信号作为一种适合高速逻辑互联的电平标准,越来越多地应用在高速A/D转换器的时钟设计中。介绍了一种交流耦合形式的PECL高速时钟设计方法。在时钟的端接设计中,采用串联终端匹配和并联终端匹配改善信号完整性,并利用HyperLynx软件进行仿真,取得了良好的效果,对于实际电路设计有良好的指导作用。     

A new ESD protection structure for high-speed GaAs RF ICs

We demonstrate a new electrostatic discharge (ESD) protection structure for high-speed GaAs RF ICs. The structure is composed of small diodes and large transistors using an InGaP heterojunction bipolar transistor (HBT) technology. Its loading effect and its robustness are evaluated experimentally. The impedance of the new structure at OFF state, represented with an equivalent shunt capacitance and an equivalent shunt resistance, are 0.22 pF and 500 /spl Omega/ at 10 GHz. The structure can withstand +2700-V and -2900-V human body model ESD pulses. It can clamp voltage more effectively than the conventional diode-based ESD structure. The new structure can be used to protect 10 Gb/s input/output pins of high-speed RF ICs against ESD.     

On-Chip Delay Measurement Based Response Analysis for Timing Characterization

We present techniques for response analysis for timing characterization, i.e., delay test and debug of Integrated Circuits (ICs), using on-chip delay measurement of critical paths of the IC. Delay fault are a major source of failure in modern ICs designed in Deep Sub-micron technologies, making it imperative to perform delay fault testing on such ICs. Delay fault testing schemes should enable detection of gross as well as small delay faults in such ICs to be efficient. Additionally there is a need for performing efficient and systematic silicon debug for timing related failures. The timing characterization techniques presented in this paper overcome the observability limitations of existing timing characterization schemes in achieving the aforementioned goals, thus enabling quick and efficient timing characterization of DSM ICs. Additionally the schemes have low hardware overhead and are robust in face of process variations.     

1 Gbit/s, 32*32 high-speed space-division switching module for broadband ISDN using SST LSIs

A high-speed 32*32 space-division switching module for high-definition TV broadcasting and switching systems is described. It employs a newly developed Si-bipolar SST 8*8 switch LSI, high-speed peripheral ICs and a high-speed impedance-controlled board. The module is capable of a 1.0 Gbit/s signal speed using 1:1 and 1:n connections.<>     

Highly uniform InAlAs-InGaAs HEMT technology for high-speed optical communication system ICs

The authors have developed a highly uniform, InP-based high-electron-mobility transistor (HEMT) technology for high-speed optical communication system integrated circuits (ICs). Special attention was paid to obtaining a high yield and uniformity without degrading the high-frequency characteristics of these HEMTs. An InP etch-stopper layer was employed to control the gate recess etching. The authors successfully fabricated InAlAs-InGaAs HEMTs with a cutoff frequency of 175 GHz after interconnection, which is sufficiently high for application in 40-Gb/s optical communication ICs. The standard deviation of the threshold voltage was only 13 mV across a 3-in wafer. They also developed a fabrication process for a Y-shaped gate to maintain high uniformity, enabling us to integrate more than a thousand transistors with a 0.1-/spl mu/m-class gate length. With this technology, ICs with over 1000 transistors were successfully fabricated and operated at over 40 Gb/s. Furthermore, the authors fabricated a 2:1 multiplexer that had more than 200 transistors and reached an operating speed of 90 Gb/s. They have thus concluded that their InAlAs-InGaAs HEMT technology can be applied to fabricate high-speed ICs for optical communication systems.     

Optimal life testing schedule for multiple types of integratedcircuits

Life testing of highly reliable integrated circuits (ICs) is a time-consuming process because it usually takes a long time before an IC fails. Several methods have been proposed in the literature to reduce the time required for testing one type of IC. The author considers the problem of estimating the mean life of I types of IC (I>1). Assuming that the lifetime distribution of the ICs is exponential and at most N ICs can be tested concurrently, it is shown that the optimal life testing schedule that requires the smallest mean testing time is to test N ICs of type 1, then test N ICs of type 2,. . . and finally test N ICs of type I      

A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters

Testing high-speed A/D converters for dynamic specifications needs test equipment running at high frequency. In this paper, a methodology to test high-speed A/D converters using low-frequency resources is described. It is based on the alternate testing approach. In the proposed methodology, models are built to map the signatures of an initial set of devices, obtained on the proposed low-cost test set-up, to the dynamic specifications of the same devices, obtained using high-precision test equipment. During production testing, the devices are tested on the low-cost test set-up. The dynamic specifications of the devices are estimated by capturing their signatures on the low cost test set-up and processing them with the pre-developed models. As opposed to the conventional method of dynamic specification testing of data converters, the proposed approach does not require the tester resources running at a frequency higher than the device-under-test (DUT). The test methodology was verified in simulations as well as in hardware with specification estimation error of less than 5%.

Influence of transmission-line interconnections betweengigabit-per-second ICs on time jitter and instabilities

The influence of transmission-line interconnections between high-speed ICs on time jitter and oscillations is investigated. Simple but flexible methods for estimating these effects are proposed and proved by measurements and simulations. The estimations are based on small-signal reflection coefficients. Moreover, various line terminations are discussed. A special gigabit-per-second bipolar IC was fabricated for the experiments     

BIST TPG for Combinational Cluster Interconnect Testing at Board Level

A novel built-in self-test (BIST) architecture and a test pattern generator (TPG) design methodology to program this architecture are presented for inter-IC interconnects among combinational non-boundary scan ICs (often called cluster-ICs) via IEEE 1149.1 boundary scan architecture (BSA). Due to the expense and complexity of BSA circuitry, cluster-ICs are still widely used in modern circuit boards. Since combinational logic and 3-state cluster nets exist within cluster interconnect, in order to test all detectable faults in inter-IC nets that include cluster-ICs, newly identified TPG requirements are used to guarantee fault coverage during the design of proposed BIST architecture. This architecture contains a two-level C-TPG that generates constrained pseudo-random patterns for boundary scan cells (BSCs) of cluster control cones, a D-TPG that generates patterns for BSCs of cluster data cones, and a look-up table which is programmed to select, for each BSC, a specific C-TPG or D-TPG stage whose content is shifted into that BSC. This test architecture provides a true BIST solution for cluster testing. The proposed methodology generates TPGs that (i) guarantee the avoidance of multi-driver conflicts when testing via BSA, (ii) guarantee the detection of all testable interconnect faults, (iii) have low area overheads, and (iv) have short test lengths.