石墨烯压力传感器Au-Si共晶键合的气密性封装

针对石墨烯压力传感器的高气密性封装要求，设计了一种应用于石墨烯压力传感器的Au-Si键合工艺。采用Au-Si键合工艺只需要在传感器的密封基板表面生长一层100 nm的SiO₂,并在生长的SiO₂表面溅射金属密封环，密封环金属采用50 nm/300 nm的Ti/Au。使用倒装焊机在380℃以及16 kN的压力环境下保持20 min完成传感器芯片与基板的键合，实现石墨烯压力传感器的气密性封装。键合完成后对键合指标进行表征测试，平均剪切力可达19.596 MPa,平均泄露率为4.589×10^-4 Pa·cm³/s。通过对键合前后石墨烯传感器芯片电阻检测，电阻输出平均值变化了3.36%,键合前后电阻输出相对稳定。对传感器进行静态压力检测，其灵敏度>0.3 kΩ/MPa,非线性<1%FS。实验结果表明，石墨烯压力传感器采用Au-Si键合工艺进行气密封装不仅工艺简单，且强度高。     

面向先进封装应用的混合键合技术研究进展

随着摩尔定律推进至纳米级节点,以硅通孔(TSV)、重布线层(RDL)、薄芯片堆叠键合等为支撑的三维集成被认为是延续摩尔定律的重要途径. Cu/SiO₂混合键合可以持续缩小芯片间三维互连节距、增大三维互连密度,是芯片堆叠键合前沿技术. 近年来它在互补金属氧化物半导体(CMOS)图像传感器(CIS)、Xtacking 3D NAND、 2.5D/3D集成等商业化应用突破,使之成为国内外领先半导体研究机构研究关注的热点话题. 本文将系统梳理混合键合技术的研究历史与产业应用现状,重点分析近年来国内外代表性研究工作的技术路线、研究方法、关键问题等, 在此基础上,对混合键合技术的未来发展方向进行展望.     

基于混合气体活化的硅基钽酸锂晶圆键合研究

集成在硅基衬底上的钽酸锂薄膜在新型声学器件上具有重要应用，等离子体活化键合是其主要的集成方式，相关研究报道众多但仍缺乏对等离子体活化工艺的深入研究。本文研究了LT和Si衬底晶圆在不同活化气氛、频率和时间下的亲水性接触角变化情况，探索了一套可以显著提高键合强度的活化参数。研究结果发现，对晶圆表面采用N₂加O₂混合活化60 s后，LT和Si衬底晶圆亲水性接触角达到最小值，分别为4.244°和3.859°。键合后用SEM扫描了样片的横截面，发现键合质量良好。最后对比了用O₂、N₂和Ar活化60 s,以及N₂加O₂混合活化60 s后键合片的键合强度，发现混合气体活化后键合强度最大，达到了9.05 MPa。     

不同退火氛围对TiN/HfO2/SiO2/Si结构电荷分布的影响

热退火技术是集成电路制造过程中用来改善材料性能的重要手段。系统分析了两种不同的退火条件(氨气氛围和氧气氛围)对TiN/HfO₂/SiO₂/Si结构中电荷分布的影响,给出了不同退火条件下SiO₂/Si和HfO₂/SiO₂界面的界面电荷密度、HfO₂的体电荷密度以及HfO₂/SiO₂界面的界面偶极子的数值。研究结果表明,在氨气和氧气氛围中退火会使HfO₂/SiO₂界面的界面电荷密度减小、界面偶极子增加,而SiO₂/Si界面的界面电荷密度几乎不受退火影响。最后研究了不同退火氛围对电容平带电压的影响,发现两种不同的退火条件都会导致TiN/HfO₂/SiO₂/Si电容结构平带电压的正向漂移,基于退火对其电荷分布的影响研究,此正向漂移主要来源于退火导致的HfO₂/SiO₂界面的界面偶极子的增加。     

STI CMP中SiO2/CeO2混合磨料对SiO2介质层CMP性能的影响

为了在浅沟槽隔离(STI)化学机械平坦化(CMP)过程中提高对SiO₂介质层去除速率的同时保持晶圆表面一致性,研究了SiO₂/CeO₂混合磨料的协同作用以及对SiO₂介质层去除速率及一致性的影响。结果显示,相比于单一磨料,采用混合磨料能够兼顾介质去除速率和一致性。采用质量分数10%SiO₂(粒径为80 nm)与质量分数0.7%CeO₂磨料混合抛光后,对介质层的去除速率达到347 nm/min,片内非均匀性(WIWNU)为9.38%。通过场发射扫描电子显微镜(FESEM)观察颗粒状态发现,晶圆表面吸附大量的SiO₂颗粒会阻碍CeO₂磨料与晶圆表面接触,从而降低对晶圆中心的去除速率,使化学作用更均匀。通过将小粒径SiO₂磨料(40 nm)与CeO₂磨料混合,使介质层去除速率进一步提升至374 nm/min, WIWNU降低到8.83%,用原子力显微镜(AFM)表征抛光后晶圆...     

TSV立体集成用Cu/Sn键合工艺

为实现硅通孔(TSV)立体集成多层芯片可靠堆叠,对一种具备低温键合且不可逆特点的Cu/Sn等温凝固键合技术进行了研究。基于Cu/Sn系二元合金平衡相图,分析了金属层间低温扩散反应机理,设计了微凸点键合结构并开展了键合工艺实验。通过优化键合工艺参数,获取了性能稳定的金属间化合物(IMC)层,且剪切力键合强度值达到了国家标准,具备良好的热、机械特性。将其应用到多芯片逐层键合工艺实验当中,成功获取了4层堆叠样品,验证了Cu/Sn等温凝固键合技术在TSV立体集成中的应用潜力。     

Cu/Sn等温凝固技术在MEMS气密封装中的应用

研究了Cu/Sn等温凝固键合技术在MEMS气密性封装中的应用。设计了等温凝固键合多层材料的结构和密封环图形,优化了键合工艺,对影响气密性的因素(如密封环尺寸等)进行了分析。在350°C实现了良好的键合效果,其最大剪切强度达到27.7MPa,漏率~2×10-4Pa·cm3/sHe,完全可以满足美国军方标准(MIL-STD-883E)的要求,验证了Cu/Sn等温凝固键合技术在MEMS气密封装中的适用性。     

含TSV结构的3D封装多层堆叠Cu/Sn键合技术

研究了利用Cu/Sn对含硅通孔(TSV)结构的多层芯片堆叠键合技术。采用刻蚀和电镀等工艺,制备出含TSV结构的待键合芯片,采用扫描电子显微镜(SEM)对TSV形貌和填充效果进行了分析。研究了Cu/Sn低温键合机理,对其工艺进行了优化,得到键合温度280℃、键合时间30 s、退火温度260℃和退火时间10 min的最佳工艺条件。最后重点分析了多层堆叠Cu/Sn键合技术,采用能谱仪(EDS)分析确定键合层中Cu和Sn的原子数比例。研究了Cu层和Sn层厚度对堆叠键合过程的影响,获得了10层芯片堆叠键合样品。采用拉力测试仪和四探针法分别测试了键合样品的力学和电学性能,同时进行了高温测试和高温高湿测试,结果表明键合质量满足含TSV结构的三维封装要求。     

甲酸预处理对基于Cu/Ag混合纳米颗粒的Cu-Cu键合的影响北大核心CSCD

针对功率电子器件中电气互连的需求,提出了一种适用于功率电子器件封装的Cu-Cu键合工艺。采用纳米尺寸的Cu/Ag混合颗粒浆料作为Cu-Cu键合的中间层,并利用甲酸气体在最佳预处理温度180℃对Cu/Ag混合纳米颗粒浆料进行预处理,之后在260℃的键合温度、外加5 MPa压力的情况下完成Cu-Cu键合。通过测试发现,甲酸气体预处理后混合纳米颗粒浆料中Cu纳米颗粒表面的氧化物得到了有效还原,使得混合纳米颗粒烧结得更充分,键合后的截面变得更致密。此外,甲酸气体预处理后的断面上产生了明显的韧性形变,且Cu-Cu键合的剪切强度平均值达到65.6 MPa。结果表明,该种键合工艺可靠,为功率电子器件封装中高可靠的Cu-Cu键合提供了新的解决方案。     

基于低温氧化的4H-SiC/SiO2界面态钝化方案

阐述4H-SiC晶圆的Si面上通过CVD淀积与低温热氧化生长的双层栅氧化物结构，在高温氮气环境下可降低4H-SiC/SiO₂界面的高密度界面缺陷。采用PECVD淀积一层均匀的SiO₂膜后，通过热氧化工艺在淀积膜与4H-SiC/SiO₂间生长一层很薄的氧化物过渡层。根据不同温区间热氧化温度形成的SiO₂膜晶型不同，改变界面中氮气退火过程中氮元素的引入，从而钝化4H-SiC/SiO₂的界面缺陷。     

Interfacial Reactions in Cu/Ga and Cu/Ga/Cu Couples

Cu-to-Cu bonding to connect through-silicon vias in three-dimensional integrated-circuit packaging is the most important interconnection technology in the next-generation semiconductor industry. Soldering is an economic and fast process in comparison with diffusion bonding methods. Ga has high solubility of up to 20 at.% in the Cu-rich face-centered cubic (FCC) phase and high mobility at moderate temperatures. In this work, an attempt has been made to evaluate Ga-based Cu-to-Cu interconnection by transient liquid-phase (TLP) bonding. The Cu/Ga interfacial reactions at temperatures ranging from 160°C to 300°C were examined. For reactions at temperatures lower than 240°C, the reaction path is Cu/γ ₃-Cu₉Ga₄/θ-CuGa₂/liquid, where the γ ₃-Cu₉Ga₄ and θ-CuGa₂ phases are thin planar and thick scalloped layers, respectively, while for the reactions at 280°C and 300°C, the scalloped γ ₃-Cu₉Ga₄ phase is the only reaction product. The phase transformation kinetics, reaction mechanisms, and microstructural evolution in the Cu/Ga couples are elaborated. In addition, reactions of Cu/Ga/Cu sandwich couples at 160°C were investigated. The original Cu/liquid/Cu couples isothermally transformed to Cu/γ ₃-Cu₉Ga₄/ θ-CuGa₂/γ ₃-Cu₉Ga₄/Cu couples as the reaction progressed. However, cracks were observed in the θ-CuGa₂ phase regions after metallographic processing. The brittle θ-CuGa₂ phase is undesirable for Ga-based TLP bonding.     

Cu/Ta/SiO_2/Si多层结构的纳米压痕研究

利用磁控溅射方法在Si衬底上沉积钽层以及铜层,并利用纳米压痕技术对Cu/Ta/SiO_2/Si多层膜结构进行了硬度和弹性模量的表征,研究发现多层膜结构的硬度随着薄膜厚度的增加而降低,然而弹性模量与膜厚之间并没有这样的关系。利用聚焦离子束（FIB）工艺将纳米压痕区域剖开,并通过透射电子显微镜（TEM）表征发现在纳米压痕过后,钽以及二氧化硅界面有了明显的分层现象,这一点表明层与层之间较弱的键合在相对大的负荷下遭到了破坏。     

The effects of boron in the Cu(B)/Ti/SiO<Subscript>2</Subscript> system on the Cu-Ti reaction,resistivity, and diffusion barrier properties

The behavior of boron in Cu(4.8at.%B)/Ti/SiO₂ was investigated as a function of temperature, and its influences on the Cu-Ti interaction, resistivity, and diffusion barrier properties were also studied. The results showed the formation of a titanium boride layer at the Cu-Ti interface, after heating the Cu(B)/Ti/SiO₂ at 400°C and higher, effectively served as a barrier for the Cu and Ti diffusion, and significantly enhanced the Cu (111) texture. The resistivity dropped from 16.3 to 2.33 μΩ-cm after heating at 600°C, and continued to decrease up to 800°C. As a result, the Cu, in the form of B(O)_x/Cu/TiB₂/Ti(O)_x/SiO₂ multilayers, obtained by heating the Cu(B)/Ti/SiO₂, showed high thermal stability with low resistivity and, thus, can be used as interconnections in advanced integrated circuits. Since the Cu, in the form of B(O)_x/Cu/TiB₂/Ti(O)_x/SiO₂ multilayers, obtained by heating the Cu(B)/Ti/SiO₂, showed high thermal stability with low resistivity, it can be used as interconnections in advanced integrated circuits.     

基于SiO2溶胶的稳定性的Cu/SiO2催化体系在化学机械抛光中的应用研究

There is a lot ofhydroxyl on the surface ofnano SiO2 sol used as an abrasive in the chemical mechanical planarization （CMP） process, and the chemical reaction activity of the hydroxyl is very strong due to the nano effect. In addition to providing a mechanical polishing effect, SiO2 sol is also directly involved in the chemical reaction. The stability of SiO2 sol was characterized through particle size distribution, zeta potential, viscosity, surface charge and other parameters in order to ensure that the chemical reaction rate in the CMP process, and the surface state of the copper film after CMP was not affected by the SiO2 sol. Polarization curves and corrosion potential of different concentrations of SiO2 sol showed that trace SiO2 sol can effectively weaken the passivation film thickness. In other words, SiO2 sol accelerated the decomposition rate of passive film. It was confirmed that the SiO2 sol as reactant had been involved in the CMP process of copper film as reactant by the effect of trace SiO2 sol on the removal rate of copper film in the CMP process under different conditions. In the CMP process, a small amount of SiO2 sol can drastically alter the chemical reaction rate of the copper film, therefore, the possibility that Cu/SiO2 as a catalytic system catalytically accelerated the chemical reaction in the CMP process was proposed. According to the van＇t Hoff isotherm formula and the characteristics of a catalyst which only changes the chemical reaction rate without changing the total reaction standard Gibbs free energy, factors affecting the Cu/SiO2 catalytic reaction were derived from the decomposition rate of Cu （OH）2 and the pH value of the system, and then it was concluded that the CuSiO3 as intermediates of Cu/SiO2 catalytic reaction accelerated the chemical reaction rate in the CMP process. It was confirmed that the Cu/SiO2 catalytic system generated the intermediate of the catalytic reaction （CuSiO3） in the CMP process through the removal rate of copper film, infrared spectrum and AFM diagrams in different pH conditions. FinalLy it is concluded that the SiO2 sol used in the experiment possesses stable performance; in the CMP process it is directly involved in the chemical reaction by creating the intermediate of the catalytic reaction （CuSiO3） whose yield is proportional to the pH value, which accelerates the removal of copper film.     

Screening self-assembled monolayers as Cu diffusion barriers

Self-assembled monolayers (SAMs) are investigated as potential Cu diffusion barriers for application in back-end-of-line (BEOL) interconnections. A screening of SAMs derived from molecules with different head group (SiCl₃, Si(OCH₃)₃, Si(OCH₃)Cl₂) bonding to the dielectric substrate, chain lengths (n = 3-21) and terminal group (CH₃, Br, CN, NH₂, C₅H₄N and SH) bonding to the Cu overlayer are compared in terms of inhibition of interfacial Cu diffusion and promotion of Cu-SiO₂ adhesion. SAM barrier properties against Cu silicide formation are examined upon annealing from 200 to 400 °C by visual inspection, sheet resistance measurements (Rs) and X-ray Diffraction Spectroscopy (XRD). Cu/SAM/SiO₂ adhesion is evaluated by tape test and four-point probe measurements. Results indicate that NH₂-SAM derived from 3-aminopropyltrimethoxysilane is the most promising for Cu diffusion barrier application. Silicide formation is inhibited to at least 400 °C, essential stability for BEOL integration. However, the 2.9 Gc (J/m²) adhesion of the layer compared with 3.1 Gc (J/m²) on SiO₂ does need improvement.     

Anodic bonding of glass-ceramics to stainless steel coated with intermediate SiO2 layer

The anodic bonding between glass-ceramics and stainless steel (No. 430#) which was coated with SiO₂ layer were investigated. The SiO₂ layers with thickness comprised between 150 and 250 nm were coated on stainless steel surfaces by sol-gel method, the bonding process was achieved at 350 °C and 800 V for 45 min under atmosphere. The micro-topography and the compositions of the bonding interfaces were investigated by XRD, SEM and EDS. The results indicated SiO₂ layers could help the formation of the bonding with glass-ceramics to stainless steel, lithium iron oxide (LiFeO₂) was observed on the surface of glass-ceramics after bonding, and the bonding strength increased with increasing bonding temperature or voltage.     

Nitrogen bonding configurations near the oxynitride/silicon interface after oxynitridation in N2O ambient of a thin SiO2 gate

The identification of the bonding environments and their progressive modifications upon reaching the oxynitride/silicon interface, in a SiO₂/SiO_xN_y/Si structure, have been investigated by means of X-ray photoemission spectroscopy (XPS). The SiO₂ film was grown at 850 °C by means of a mixed dry-steam process, followed by a 60 min, 950 °C furnace oxynitridation in N₂O gas. A depth profile analysis was carried out by a progressive chemical etching procedure, reaching a residual oxide thickness of about 1.2 nm. XPS analysis of the Si 2p and N 1s photoelectron peaks pointed out that the chemistry of the oxynitride layer is a rather complex one. Four different nitrogen bonding environments were envisaged. Both the overall nitrogen content, which rises up to 2.5%, and its bonding configurations are progressively changing while moving towards the silicon interface.     

In-situ cleaning and passivation of oxidized Cu surfaces by alkanethiols and its application to wire bonding

The treatment of oxidized Cu surfaces using an alkanethiol as a reducing agent has been investigated. Exposure to a dilute solution of 1-decanethiol resulted in the complete removal and/or conversion of CuO and subsequent formation of a passivating thiolate film, a so-called self-assembled monolayer (SAM), on the underlying Cu/Cu₂O surface as evidenced by x-ray photoelectron spectroscopy (XPS) analysis. Morphological changes, monitored by scanning electron microscopy (SEM) and atomic force microscopy (AFM), revealed transformation of the rough, porous CuO layer into a comparatively smooth Cu/Cu₂O surface. Experiments performed on integrated circuit back-end-of-line (BEOL) die structures, comprising Cu/SiO₂ bond pads used as substrates for Cu wire bonding, demonstrate the potential application of a thiol-based in-situ cleaning-passivation procedure in microelectronics.     

Microstructure control of copper films by the addition of molybdenum in an advanced metallization process

The effect of annealing on the resistivity, morphology, microstructure, and diffusion characteristics of Cu(Mo)/SiO₂/Si and Ti/Cu(Mo)/SiO₂/Si multilayer films has been investigated in order to deterine the role of Mo. In the case of a Cu(Mo)/SiO₂/Si multilayer, most of the Mo diffused out to the free surface to form MoO₃ at temperatures up to 500 C, and complete dissociation of Mo occurred at higher temperatures. The segregation of Mo to the external surface leads to Mo-free Cu films with extensive grain growth up to 20 times the original grain size and strong (111) texture. In the case of a Ti/Cu(Mo)/SiO₂/Si multilayer, a thin Ti film prohibits Cu agglomeration, out-diffusion of Mo, and diffusion of Cu into SiO₂ at temperatures up to 750 C. Cu(Mo) grain growth was less extensive, but (111) fiber texturing was much stronger than in the case of Cu(Mo)/SiO₂/Si. In the current study, significant changes in microstructure, such as a strong (111) texture and abnormal grain growth, have been obtained by adding Mo to Cu films when the films are annealed.     

The need for multi-scale approaches in Cu/low-k reliability issues

Since recent years, micro-electronic industry changed the basic materials from Al/SiO₂ to Cu/low-k in IC interconnect structure. As a consequence, new reliability issues at device/product level has been discovered, and most of the failure modes have the characteristics of multi-scale: the failure of the μm or nm induces the malfunction of the device/product. Under the pressure of the time-to-market, the industries, universities and research institutes developed numerous multi-scale simulation technologies/tools to analyze the failure mechanism and to achieve the high reliability design with the capability of high volume production and low cost. This paper reviews the multi-scale modeling techniques for reliability and processing issues in Cu/low-k IC back-end structure, from the continuum level to the atomic scale.