Year 2000 — a Sytems Integration challenge

BT, along with virtually every other IT-dependent business worldwide, is tackling a problem which is quite unique and if not corrected could be disastrous. The problem, sometimes known as the Year 2000 bug or millennium time bomb, has been caused by the use of two digits to represent the year in the majority of our systems and applications. The problem is technically not difficult to fix but the volume of changes occurring, and the need to potentially test every system to ensure that it is year 2000 proof, presents unique and challenging difficulties for integration and testing. Why this is the case, what problems need to be addressed, and an overview of some of the proposed integration and test strategies to tackle these problems, is the subject of this paper.     

Pervasive Home Environments

For decades, technologists have been promising the intelligent house. The vision is usually portrayed as a house filled with technology which will do the dweller's bidding and take all domestic drudgery out of their lives. The truly intelligent house is still some way off, but the emergence of broadband, availability of faster, smaller and ever cheaper computing equipment and a variety of wired and wireless network technologies are enabling technologies that bring this vision closer to reality. These technology trends lead to the concept that computing and other smart devices will become pervasive, fully networked and disappear into the infrastructure of the home. People will carry out their tasks unaware of the complexity of the infrastructure that supports their activities in much the same way as people today use mains electricity.This paper introduces these concepts and discusses the technological challenges to be overcome. We present our vision of the pervasive home environment where inhabitants can focus on tasks rather than the technology: I need to create X and send it to Y rather than I need to use this computer and this application which needs access to service A and resource B. Although this sounds simple, the environment needs to understand who I is, and who or what Y is. Appropriate permissions must be in place and resources allocated, if available. The most appropriate interface for the task and user must be determined.The pervasive, intelligent home will make available new ways to access and share information. It will herald new services, such as care and support of people in the home, entertainment, educational and security services. The final part of the paper discusses the commercial opportunities and challenges which must be met, not least the need for industry to agree on open standards and interfaces.     

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults--slow-to-rise and slow-to-fall--are considered as well as delayed transitions from isolating signal state high impedance to binary states 0 and 1 and vice versa. The presented parallel delay fault simulator distinguishes between non-robust, robust and hazard free tests and determines the quality of a test. Experimental results for ISCAS85/89 benchmark circuits are presented as well as results for industrial circuits containing three-state elements.     

Editorial

Future integrated microsystems will benefit significantlyfrom progress in the VLSI field. Two key elements will boostthe implementation of new micro-integrated architectures: progressin batch-manufactured silicon sensors and the introduction ofnew circuit techniques for designing interface circuits. Thesetwo factors will be essential in favoring the transition fromthe present research driven speculations to customer drivenactivities. This paper discusses the key issues in realizingmicrosensors and the most suitable circuit techniques for interfacingand processing their output signals. A number of examples ofintegrated structures will illustrate present problems and possiblesolutions.     

Detection of Defects Using Fault Model Oriented Test Sequences

This paper analyzes the possibilities and limitations of defect detection using fault model oriented test sequences. The analysis is conducted through the example of a short defect considering the static voltage test technique. Firstly, the problem of defect excitation and effect propagation is studied. It is shown that the effect can be either a defective effect or a defect-free effect depending on the value of unpredictable parameters. The concept of Analog Detectability Interval (ADI) is used to represent the range of the unpredictable parameters creating a defective effect. It is demonstrated that the ADIs are pattern dependent. New concepts (Global ADI, Covered ADI) are then proposed to optimize the defect detection taking into account the unpredictable parameters. Finally, the ability of a fault oriented test sequence to detect defect is discussed. In particular, it is shown that the test sequence generated to target the stuck-at faults can reasonably guarantee short defect detection till a limit given by the Analog Detectability Intervals.     

The discrete Einstein relation

In this paper the connection between massM, resistance and commute time for random walks on graphs is further explored, and the relation=2M · is proved. An extension of the result is made to multigraphs, which are an extension of the graph concept where a black box is treated like an edge.     

Network computing

Network computing represents a new computing paradigm in which all information, data and software applications reside on a network and are accessed on demand by users. This approach to computing offers the potential for users to access everything from anywhere, removing the constraints of localised storage of information and applications, and, based on evolving standards, allowing access from a range of information appliances. This paper introduces the basic ideas behind network computing, and examines a range of forms it could take. It describes the current status of commercial network computing approaches, with particular emphasis on the use of the Java language, and examines the associated benefits and technical issues. A prototype BT system, developed using Java client software and CORBA-based middleware, is described.     

Why ‘Current Mode’ Does Not Guarantee Good Performance

It is often said that there is a fundamental difference between current-mode and voltage-mode circuits. This conjecture is discussed in technical and philosophical terms, and it is shown that there is no such performance difference to be found, and that it is not possible to make a clear divide between voltage mode and current mode.And yet performance differences appear in the literature. It is shown that they come from the different design practices of the current-mode and the voltage-mode research groups. The conclusion of this paper is that the practical knowledge of the current-mode research groups should be re-integrated into main-stream IC design, and that all propaganda of the type current-mode is better than voltage-mode should be stopped immediately.     

The Problem with Disruption

Back in January 1995 Clayton Christensen and Joseph Bower wrote an article, Disruptive Technologies: catching the wave, in the Harvard Business Review, in which they argued: No matter the industry, a corporation consists of business units with finite life spans: the technological and market bases of any business will eventually disappear. Good businesses will often be adept at managing a process of incremental improvement, but this kind of incremental change, what they call sustaining technologies, is not the focus of this paper but rather disruptive technologies, which change the rules and leave established businesses with nowhere to go.     

Performance engineering

Failure caused by poor performance renders a system just as useless as failure caused by functional errors, and can be even more expensive to correct. For many years, performance in software systems has been achieved through a fix-it-later approach, using optimisation and tuning techniques. Recent evidence shows that, with the increased use of highly complex, multi-layered, client/server, distributed architectures, these techniques cannot be relied on to deliver even the level of performance required during early operation when workloads are small, let alone over extended periods. This paper describes some of the ways in which performance can be engineered into systems — examples of how these techniques have been used in recent BT projects are included.     

Long-Term Business Modelling Using System Dynamics

This paper presents an overview of the methodology used to model the resource allocation decisions of a research organisation using system dynamics. The resulting model combined the concept of aging chains and co-flows of System Dynamics with conventional spreadsheet analysis, and included representations of staff development and turnover; patent development and licensing revenue; and revenue from other sources. Using the model, senior management were able to evaluate the impact over the coming years of different resource allocation strategies.     

The Supply Chain

One of the most visible examples of ubiquitous computing poised for implementation can be found in the retail industry. Radio frequency identification (RFID) tags are being billed as the replacement for barcoding, the all-pervasive technology which has underpinned supply chains for the past 35 years. The standards allow for up to thirty trillion, trillion, trillion unique addresses, and the ultimate goal is to create an Internet of things in which everyday physical items are networked together. Concerted research effort over the past five years has developed the technology and reduced cost to a point where deployment is now possible. However, the recent heated debate centred on spy chips has highlighted the fact that one person's ubiquitous computing is another person's Big Brother state.     

SRAM-Based FPGAs: Testing the Embedded RAM Modules

This paper addresses the problem of testing the RAM mode of the LUT/RAM modules of configurable SRAM-based Field Programmable Gate Arrays (FPGAs) using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes. Targeting the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the March tests. We also propose a unique test configuration called pseudo shift register for an m × m array of modules. In the proposed configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called shifted MATS++ is described.     

A Kind of Topology Aggregation Algorithm in Hierarchical Wavelength-Routed Optical Networks

In large scale networks composed of several hierarchical subnetworks, topology aggregation is implemented for both scalability and security consideration. However, due to the special characteristic of optical wavelength-routed networks, existing topology aggregation algorithms cannot be applied directly for topology compression. In this paper, we propose a kind of topology aggregation algorithm suitable for hierarchical wavelength-routed optical networks, thereby considering information of residual wavelengths on network links. Basically, our topology aggregation algorithm is based on a transition matrix technique for constructing a full mesh topology and asymmetric star approach for a more compact topology. Simulations with randomly-generated networks show that topology information compression can be achieved with a little loss of its accuracy: the ratio of border node pairs with representation deviation being well below 10%. Results also indicate that the advantage of our algorithm is also behaved on reducing the amount of link-state-advertisement messages and making networks less vulnerable to propagation delay of these messages over communication links. This work is supported by National 863 Program 2003AA122220.     

Corporate multimedia communications

IP-based communications technology will enable people to work in a virtual way and from anywhere in the world. This is already true for data services and applications where IP has become the universal networking technology. Although voice over IP is still a relatively new technology, it has laid the path for new and innovative voice and multimedia communications. This paper looks at new and emerging technology that will tempt business and corporate organisations to adopt IP as a single communications infrastructure for both data and real-time communications.     

SMART — improving customer service

The quality and consistency of customer service offered by telecommunications providers is now a key differentiator in the residential market-place. BT has introduced the SMART customer handling system to provide competitive advantage through worldclass levels of customer service. A large-scale, three-tier client/server system, SMART exploits the existing functionality, data and security mechanisms of an established mainframe system and adds ease-of-use, reduced error rates and a focus on service and selling. The development and deployment experiences of the SMART programme provide lessons in the delivery of large-scale distributed systems in a business-critical environment. The key issues of security, performance, resilience and operability are discussed and the solutions implemented for SMART are presented.     

Unified IP Networks

Corporations are looking to harness the flexibility and ubiquity of IP as a means of automating key business transactions and increasing efficiency. As part of this eRevolution corporate businesses are looking at migrating new applications on to their existing IP infrastructures.Computer/telephony integration and unified messaging are applications that will drive forward the integration of voice and data networks for BT's corporate customers, enabling the use of a flexible, shared IP infrastructure for voice and data.While voice over IP is widely seen as the obvious way forward there are many issues to be resolved before this can deliver the anticipated benefits. This paper provides an insight into the building blocks required to enable the development/deployment of shared infrastructure, for quality of service (QoS) capable, unified, IP network solutions. It highlights the detailed understanding and careful design approach required (particularly in the complex area of network QoS) to engineer custom voice solutions as part of a unified IP network design based on today's technology. Emerging protocols and technology, which may turn the unified network dream into reaility, are identified.     

Design,Implementation and Evaluation of Programmable Handoff in Mobile Networks

We describe the design, implementation and evaluation of a programmable architecture for profiling, composing and deploying handoff services. We argue that future wireless access networks should be built on a foundation of open programmable networking allowing for the dynamic deployment of new mobile and wireless services. Customizing handoff control and mobility management in this manner calls for advances in software and networking technologies in order to respond to specific radio, mobility and service quality requirements of future wireless Internet service providers. Two new handoff services are deployed using programmable mobile networking techniques. First, we describe a multi-handoff access network service, which is capable of simultaneously supporting multiple styles of handoff control over the same physical wireless infrastructure. Second, we discuss a reflective handoff service, which allows programmable mobile devices to freely roam between heterogeneous wireless access networks that support different signaling systems. Evaluation results indicate that programmable handoff architectures are capable of scaling to support a large number of mobile devices while achieving similar performance to that of native signaling systems.     

BT Middleware — software as infrastructure

BT Middleware has been in production use since 1987. Every working day a user population of 60 000 people execute 25 million transactions on systems that generate in excess of 70% of BTs revenues. BT Middleware is installed on 32 production mainframe instances.BT Middleware provides both a development and run-time environment for applications that is controlled and manageable. Application standards can be enforced providing reuse of common code as well as common look and feel user interfaces. The use of BT Middleware has allowed the rapid implementation of leading edge solutions to pressing business requirements and Middleware is evolving to allow BTs operational support systems (OSS) to participate seamlessly in complex distributed architectures.The future for BTs OSS lies in their ability to integrate with new applications developed on open systems platforms. BT Middleware has been evolving to provide the required interconnection capabilities and now supports numerous batch and on-line interfaces via strategic infrastructure products. This paper describes the major Middleware infrastructure components developed and supported by BTs London Software Engineering Centre that allow the companys huge investment in OSS to be exploited in todays environment.     

A Single Clocked Adiabatic Static Logic—A Proposal for Digital Low Power Applications

A modified method to construct adiabatic logic is introduced. Advantages of this circuitry over most of the previous ones is that logic behaves in a static mode. In the present research the applicability of a one-phase power clock was studied. The functionality was guaranteed by having the power source frequency much higher than the logic frequency. The new logic gates do not differ much from any standard CMOS logic gates. The only difference is the use of diodes to form logical 1 and 0 states. The static nature of the introduced logic family makes possible to apply the charge recycling technic to other more complex digital circuits and systems. In measurements 77% power saving was achieved compared to a conventional CMOS logic.