A low-cost graphics and multimedia workstation chip set

With just three VLSI parts, Hewlett-Packard's latest workstation class lets designers optimize performance and cost at the system level. Its Hummingbird microprocessor features two-way superscalar execution incorporating two integer units, a floating-point unit, a 1-Kbyte internal instruction cache, an integrated external cache controller, an integrated memory and I/O controller, plus enhancements for little-endian and multimedia applications. Its Artist graphics controller integrates a graphical user interface accelerator, a frame buffer controller, and a video controller on a single chip     

A low-cost memory remapping scheme for address bus protection

The address sequence on the processor-memory bus can reveal abundant information about the control flow of a program. This can lead to leakage of proprietary algorithms or critical information such as encryption keys. Addresses can be observed by side-channel attacks mounted on remote servers that run sensitive programs but are not under the physical control of the client. Two previously proposed hardware techniques tackled this problem through randomizing address patterns on the bus. In this paper, we examine these attempts and show that they impose great pressure on both the memory and the disk. We propose a lightweight solution to alleviating the pressure with equal security strength. The results show that our technique can reduce the memory traffic by a factor of 10 compared with the prior scheme, while keeping almost the same page fault rate as a baseline system with no security protection.     

低成本聚合物微流控芯片加工技术综述

针对传统微流控芯片加工方法成本高昂、耗时长的问题,近年来出现了多种低成本的微流控芯片加工方法,在聚合物、纸等材料上加工、完成了能够满足其应用需求的微流控芯片。对当前各类基于聚合材料的低成本微流控芯片加工技术进行了梳理和总结,并对未来低成本微流控芯片的发展进行了展望。     

数据采集片上系统动态性能测试的新方法

提出一种新的方法用于高精度数据采集片上系统的动态性能测试。该方法利用高维空间几何矢量投影的思想,将正弦响应信号向由其各次谐波组成的正交基投影来拟合测试数据,以残差的负熵作为拟合结束的判据,使残差最大限度接近白噪声,避免了传统以残差最小为判据的过拟合问题。实验证明了该方法的有效性。     

A survey of memory architecture for 3D chip multi-processors

3D chip multi-processors (3D CMPs) combine the advantages of 3D integration and the parallelism of CMPs, which are emerging as active research topics in VLSI and multi-core computer architecture communities. One significant potentiality of 3D CMPs is to exploit the diversity of integration processes and high volume of vertical TSV bandwidth to mitigate the well-known “Memory Wall” problem. Meanwhile, the 3D integration techniques are under the severe thermal, manufacture yield and cost constraints. Research on 3D stacking memory hierarchy explores the high performance and power/thermal efficient memory architectures for 3D CMPs. The micro-architectures of memories can be designed in the 3D integrated circuit context and integrated into 3D CMPs. This paper surveys the design of memory architectures for 3D CMPs. We summarize current research into two categories: stacking cache-only architectures and stacking main memory architectures for 3D CMPs. The representative works are reviewed and the remaining opportunities and challenges are discussed to guide the future research in this emerging area.     

面向测试优化的片上网络映射算法

针对复杂片上系统(SoC)芯片的片上网络(NoC）映射方案未考虑测试需求的问题,提出了一种面向测试优化的NoC映射算法,兼顾了可测性的提升和映射开销的最小化。该映射方案首先依据特定的测试结构,使用划分算法进行片上系统所有IP核的测试分组,其优化目标为测试时间最短;之后,再基于分组内IP核之间的通信量,应用遗传算法实现NoC映射,其优化目标是在测试优化的基础上实现映射开销最小。通过多个ITC'02测试基准电路进行的实验结果表明:应用该方案后,测试时间平均减少12.67%;与随机任务映射相比,映射代价平均减少24.5%。     

角加速度陀螺仪自动测试系统的设计

针对角加速度陀螺仪生产装配过程中产品性能测试的需要,根据角加速度陀螺仪的工作原理,推导了其简化的工程应用数学模型,采用以数据采集卡为核心的计算机系统,设计了一种用于角加速度陀螺仪静态参数的自动测试系统。试验表明:系统数据处理精度小于0.5%,其测试精度和效率得到明显改善。     

A new method for testing timed systems

Devising formal techniques and methods that can automatically generate test suites for timed systems has remained a challenge. In this paper Timed Input/Output Automata (TIOA) are used as a formal specification model for timed systems. This work proposes and proves the correctness of a new and more general discretization method that can be used to obtain grid automata corresponding to specification TIOA, using almost any granularity of interest. Such flexibility to find a suitable granularity opens the possibility for a more compact construction of grid automata. It is also shown how test purposes can be used together with the specification TIOA in order to generate grid automata that capture the behavior of both the specification and the test purpose. From such grid automata one can algorithmically extract test suites that can be used to verify whether given implementations adhere to the specification and reflect the properties modeled using the test purposes. Copyright © 2011 John Wiley & Sons, Ltd.     

HF-contact elements for testing and multi chip module applications

In this paper a platform based on the composite IC concept (Semiconductor Industry Association in The NTRS, pp 63, 1994) will be presented that is optimized for high frequency applications. Key elements of the platform are coplanar waveguides and micro springs that are processed using MEMS technologies. Rotation symmetric micro springs with diameters between 500 and 125 μm with different widths and thicknesses were designed, simulated and fabricated. The best mechanical properties were obtained from springs with a diameter of 250 μm. They were made by electroplating of a nickel–tungsten-alloy. FEM simulation of the high frequency performance shows a good performance up to frequencies of 10 GHz.     

HF-contact elements for testing and multi chip module applications

In this paper a platform based on the composite IC concept (Semiconductor Industry Association in The NTRS, pp 63, 1994) will be presented that is optimized for high frequency applications. Key elements of the platform are coplanar waveguides and micro springs that are processed using MEMS technologies. Rotation symmetric micro springs with diameters between 500 and 125 μm with different widths and thicknesses were designed, simulated and fabricated. The best mechanical properties were obtained from springs with a diameter of 250 μm. They were made by electroplating of a nickel–tungsten-alloy. FEM simulation of the high frequency performance shows a good performance up to frequencies of 10 GHz.

     

Content-based image retrieval algorithm acceleration in a low-cost reconfigurable FPGA cluster

The SMILE project main aim is to build an efficient low-cost cluster based on FPGA boards in order to take advantage of its reconfigurable capabilities. This paper shows the cluster architecture, describing: the SMILE nodes, the high-speed communication network for the nodes and the software environment. Simulating complex applications can be very hard, therefore a SystemC model of the whole system has been designed to simplify this task and provide error-free downloading and execution of the applications in the cluster. The hardware–software co-design process involved in the architecture and SystemC design is presented as well. The SMILE cluster functionality is tested executing a real complex Content-Based Information Retrieval (CBIR) parallel application and the performance of the cluster is compared (time, power and cost) with a traditional cluster approach.     

一种新的角加速度估计方法及其应用

首先提出了一种新的基于卡尔曼滤波及牛顿预测的角加速度估计方法,在已知电机驱动系统位置信息的情况下,利用卡尔曼滤波实时估计系统的角加速度;同时采用牛顿预测方法解决估计算法的滞后问题,进一步提高了估计加速度的响应频带．以此为基础,本文进一步分析了利用估计加速度进行反馈控制以增强系统对外扰动的鲁棒性问题,提出了加速度反馈控制策略的设计准则并分析了稳定性．在一个直接驱动机器人关节上针对上述加速度估计及控制方法进行了实验研究:将估计加速度的实验结果与实测加速度(利用加速度计)的实验结果进行了比较分析,从而定量地揭示出估计加速度及其反馈控制在实际系统中的可行性及有效性．     

一种新型加速度传感器性能测试系统

介绍了一种新型的加速度传感器性能测试系统,它由计算机分析平台、数据采集子系统、数据交换子系统和直流调速子系统四个部分组成。系统通过串口控制直流调速系统改变转盘的速度从而获得变化的加速度曲线,再通过射频芯片nRF2401进行相应的数据采集。上位机采用LabVIEW开发,其他3个子系统采用PIC单片机作为主控芯片实现。     

Model-based testing leveraged for automated web tests

Software Quality Journal - Agile methods and their practices have fostered the widespread presence of automated test cases. Such test cases have been successfully and extensively adopted to test...     

Design and testing of a low-cost robotic wheelchair prototype

Many people who are mobility impaired are, for a variety of reasons, incapable of using an ordinary wheelchair. In some instances, a power wheelchair also cannot be used, usually because of the difficulty the person has in controlling it (often due to additional disabilities). This paper describes two low-cost robotic wheelchair prototypes that assist the operator of the chair in avoiding obstacles, going to pre-designated places, and maneuvering through doorways and other narrow or crowded areas. These systems can be interfaced to a variety of input devices, and can give the operator as much or as little moment by moment control of the chair as they wish. This paper describes both systems, the evolution from one system to another, and the lessons learned.     

一种新型三维方向和加速度传感器

根据流动的水银球与裸置的环形电阻丝连接形成回路,返回不同位置对应电信号的原理,设计了一种新型的探测运动物体一维方向和加速度大小方向的传感器。由3只一维方向传感器相互垂直构成三维传感器,可探测物体三维运动信息;2只一维传感器返回的电信号构成数组,与测试物体的运动信息一一对应,数据经过处理,可获运动物体的三维方向和加速度大小方向信息。     

新型水中油在线检测系统的设计

介绍了荧光分析法的原理并基于此原理设计了水中微量油在线检测仪.本文重点介绍了此仪器的控制系统的设计,通过采用信号放大器、滤波器及AD转换器实现了微弱信号的高精度放大.结合单片机和特定的程序流程,使仪器在水中微量油在线检测和自动控制方面得到了很好的应用.     

A new memory allocation method for shared memory multiprocessors with large virtual address space

This paper proposes a new memory allocation method for shared memory multiprocessors with large virtual address spaces. An evaluation of its performance is also presented. For effective use of shared memory multiprocessors, it is important that no processor's execution is blocked. If several processors simultaneously access a shared variable, their processes are blocked and access to the variable is serialized. Thus, frequent access to shared variables reduces the parallelism. In particular, the parallelism is significantly reduced when a special shared variable – the ‘allocation pointer’ – is frequently accessed in the dynamic object allocation by an application program. In this paper, we propose a new method for allocating physical memory pages where the allocation pointer is monotonically increased in the virtual address space in contrast to the conventional method. This allows the critical sections for access to the allocation pointer to be executed effectively and atomically by using the fetch-and-add primitive. Our method improves the application program's parallelism by access to the allocation pointer with considerably short blocking time to the process. © 1997 John Wiley & Sons, Ltd.