Novel unity power factor circuits using zero-vector control forsingle-phase input systems

This paper proposes two novel circuits which realize a unity input power factor single-phase to three-phase converter with a motor load. The power supply is connected to the neutral point of the motor, and the three-phase inverter is controlled to act also as a virtual AC/DC power converter leg. This virtual leg is controlled by zero vectors of the three-phase inverter. The main features of these circuits are as follows: no inductive components are required; a reduction in the number of switching devices compared with conventional topologies; and motor current increases because converter input current also flows through the motor windings. A full-bridge converter can be built using the same number of switching devices as the conventional half bridge and with no need for a capacitive leg with an accessible neutral point. In this paper, the proposed full-bridge-type circuit is experimentally tested using a 750-W induction motor as load     

基于LM5175的Buck-Boost车用开关电源设计

针对一款应用于新能源汽车的电机驱动控制器,设计了一种基于TI公司的电源芯片LM5175的4开关Buck-Boost开关电源。根据车载情况对电源的要求确定输入输出电压范围、电流范围、开关频率,进而选择合理的输入输出电容、电感、MOSFET等元器件,完成了电源芯片外围电路的搭建。绘制开关电源系统的伯德图对开关电源的工作稳定性进行分析,优化开关频率等参数。通过相同负载不同输入电压和相同输入电压不同负载的两组实验验证,开关电源可稳定输出目标电压以及开关电源效率。     

The development of a closed-form expression for the input impedance of power-return plane structures

In multilayer printed circuit boards, the noise on the power bus is influenced by the impedance between the power and ground planes. Power-bus noise estimates require an accurate estimate of the power-bus input impedance. This paper develops a closed-form estimate of the input impedance for circular power-return plane structures. When the structure is lossy (e.g., boards employing embedded capacitance or densely populated boards), the energy reflected from the board edge does not significantly affect the input impedance. In general, the expressions developed here for circular structures can be used to estimate the impedance of lossy power-return plane structures of any shape.     

高性能栅压自举开关的设计

对模数转换器中的传统开关电路的导通电阻进行了详细的理论分析,提出了一种互补型栅压自举开关电路.该电路结构相比于传统开关,通过少量的功耗代价换取了更优的频域性能,在不同工艺角下具有更好的鲁棒性,适用于先进工艺下的低电压工作环境.互补型栅压自举开关电路采用28 nm工艺设计,在1V的电源电压下,对800fF的负载电容进行速率为800 MS/s的采样,在低频输入下(181.25 MHz)实现的无杂散动态范围(SFDR)为89 dB,四倍奈奎斯特输入频率下(1 556 MHz)实现的SFDR为65 dB,开关电路面积为80 μm×20 μm.     

A compact reconfigurable counter memory for spiking pixels

In this letter, a compact reconfigurable counter memory (RCM) is proposed for spiking pixels. In contrast to conventional in-pixel counter circuitry, the proposed RCM does not rely on a flip-flop-based circuit but instead uses a very novel circuit structure that combines a combinational incrementer together with static and dynamic memory cells. The proposed RCM provides counting as well as in-pixel storage functionalities allowing for intermediate readout of digital pixel values. Reported experimental results validate the novel concept of RCM-based spiking pixel in AMIS 0.35-/spl mu/m CMOS technology. The proposed pixel architecture is inherently insensitive to power supply voltage scaling and is thus well suited to submicrometer CMOS processes.     

A Low Power Correlator for CDMA Wireless Systems

The complex valued matched filter correlators consume maximum power in the DS/SS CDMA receivers. These correlators accumulate 1024 samples lying in the range –7 to +7. This accumulation needs 3 data bits, 1 sign bit and 10 extra bits for overflow. Hence, the correlator can be implemented as a cascade of 4-bit full adder and a 10-bit incrementer. As a ripple carry adder (RCA) consumes the least power among all the existing adder architectures, we have implemented the 4-bit adder as a RCA. Previous incrementers were implemented as ripple counters. In this paper we propose a novel incrementer which is faster than a ripple counter based incrementer. Hence, it can be operated at a reduced voltage resulting in considerable power reduction. The incrementer is implemented using multiplexers, AND gates and TSPC registers. The ripple-counter correlator and the proposed incrementer correlator were laid out in MAGIC using 0.5 CMOS technology followed by power estimation using HSPICE. It is shown that the proposed architecture requires 50% less power than a ripple counter based design.     

11.GHz GaAs Power MESFET Load-Pull Measurements Utilizing a New Method of Determining Tuner Y Parameters

A Ioad-pull technique utilizing a new method of determining tuner Y parameters is proposed for huge-signal characterization of microwave power transistors. Large-signal input-output transfer characteristics of an active circuit containing a GaAs FET and an input matching circuit are measured by inserting a microstrip tuner between the active circuit output drain terminal and the 50-Omega load. The microstrip-tuner Y parameters are determined by comparing the dc bias-dependent small-signal S parameter S/sub 22/ of the active circuit and that of the circuit which contains the active circuit and microstrip tuner. The reflection coefficient presented to the active circuit output drain terminal is derived from tuner Y parameters. Optimal load impedances for output power, obtained with this new Ioad-pull technique, are used to design X-band GaAs FET power amplifiers. An 11-GHz power amplifier with a 3000-mu m gate-width FET chip delivers 1-W microwave power output with 4-dB gain in the 500-MHz band.     

Unity Power-Factor Controller for a Synchronous Motor

A simple electronic controller for maintaining the input power factor of a synchronous motor, close to unity, irrespective of load is described. The controller is applicable to a synchronous motor with an additional quadrature field winding. An electronic feedback circuit detects the armature current and causes variation of firing angle of a controlled bridge rectifier which provides the excitation for the quadrature field winding. The induced EMF due to the quadrature field winding cancels out the synchronous reactance voltage drop, thereby keeping the power factor close to unity without the need of changing the main field excitation. A prototype controller is constructed and experimental results are presented.     

Input filter design for power factor correction circuits

The issues involved in the design of power factor correction circuit input filters are significantly different from those involved in the design of input filters for DC-DC power converters. In many cases, the EMI and power factor requirements are impossible to meet using the existing filtering technology. This paper proposes the use of high-order elliptic filters to achieve the required EMI attenuation and power factor. The new input filter technology provides a significant filter size reduction over the standard filter designs, minimizes the filter-power converter interaction, and maintains a good converter power factor. New active and passive filter damping methods that guarantee optimal filter pole damping, while virtually eliminating damping resistor power dissipation, are proposed. The filter design procedure that makes possible a simple and fast design of filters with an arbitrary number of stages is also presented     

Regenerative medium-voltage AC drive based on a multicell arrangement with reduced energy storage requirements

Multicell power circuit topologies have proved to be an effective alternative to medium-voltage ac drives. The main advantage is the improved power quality at both the ac system and the motor sides. However, several drawbacks are present in these configurations, such as a lack of sustained regenerative operating mode, uncontrolled input reactive power, and a large second current harmonic that is injected by the load into the dc link of each cell, which leads to a bulky electrolytic capacitor. This paper proposes to replace the input diode-based front-end rectifier with an active front-end rectifier in all cells of the topology and a novel control strategy in order to overcome the aforementioned drawbacks. In fact, the active front-end rectifier allows the topology to regenerate and the control strategy handles the reactive input power and reduces the large second current harmonic from the dc-link capacitor, thus reducing its size. These features are achieved without any penalties in the quality of both the ac input current and the motor voltage waveforms. Experimental results confirm the theoretical considerations.     

一种具有采样带宽补偿的高性能采样/保持电路

针对中频采样模数装换器中的宽带采样/保持电路,提出了一种新颖的电荷交换补偿（CEC）技术.该技术通过消除采样开关有限导通电阻的影响,补偿了采样带宽,并避免了时钟馈通和电荷注入的加剧.同时设计了具有AB类输出的低功耗两级运放,在1.8V电源下为该采样/保持提供了3V峰-峰值的输入范围.该采样/保持电路在100Ms/s的采样率下,对于200MHz输入信号达到了94dB的无杂散动态范围.在5.5pF的负载下,功耗仅为26mW.     

一种具有采样带宽补偿的高性能采样/保持电路

针对中频采样模数装换器中的宽带采样/保持电路,提出了一种新颖的电荷交换补偿(CEC)技术.该技术通过消除采样开关有限导通电阻的影响,补偿了采样带宽,并避免了时钟馈通和电荷注入的加剧.同时设计了具有AB类输出的低功耗两级运放,在1.8V电源下为该采样/保持提供了3V峰-峰值的输入范围.该采样/保持电路在100Ms/s的采样率下,对于200MHz输入信号达到了94dB的无杂散动态范围.在5.5pF的负载下,功耗仅为26mW.     

Analysis of power delivery network constructed by irregular-shaped power/ground plane including densely populated via-hole

The high speed and low power trend has imposed more and more importance on the design of the power distribution network (PDN) using multilayer printed circuit boards (PCBs) for modern microelectronic packages. This paper presents a fast and efficient analysis methodology in frequency domain for the design of a PDN with a power/ground plane pair, which considers the effect of irregular shape of the power/ground plane and densely populated via-holes. The presented method uses parallel-plate transmission line theory with equivalent circuit model of unit-cell grid considering three-dimensional geometric boundary conditions. Characteristics of PDNs implemented by perforated planes including a densely populated via-hole structure is quantitatively determined based on full-wave analysis using the finite-difference time-domain (FDTD) periodic structure modeling method and full-wave electromagnetic field solver. Using a circuit simulator such as popularly used SPICE and equivalent circuit models for via-hole structure and perforations, the authors have analyzed input-impedance of the power/ground plane pair. Since the presented method gives an accurate and fast solution, it is very useful for an early design of multilayer PCBs.     

2.5W低噪声CMOSD类音频功放设计

提出了一种基于0.5μm5VCMOS工艺的低噪声PWM调制D类音频功率放大器。该放大器在5V电源电压下以全桥方式可以驱动4Ω负载输出2.5W功率;转换效率等于87%,信噪比达94dB(负载8Ω,输出功率1W);THD+N仅0.05%(负载4Ω,输出功率1W);PSRR为68dB(频率1kHz)。分析了整体电路结构及其线性化模型,并着重介绍了高性能前置斩波稳定运算放大器(开环增益117dB,等效输入噪声16μV.Hz-1/2),线性三角波振荡电路(斜率偏差仅±0.2%)和功率器件、驱动电路的设计。最后给出了D类放大器的测试结果。     

Optimal selection of motor and gearhead in mechatronic applications

A method for the selection of motor and gearhead in mechatronic applications is proposed. The method is applicable to any kind of load and helps to find the optimal motor gearhead combination with respect to output torque, peak power, mass/size and/or cost. The input to the method is the load cycle and component data on candidate motors and gearheads. Output is a set of graphs of all motor/gear ratio combinations that can drive the given load. From these graphs it is easy to read out the peak power, motor torque and energy efficiency for all feasible motor/gear ratio combinations.     

DC/DC模块输入端电压反加后的影响分析

在航天等空间产品中使用的分布式供电系统中,总体电路一般只提供27~30 V的直流一次电源,各单机产品大多采用DC/DC模块将该一次电源转换为所需的二次电源,并实现一次地与二次地的隔离。分析了INTERPOINT公司的DC/DC模块的输入端反接后,输入电压对DC/DC模块、电源保护滤波电路及负载的影响,通过仿真与验证试验,得出电源模块输入端反接后单机产品中电源保护电路发生作用,对产品中负载无影响,可以继续使用。电源模块失效分析对航天产品中电源模块中出现类似的故障后的处理提供了参考。     

An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.     

High-speed driving scheme and compact high-speed low-power rail-to-rail class-B buffer amplifier for LCD applications

A high-speed driving scheme and a compact high-speed low-power rail-to-rail class-B buffer amplifier, which are suitable for small- and large-size liquid crystal display applications, are proposed. The driving scheme incorporates two output driving stages in which the output of the first output driving stage is connected to the inverting input and that of the second driving stage is connected to the capacitive load. A compensation resistor is connected between the two output stages for stability. The second output stage is used to improve the slew rate and the settling time. The buffer draws little current while static but has a large driving capability while transient. The circuit achieves the large driving capability by employing simple comparators to sense the transients of the input to turn on the output stages, which are statically off in the stable state. This increases the speed of the circuit without increasing static power consumption too much. A rail-to-rail folded-cascode differential amplifier is used to amplify the input signal difference and supply the bias voltages for the second stage. An experimental prototype output buffer implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the circuit draws only 7-/spl mu/A static current and exhibits the settling times of 2.7 /spl mu/s for rising and 2.9 /spl mu/s for falling edges for a voltage swing of 3.3 V under a 600-pF capacitance load with a power supply of 3.3 V. The active area of this buffer is only 46.5/spl times/57/spl mu/m/sup 2/.     

Design of high-performance CMOS priority encoders andincrementer/decrementers using multilevel lookahead and multilevelfolding techniques

Lookahead signals to form the multilevel folding architecture for priority-encoding-based designs was used to improve the performance to the order of O(log N). Analysis showed that both the multilevel lookahead and the multilevel folding techniques could be easily merged and implemented in the dynamic CMOS circuits. For the 256-bit priority encoder, the new design adopting all the proposed techniques can achieve nearly ten times performance while spending nearly half the power consumption as compared to the conventional design, utilizing only a simple lookahead structure. For the 64-bit incrementer/decrementer, the new design adopting all the proposed techniques requires less than one-third delay time as compared to a high-speed carry-select adder (CSA)-based incrementer/decrementer. The power consumption evaluated at the maximum operating frequency and the transistor count of the new incrementer/decrementer are also reduced to 67% and 35%, respectively, as compared to the CSA-based design. The measurement results indicate that the proposed 256-bit priority encoder and the proposed 64-bit incrementer/decrementer can operate up to 116 and 139 MHz, respectively, when they are designed based on a 0.6-μm CMOS technology     

A Printed Circuit Balun for Use with Spiral Antennas

A novel printed circuit balun is described which is particularly well suited to applications where space is at a premium. The design utilizes unshielded strip transmission line, but is readily adaptable to all of the common printed circuit transmission line techniques. When the balun is housed within the cavity of a spiral antenna, boresight error is virtually eliminated, ellipticity ratios of less than 2 db are maintained over an azimuth angle greater than /spl plusmn/ 60/spl deg/, and the input standing-wave ratio is less than 2:1 over an octave frequency range. Experimental results are given and additional applications are described.