Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO₂ gate dielectric, where the gate is also separated from the source contact with a 100-nm SiO_x, spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiN_x, gate dielectrics.     

垂直纳米线晶体管的制备技术

对目前垂直纳米线晶体管的制备技术进行了综述.首先根据器件结构取向介绍了纳米线晶体管的分类,即水平纳米线晶体管和垂直纳米线晶体管,比较了这两类不同结构晶体管的优缺点,阐述了垂直纳米线晶体管的优势及其潜在应用价值.重点介绍了两种主流的垂直纳米线晶体管的制造方法,即自下而上方法和自上而下方法,自上而下方法则又分为后栅工艺和先栅工艺.随后详细比较了它们之间的不同.最后,对垂直纳米线晶体管制造过程中的工艺挑战进行了分析,提出了几种可行的解决方案,并预测了垂直纳米线晶体管未来的发展趋势,特别是在低功耗器件及3D存储器等方面的发展走向.     

High-Frequency ZnO Thin-Film Transistors on Si Substrates

Record microwave frequency performance was achieved with nanocrystalline ZnO thin-film transistors fabricated on Si substrates. Devices with 1.2-$muhbox{m}$ gate lengths and Au-based gate metals had current and power gain cutoff frequencies of $f_{T} = hbox{2.45} hbox{GHz}$ and $f_{max} = hbox{7.45} hbox{GHz}$ , respectively. Same devices had drain–current on/off ratios of $hbox{5} times hbox{10}^{10}$, exhibited no hysteresis effects and could be operated at a current density of 348 mA/mm. The microwave performances of devices with 1.2- and 2.1- $muhbox{m}$ gate lengths and 50- and 100-$muhbox{m}$ gate widths were compared.      

Symmetric and Excellent Scaling Behavior in Ultrathin n- and p-Type Gate-All-Around InAs Nanowire Transistors

Complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) are the key component of a chip. Bulk indium arsenide (InAs) owns nearly 30 times higher electron mobility µ_e than silicon but suffers from a much lower hole mobility µ_h (µ_e/µ_h = 80), thus unsuited to CMOS application with a single material. Through the accurate ab initio quantum-transport simulations, the performance gap between the NMOS and PMOS is significantly narrowed is predicted and even vanished in the sub-2-nm-diameter gate-all-around (GAA) InAs nanowires (NW) FETs because the inversion of the light and heavy hole bands occurs when the diameter is shorter than 3 nm. It is further proposed several feasible strategies for further improving the performance symmetry in the GAA InAs NWFETs. Short-channel effects are effectively depressed in the symmetric n- and p-type GAA InAs NWFETs till the gate length is scaled down to 2 nm according to the standards of the International Technology Roadmap for Semiconductors. Therefore, the ultrasmall GAA InAs NWFETs possess tremendous prospects in CMOS integrated circuits.     

ZnO Nanowire Field-Effect Transistors

Owing to the extraordinary properties and prominent applications in emerging nanoelectronics, ZnO nanowire has attracted tremendous research effort. This paper provides an introductory overview, covering topics ranging from basic nanowire synthesis and fundamental electrical properties to device characteristics based on field-effect transistor configuration.      

Scaling of Nanowire Transistors

This paper considers the scaling of nanowire transistors to 10-nm gate lengths and below. The 2-D scale length theory for a cylindrical surrounding-gate MOSFET is reviewed first, yielding a general guideline between the gate length and the nanowire size for acceptable short-channel effects. Quantum confinement of electrons in the nanowire is discussed next. It gives rise to a ground-state energy and, therefore, a threshold voltage dependent on the radius of the nanowire. The scaling limit of nanowire transistors hinges on how precise the nanowire size can be controlled. The performance limit of a nanowire transistor is then assessed by applying a ballistic current model. Key issues such as the density of states of the nanowire material are discussed. Comparisons are made between the model results and the published experimental data of nanowire devices.      

2D TMD Channel Transistors with ZnO Nanowire Gate for Extended Nonvolatile Memory Applications

2D transition metal dichalcogenides (TMDs) have been extensively studied due to their excellent physical properties. Mixed dimensional devices including 2D materials have also been studied, motivated by the possibility of any synergy effect from unique structures. However, only few such studies have been conducted. Here, semiconducting 1D ZnO nanowires are used as thin gate material to support 2D TMD field effect transistors (FETs) and 2D stack‐based interface trap nonvolatile memory. For the trap memory, deep level electron traps formed at the first MoS₂/second MoS₂ stack interface are exploited, since the first MoS₂ is treated in an atomic layer deposition chamber for a short while. On the one hand, a complementary inverter type memory device can also be achieved using a long single ZnO wire as a common gate to simultaneously support both n‐ and p‐channel TMD FETs. In addition, it is found that the semiconducting ZnO nanowire itself operates as an n‐type channel when the TMD materials can become a top‐gate to charge the ZnO channel. It means that 2D (bottom gated) and 1D channel (top gated) FETs are respectively operational in a single device structure. The 1D–2D mixed devices seem deserving broad attention in both aspects of novelty and functionality.     

Heterostructure Barriers in Wrap Gated Nanowire FETs

We present results on the effects of inserting a heterostructure barrier along the channel of vertical wrapped insulator-gate field-effect transistors (WIGFETs). Two sets of devices were fabricated, one InAs WIGFET and one with a 50-nm-long $hbox{InAs}_{0.8}hbox{P}_{0.2}$ segment in the channel. This addition of P induces a barrier in the conduction band of 130 mV, measured from the Fermi-level. The barrier blocks the diffusion current through the channel and reduces the feedback gating of holes created from band-to-band tunneling, resulting in improvements in on/off current ratio, and subthreshold characteristics. The heterosegment also induces a shift in the threshold voltage and provides an additional parameter for threshold voltage control in nanowire III–V MOSFETs.      

Characteristics and Fluctuation of Negative Bias Temperature Instability in Si Nanowire Field-Effect Transistors

In this letter, negative bias temperature instability (NBTI) in silicon nanowire field-effect transistors (SNWFETs) is investigated and found to exhibit some new characteristics that are probably due to the structural nature of nanowires. In long-channel SNWFETs, a fast degradation and a quick saturation of NBTI are observed and discussed. In short-channel SNWFETs, a large fluctuation of NBTI is observed, which mainly originates from the ultrasmall gate areas of the short-channel SNWFETs and the statistical nature of randomly trapped charges in the oxide and at the Si/SiO₂ interface. Techniques to suppress the fluctuation and characterize the intrinsic NBTI in ultrasmall SNWFETs are proposed and discussed. A recently developed online gate current method is demonstrated, which effectively alleviates this NBTI fluctuation in SNWFETs.     

Experimental Investigations on Carrier Transport in Si Nanowire Transistors: Ballistic Efficiency and Apparent Mobility

As devices continue scaling down into nanometer regime, carrier transport becomes critically important. In this paper, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top–down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is adopted, which takes into account the impact of temperature dependence of parasitic source resistance in SNWTs. The highest ballistic efficiency at room temperature is observed in sub-40-nm n-channel SNWTs due to their quasi-1-D carrier transport. The apparent mobility of GAA SNWTs are also extracted, showing their close proximity to the ballistic limit as shrinking the gate length, which can be explained by Shur's model. The physical understanding of the apparent mobility in SNWTs is also discussed using flux's scattering matrix method.      

Dual-Gate Multiple-Channel ZnO Nanowire Transistors

We report on conventional multichannel ZnO nanowire field-effect transistors (FETs) operating in one device in a dual-gate mode. Our FETs were prepared by assembling ZnO nanowires on a Si substrate using an optimized dielectrophoresis technique with bottom-gate and top-gate FET structures. We observed that the enhancement of the electrical characteristics in FETs with top-gate mode operation results from a thinner gate oxide and top-gate geometry compared with FETs with bottom-gate mode operation. It was also verified that surface passivation strongly affected the electrical performance of ZnO nanowire FETs.     

非晶硅薄膜晶体管基于表面势的栅电容模型

基于Lambert W函数,推导出非晶硅薄膜晶体管表面势的解析解,并将其与泊松方程的数值解进行对比.结果显示:该求解大大提高了计算效率,且精确度极高.基于有效温度近似,并利用所求解到的表面势,建立器件的栅电容模型.该模型可连续、准确地描述a-Si:H TFT在所有工作区的动态特性.最后,将模型结果与实验数据进行了对比,两者拟合良好.     

Quasi-Ballistic Transport in Nanowire Field-Effect Transistors

In this paper, we investigate quasi-ballistic transport in nanowire field-effect transistors (NW-FETs). In order to do so, we address the 1-D Boltzmann transport equation (BTE) and find its exact analytical solution for any potential profile with the constraint of dominant elastic scattering. A simulation code implementing a self-consistent SchrÖdinger–Poisson solver in the transverse direction and the present BTE solution in the longitudinal direction is worked out, providing the $I$–$V$ characteristics of the NW-FET. Such characteristics are compared with those computed using a numerical BTE solver accounting for both inelastic and elastic collisions, and the two of them turn out to agree very nicely. From this comparison, it may be concluded that inelastic scattering plays a minor role for small-diameter FETs with device lengths in the decananometer range. Next, a methodology for the calculation of the transmission and backscattering coefficients is worked out for the first time starting from the scattering probabilities. The aforementioned coefficients turn out to be functions of the ratio between the carrier transit time and a suitably averaged momentum-relaxation time. Therefore, one of the main conclusions of this paper is that, so long as inelastic collisions are negligible, the so-called $kT$ layer plays no role in 1-D quasi-ballistic carrier transport.      

Microwave Performance of AlGaN/GaN High-Electron-Mobility Transistors on Si/SiO2/Poly-SiC Substrates

The radiofrequency (RF) performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) grown by molecular beam epitaxy (MBE) on Si-on-poly-SiC (SopSiC) substrates formed by the Smart-Cut^TM process is reported. This provides a low-cost, high-thermal-conductivity substrate for power applications. HEMTs with a 0.5 μm gate length show cutoff frequencies (f _T) of 18 to 27 GHz for gate-to-drain distances of 3 to 32 μm and a maximum frequency of oscillation (f _max) of 43 to 47 GHz. The f _max values are slightly lower than comparable devices on sapphire, SiC or Si alone. This approach looks promising for applications requiring cheap large-area substrates and better thermal management than provided by pure Si substrates alone.     

Si纳米线场效应晶体管研究进展

从Si纳米线场效应晶体管(SiNWFET)的结构原理、Si纳米线的制作工艺以及器件电学性能的改善措施三个方面介绍了SiNWFET的研究进展。通过分析SiNWFET的漏极电压对沟道电势的影响,表明SiNWFET自身的细沟道和围栅结构对于改善亚阈值特性和抑制短沟道效应起着关键作用。针对Si纳米线的制备,介绍了光刻、刻蚀与热氧化等自上而下的方法和气-液-固生长这种自下而上的方法。分析了SiNWFET的电学性能,探讨了为改善电学性能而进行的器件结构和工艺的改进,包括选择沟道取向,采用多条纳米线、应变纳米线或新材料作为沟道以及减小源-漏接触电阻等措施。最后对SiNWFET所面临的挑战和前景作了展望。     

Radio-Frequency Operation of Transparent Nanowire Thin-Film Transistors

In this letter, radio-frequency characterization of fully transparent thin-film transistors (TFTs) based on chemically synthesized nanowires (NWs) has been carried out. The NW TFTs show current-gain cutoff frequency $f_{T}$ of 109 MHz and power-gain cutoff frequency $f_{max}$ of 286 MHz. The TFTs were fabricated on glass substrates using aligned $hbox{SnO}_{2}$ NWs as the transistor channel and sputtered indium–tin–oxide films as the source–drain and gate electrodes. Besides exhibiting $≫$ 100-MHz operation frequencies, the transparent NW TFTs show a narrow distribution of performance metrics among different devices. These results suggest the NW-TFT approach may be promising for high-speed transparent and flexible integrated circuits fabricated on diverse substrates.      

Modeling and Fabrication of ZnO Nanowire Transistors

ZnO is attracting attention for application in transparent nanowire (NW) transistors because of the ease of synthesis of ZnO nanostructures, their good transport properties, the availability of heterostructures, and the possibility for optoelectronic integration. A variety of both top and bottom gate n-type ZnO NW transistors have been reported, showing generally high on/off ratios $(hbox{10}^{4} - hbox{10}^{7})$, subthreshold voltage swings of 130–300 mV/dec, and excellent drain–current saturation. Much higher electron mobilities and improved device stability are found when surface passivation is employed, pointing to the importance of controlling surface charge density. Simulations show that defects such as grain boundaries lead to a decrease of drain current. While the dc characteristics of such devices are generally reasonable, there have been no reports of the RF or high-speed switching performance. Additional work is needed on optimized gate dielectrics, reliability, and functionality of ZnO NW transistors.      

Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness

A new method is proposed and successfully demonstrated for the fabrication of polycrystalline silicon (poly-Si) nanowire (NW) transistors with rectangular-shaped NW channels and two independent gates. The two independently controllable gates allow higher flexibility in device operation and provide a unique insight into the conduction mechanism of the NW device. Our results indicate that dramatic performance enhancement is feasible when the thickness of the NW channel is sufficiently thin, and the two conduction channels in the NW structure are operating simultaneously.      

Heterostructures with InAs/AlAs Quantum Wells and Quantum Dots Grown on GaAs/Si Hybrid Substrates

Semiconductors - Heterostructures with InAs/AlAs quantum dots are grown on GaAs/Si hybrid substrates. The experimentally observed low-temperature (5–80 K) photoluminescence spectra of...     

GAT双极晶体管的高频高压兼容特性

建立了 GAT器件集电结耗尽层电位分布和电场分布的二维解析模型 ,定量研究了 GAT的栅屏蔽效应和 GAT的基区穿通电压 VPI,并且解释了该器件实现高频率与高电压兼容的实验结果 .该模型可供优化设计双极型高频、高压、低饱和压降功率器件参考