Dead‐time elimination SVPWM of six‐leg inverter

We present a six‐leg voltage source inverter (VSI) with a single DC link to feed a three‐phase inductive load. The space vector pulse width modulation (SVPWM) of the six‐leg inverter is studied in detail. The novel switching strategy in one sampling period for H bridge is proposed to avoid the 180° phase shift of the PWM signals for upper and lower side switches. Based on the novel switching strategy, a dead‐time elimination SVPWM is proposed, which can be easily implemented on a digital signal processor. Experimental results are presented to demonstrate the validity and features of the proposed novel SVPWM. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A Method for Reducing the Dead‐Time Voltage and Impedance Voltage in a Series Voltage Compensator

Many research groups are developing series voltage compensators. In a series converter, since a transformer is used in series in the power system, the power system current flows into the voltage source inverter through the transformer. The inverter current, which is determined by the transformation ratio, gives rise to an error voltage that consists of a dead‐time voltage and an impedance voltage. The error voltage is generated even when the reference voltage is zero. This paper describes the mechanism by which the error voltage occurs and proposes a method for reducing the error voltage. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 186(3): 85–93, 2014; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.22333     

A New Control Method of Suppressing the DC‐Capacitor Voltage Ripple Caused by Third‐Order Harmonic Compensation in Three‐Phase Active Power Filters

This paper proposes a new control method suitable for active power filters, which can reduce the dc capacitor voltage ripple associated with the third‐order harmonic current compensation. The proposed method superimposes a negative‐sequence fundamental current on the compensating current to cancel out the active power ripple caused by the third‐order harmonic current. As a result, the proposed method has the capability to eliminate the dc capacitor voltage ripple oscillating at double the source frequency. Experimental results obtained by a 10‐kW three‐phase diode rectifier load verify the validity of the proposed method. The proposed method exhibits a small dc capacitor voltage ripple reduced to 43% of that using the conventional method.     

Low‐Voltage‐Ride‐Through Performance of an HVDC Transmission System Using Two Modular Multilevel Double‐Star Chopper‐Cells Converters

This paper presents an intensive discussion on a long‐distance high‐voltage direct‐current (HVDC) transmission system that combines two modular multilevel cascade converters based on double‐star chopper cells (MMCC‐DSCC) with DC power cables. Hereinafter, a single MMCC‐DSCC is referred to as a DSCC converter or just as a DSCC for the sake of simplicity. The HVDC transmission system is required to provide low‐voltage‐ride‐through (LVRT) capability to enhance transmission system availability. This paper proposes a new LVRT method without any direct information exchange between the two DSCC converters. The validity of the method is verified, using simulated waveforms from the software package of “PSCAD/EMTDC” and experimental waveforms from a three‐phase 200‐V, 400‐Vdc, 10‐kW, 50‐Hz downscaled HVDC system with a set of 300‐meter‐long DC power cables.     

A single‐phase buck‐boost PFC converter with output‐voltage,ripple‐reducing operation

This paper describes a new single‐phase buck‐boost power‐factor‐correction (PFC) converter with output‐voltage, ripple reducing operation. The converter consists of a conventional buck‐boost PFC converter and an additional switch to obtain a freewheeling mode of the dc inductor current, and is operated by two modulators. The first modulator controls the buck‐boost switch to obtain PFC. The other modulator controls the square value of the instantaneous dc inductor current to perform the output‐voltage‐ripple‐reducing operation. In the two modulations, the time integral value of the input and output currents in each modulation period are controlled directly and indirectly, respectively. Thus, modulation errors or undesirable distortions of the input current and output voltage ripple are eliminated even if the dc inductor current produces large ripple in a low‐frequency range. The theories and combination techniques for the two modulators, implementation, and experimental results are described. © 1998 Scripta Technica, Electr Eng Jpn, 126(2): 56–70, 1999     

电压源换流器开关器件损耗建模

IGBT在电力电子装置中得到了大量应用,尤其是在高压大功率电压源换流器领域,而电压源换流器损耗分析一直是电力电子领域的一个研究热点。为了能对电压源换流器损耗进行精确分析,提出一种基于波形拟合理论的绝缘栅双极晶体管与二极管的损耗分析模型。建立的损耗模型充分考虑了电压源换流器不同开关里导通电流变化对于二极管反向恢复过程参数及损耗的影响,该模型还考虑了二极管与IGBT器件相互关系,器件电压、电流、结温变化对损耗的影响,特别计入了电流拖尾过程、电路杂散电感参数的影响。搭建了2.5kV输出Boost实验电路对该损耗模型进行验证,实验结果对比证明了该损耗模型的正确性和有效性。提出的损耗模型适用于电压源换流器型直流输电(voltage sourceconverter high voltage direct current,VSC-HVDC)、静止无功补偿器(static synchronous compensator,STATCON)、统一潮流控制器(unified power flow controller,UPFC)等高压大功率应用场合的电压源换流器损耗分析。     

高频感应加热电源死区时间的选择

以高频串联感应加热电源为研究对象,就串联谐振逆变器的换流过程从理论上进行了深入的研究。论述了死区对浪涌电压电流的影响,并经实验验证。     

Improvement of Three‐Phase Unbalance Due to Connection of Dispersed Generator by Damper Windings of Synchronous Generator

It is well known in the numerical simulations of a synchronous generator that the damper winding contributes to suppressing three‐phase circuit unbalance in power systems. However, an experimental study has not been performed yet. In this paper, we verify experimentally the suppression of three‐phase unbalance by the damper windings. In order to simulate the three‐phase unbalance, a 470‐W dispersed generator of single‐phase two‐line type was connected to a three‐phase laboratory‐scale power system that included a 6‐kVA synchronous generator. We measured and analyzed line voltages and currents as well as damper bar currents both with and without the dispersed generator. The influence of damper windings on the unbalance of the three‐phase circuit was also investigated. The results show that the damper winding contributes to improving the three‐phase unbalance. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 186(1): 43–50, 2014; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.22305     

A New PV Converter for Grid Connection Through a High‐Leg Delta Transformer Using Cooperative Control of Boost Converters and Inverters

This paper proposes a new high‐efficiency photovoltaic (PV) converter for grid connection through a high‐leg delta transformer, which is composed of a symmetrically connected boost converter and three half‐bridge inverters. One of the three half‐bridge inverters is connected to the boost converter, and the others are directly connected to the PV terminals. This circuit configuration enables to reduce the power losses in both boost converter and inverter. This paper also proposes a new cooperative control method between the symmetrically connected boost converter and inverter. The control method can reduce the average switching frequency to 75% of that in a conventional one, resulting in a great reduction in switching power loss. Experimental results show that the proposed circuit improves its European efficiency from 91.6% to 94.5%.     

A power decoupling control method for an isolated single‐phase AC‐to‐DC converter based on a high‐frequency cycloconverter

This paper proposes a new power decoupling method for a high‐frequency cycloconverter which converts the single‐phase line‐frequency ac input to the high‐frequency ac output directly. The cycloconverter consists of two half‐bridge inverters, two input filter capacitors, and a series‐resonant circuit. The proposed power decoupling method stores the input power ripple at double the line frequency in the filter capacitors. Therefore, the proposed method achieves a unity power factor in ac input and a constant current amplitude in the high‐frequency output without any additional switching device or energy storage element. This paper theoretically discusses the principle and operating performance of the proposed power decoupling method, and the viability is confirmed by using an experimental isolated ac‐to‐dc converter based on the high‐frequency cycloconverter. As a result, the proposed power decoupling method effectively improved the displacement power factor in the line current to more than 0.99 and reduced the output voltage ripple to 4% without any electrolytic capacitor.     

有源电力滤波器电流环高性能补偿控制策略分析

文章对传统电流环PI控制器检测误差进行了详细的理论分析,指出了检测负载侧谐波电流的局限性,提出了一种电源侧电流前馈补偿的控制器。该控制器基本上可以做到谐波指令的无静差跟踪,具有良好的补偿性能,克服了传统检测负载侧谐波电流时PT控制器的缺陷,而且具有传统检测负载侧谐波电流的灵活性,即使负载谐波电流高于有源电力滤波器的容量,也能够基本上无静差输出,具有一定的理论意义和工程应用价值。理论分析和仿真验证了此种新型控制策略的正确性和有效性。     

Verification of Characteristics of a Boost‐Type Matrix Converter for a Three‐Phase Four‐Wire System

This paper describes an improvement to the control method of a boost‐type matrix converter (MC) for a three‐phase four‐wire system. The system is intended for use in a stand‐alone power source with a constant voltage and frequency. However, the conventional method is not able to control the output voltage with a low power‐factor load. To resolve this problem, we propose a new control method by using a MC and revising the conventional control method.     

峰值电流控制的PFC变换器快时标分岔控制

峰值电流控制方式是PFC开关变换器的一种常用方式,由于输入电压的时变性造成在输入交流电压过零点处出现输入交流电流的快时标分岔现象,该现象会严重影响PFC变换器的性能,因此采用一种合理有效的分岔控制手段是非常重要的。文中深入分析了峰值电流控制PFC变换器工作原理,从理论上分析了PFC变换器出现快时标分岔现象的根源。在谐振分岔控制理论的基础上提出了一种比较有效的控制器参数选择方法,可以较好地实现PFC变换器的快时标分岔控制,因此改善了PFC变换器的性能。理论结果得到了数值仿真分析和实验的验证。     

非并网风力发电系统的电压协调控制

在非并网风力发电系统中,当风能突然增加或负载突然减少时,系统的功率平衡将被打破,从而造成直流电网中出现电压尖峰和电压升高,可能造成系统中功率器件的损坏。文中通过改变负载电流、输电线电压或注入电网电流等参考值,从而改变从直流电网吸收或向直流电网注入的电流值,抑制了电压尖峰和电压升高。仿真分析结果表明该控制方法能够起到很好的抑制作用。     

Unified Pulse‐Width Modulation Scheme for Improved Digital‐Peak‐Voltage Control of Switching DC‐DC Converters

Contrast to conventional dependent double‐edge (DDE) pulse‐width modulation (PWM), independent double‐edge (IDE) PWM is investigated and applied to the control of switching dc‐dc converters, with improved digital‐peak‐voltage (IDPV) controlled buck converter in this paper. IDE modulation unifies all the PWM schemes reported up to now and is thus called as unified PWM. It is revealed that conventional trailing‐edge, leading‐edge, trailing‐triangle, and leading‐triangle modulations are special cases of IDE modulation. The control laws of IDPV controlled buck converter with IDE modulation are investigated and compared with those of IDPV with DDE modulation. Their stabilities and robustness are analyzed subsequently. Digital implementation of the unified PWM is also carried out. Steady‐state and transient performances of IDPV controlled buck converters with IDE modulation and DDE modulation are compared and verified by experimental results. It is concluded that steady‐state and transient performances of IDPV with IDE are better than those of IDPV with DDE modulation. Copyright © 2012 John Wiley & Sons, Ltd.     

Three‐Phase Current Control by Dynamic Reconstruction of Undetected Currents for AC Motor Drives

This paper proposes new three‐phase current control methods for AC motor drives, which detects only a phase current from among three‐phase currents. The first proposed method first detects a phase current, and then estimates the two‐phase current in the stationary reference frame using the detected single phase current. The second proposed method first detects a phase current, then synthesizes the two‐phase quasi‐current in the dq rotating reference frame, and finally produces two‐phase current estimates by extracting the positive‐phase component from the quasi‐current. The third proposed method produces two‐phase current estimates by filtering out the negative‐phase component from the quasi‐current. This paper presents the principles and detailed characteristic analyses of the proposed methods and validates them on the basis of extensive experiments.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

低压配电线路分相功率因数自动补偿

介绍了分相无功功率自动补偿技术在建筑电气设计的中的应用,分析了该技术的特点,并以应用举例说明采用该技术后取后的效益。     

Compensation method of phase‐locked loop under unbalanced grid condition based on harmonic linearization

The voltage source converter (VSC) is often faced with unbalanced grid conditions that will degrade its performance because of the distorted current with a large amount of harmonics. One of the main parts of current distortion is the third‐order harmonics caused by the negative‐sequence voltage component at the fundamental frequency. The distorted output of the synchronous reference frame phase‐locked loop (SRF‐PLL) due to the unbalanced grid voltage is the main reason for the existence of the harmonics. This paper analyzes the mechanism of the generation of harmonics currents and proposes a compensation method for the PLL in VSCs based on the harmonic linearization method without changing the structure of SRF‐PLL. The proposed PLL can work properly under unbalanced grid conditions and has a good dynamic response. The third‐order current harmonics are reduced significantly by using the proposed PLL instead of the conventional SRF‐PLL without changing the current control strategy of VSC. The compensation method is verified by cycle‐by‐cycle circuit simulations and controller hardware‐in‐the‐loop experiments.