Low-noise properties of dry gate recess etched InP HEMTs

Lattice-matched InAlAs-InGaAs HEMTs with dry etched and wet etched gate recesses have been fabricated and both high-frequency and noise measurements have been carried out. The highly selective dry etching process ensures uniform device parameters. The small signal and noise performance shows only minor differences between the two transistor types. There is no evidence of detrimental effects caused by dry etching that reduce the electrical and noise performance of the device at high frequencies. These results show that dry etched InP HEMT's have suitable characteristics for the fabrication of MM-wave integrated circuits     

Trap studies in GaInP/GaAs and AlGaAs/GaAs HEMT's by means oflow-frequency noise and transconductance dispersion characterizations

The presence of traps in GaInP/GaAs and AlGaAs/GaAs HEMT's was investigated by means of low frequency noise and frequency dispersion measurements. Low frequency noise measurements showed two deep traps (E _a1=0.58 eV, E_a2=0.27 eV) in AlGaAs/GaAs HEMT's. One of them (E_a2) is responsible for the channel current collapse at low temperature. A deep trap (E_a1'=0.52 eV) was observed in GaInP/GaAs HEMT's only at a much higher temperature (~350 K). These devices showed a transconductance dispersion of ~16% at 300 K which reduced to only ~2% at 200 K. The dispersion characteristics of AlGaAs/GaAs HEMT's were very similar at 300 K (~12%) but degraded at 200 K (~20%). The low frequency noise and the transconductance dispersion are enhanced at certain temperatures corresponding to trap level crossing by the Fermi-level. The transition frequency of 1/f noise is estimated at 180 MHz for GaInP/GaAs HEMT's and resembles that of AlGaAs/GaAs devices     

Low frequency noise sources in InAlAs/InGaAs MODFETs

Detailed analysis of the 1/f low-frequency noise (LFN) in In/sub 0.52/Al/sub 0.48/As/InGaAs MODFET structures is performed, for low drain bias (below pinch-off voltage), in order to identify the physical origin and the location of the noise sources responsible for drain current fluctuations in the frequency range 0.1 Hz-10/sup 5/ Hz. Experimental data were analyzed with the support of a general modeling of the 1/f LFN induced by traps distributed within the different layers and interfaces which constitute the heterostructures. Comparative noise measurements are performed on a variety of structures with different barrier (InAIAs, InP) and different channel (InGaAs lattice matched to InP, strained InGaAs, InP) materials. It is concluded that the dominant low frequency noise sources of InAlAs/InGaAs MODFET transistors in the ON state are generated by deep traps distributed within the "bulk" InAlAs barrier and buffer layers. For reverse gate bias, the gate current appears to be the dominant contribution to the channel LFN, whereas both the gate current and the drain and source ohmic contacts are the dominant sources of noise when the device is biased strongly in the ON state. Heterojunction FET's on InP substrate with InP barrier and buffer layers show significantly lower LFN and appear to be more suitable for applications such as nonlinear circuits that have noise upconversion.     

Origins and characterization of low-frequency noise in GaAsMESFET's grown on InP substrates

An experimental study of the low-frequency noise in GaAs MESFET's grown on InP substrates is reported. The influence of the biases applied to the gate, backgate, and drain in the ohmic region is investigated in order to identify and characterize the 1/f noise origin. We find that this noise can be explained by carrier number fluctuations in the channel and related to trapping phenomena. The traps responsible for this noise are located near the channel-buffer interface. Moreover, the noise behavior exhibits for a well-defined gate voltage, corresponding to the case where the drain current flows near the channel-buffer interface, a GR-type (Lorentzian) noise spectrum emerging from a quite general 1/f noise. This last spectrum corresponds to a single trap level with a density of N_T=10¹⁶ cm^-3 and a time constant τ=1.8 ms which may be attributed to crystal defects present in the GaAs layers     

栅槽刻蚀工艺对增强型GaN HEMT器件性能的影响

基于凹槽栅增强型氮化镓高电子迁移率晶体管(GaN HEMT)研究了不同的栅槽刻蚀工艺对GaN器件性能的影响。在栅槽刻蚀方面,采用了一种感应耦合等离子体(ICP)干法刻蚀技术与高温热氧化湿法刻蚀技术相结合的两步法刻蚀技术,将AlGaN势垒层全部刻蚀掉,制备出了阈值电压超过3 V的增强型Al_2O_3/AlGaN/GaN MIS-HEMT器件。相比于传统的ICP干法刻蚀技术,两步法是一种低损伤的自停止刻蚀技术,易于控制且具有高度可重复性,能够获得更高质量的刻蚀界面,所制备的器件增强型GaN MIS-HEMT器件具有阈值电压回滞小、电流开关比(I_ON/I_OFF)高、栅极泄漏电流小、击穿电压高等特性。     

Effects of SiN passivation and high-electric field on AlGaN-GaN HFET degradation

The authors report on the effects of silicon nitride (SiN) surface passivation and high-electric field stress (hot electron stress) on the degradation of undoped AlGaN-GaN power HFETs. Stressed devices demonstrated a decrease in the drain current and maximum transconductance and an increase in the parasitic drain series resistance, gate leakage, and subthreshold current. The unpassivated devices showed more significant degradation than SiN passivated devices. Gate lag phenomenon was observed from unpassivated devices and removed by SiN passivation. However, SiN passivated devices also showed gate lag phenomena after high-electric field stress, which suggests possible changes in surface trap profiles occurred during high-electric field stress test.     

A Comparative Study of a Dielectric‐Defined Process on AlGaAs/InGaAs/GaAs PHEMTs

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric‐defined process. This process was utilized to fabricate 0.12 μm × 100 µm T‐gate PHEMTs. A two‐step etch process was performed to define the gate footprint in the SiN_x. The SiN_x was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T‐gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross‐sectional area of the gate and its mechanically stable structure. From s‐parameter data of up to 50 GHz, an extrapolated cut‐off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the SiN_x) with sample A (dry etching for the SiN_x), we observed an 62.5% increase of the cut‐off frequency. This is believed to be due to considerable decreases of the gate‐source and gate‐drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.     

HEMT degradation in hydrogen gas

The effect of hydrogen treatment on both GaAs pseudomorphic HEMT's and InP-based HEMT's, in order to simulate the hermetic seal environment in a Kovar package, is reported for the first time. Under the 270°C, 4% H₂ in Ar atmosphere, significant changes in both types of HEMT's were observed within several minutes. While the drain current at a fixed gate bias and the pinchoff voltage of the GaAs PHEMT consistently decreased under the influence of the hydrogen gas, they were found to either increase or decrease with the InP HEMT. The change of device characteristics resulting from exposure to the hydrogen environment is not permanent; partial recovery of device characteristics was observed under either nitrogen or hydrogen at both elevated and room temperatures. The change in HEMT DC characteristics seems to be primarily resulted from the change in the gate built-in potential. Any device changes due to the Si-donor neutralization by atomic hydrogen, and therefore a reduction in channel carrier concentration, were found to be insignificant     

ECR plasma etch fabrication of C-doped base InGaAs/InP DHBT structures: A comparison of CH4/H2/Ar vs BCl3/N2 plasma etch chemistries

We compare ECR plasma etch fabrication of self-aligned thin emitter carbondoped base InGaAs/InP DHBT structures using either CH₄/H₂/Ar or BCl₃/N₂ etch chemistries. Detrimental hydrogen passivation of the carbon doping in the base region of our structure during CH₄/H₂/Ar dry etching of the emitter region is observed. Initial conductivity is not recovered with annealing up to a temperature of 500°C. This passivation is not due to damage from the dry etching or from the MOMBE growth process, since DHBT structures which are ECR plasma etched in BCl₃/N₂ have the same electrical characteristics as wet etched controls. It is due to hydrogen implantation from the plasma exposure. This is supported with secondary ion mass spectroscopy profiles of structures which are etched in CH₄/D₂/Ar showing an accumulation of deuterium in the C-doped base region.     

Low frequency gate noise in a diode-connected MESFET: measurementsand modeling

The low frequency Schottky diode noise has been investigated in GaAs power MESFETs. For those devices, gate noise spectra are generally composed of 1/f and shot noise contributions. We have observed an increase by two orders of magnitude of the noise level when MESFETs are submitted to rf life-test. The increase of the 1/f noise can be explained by a modification of the gate space charge region extension. This interpretation is sustained by a reduction of the drain current transient magnitude and the inherent active trap density. A correlation is assumed between the increase of the shot noise level after rf life-test and a micro-plasma formation. Both 1/f noise and shot noise evolution might originate in a local increase of the electric field in the vicinity of the gate in drain access region. We have demonstrated that LF gate current noise is an early indicator of damage mechanisms occurring at the gate-semiconductor and passivation-semiconductor interfaces of the devices     

Measurement of plasma etch damage by a new slow trap profilingtechnique

MOS capacitor structures with plasma damaged oxides have been used to demonstrate a new technique for profiling slow traps at the Si-SiO ₂ interface. The technique measures the density and trapping rate of slow traps by stepping the gate voltage in small increments and monitoring the resulting substrate current transients, thereby producing a profile of the traps in energy and response time. The response time is a function of the trap's energy position and distance from the interface. Some traps created by plasma etching are not obvious in quasistatic CV measurements, yet are clearly evident when the new technique is used. Results show an increase in slow trap densities and response times in the upper half of the silicon bandgap with long plasma overetch times. In comparison, wet etched control devices show only low densities of slow traps with shorter response times around the midgap     

Enhancement mode InP MISFET's with sulfide passivation andphoto-CVD grown P3N5 gate insulators

High performance enhancement mode InP MISFET's have been successfully fabricated by using the sulfide passivation for lower interface states and with photo-CVD grown P₃N₅ film used as gate insulator. The MISFET's thus fabricated exhibited exhibited pinch-off behavior with essentially no hysteresis. Furthermore the device showed a superior stability of drain current. Specifically under the gate bias of 2 V for 10⁴ seconds the room temperature drain current was shown to reduce from the initial value merely by 2.9% at the drain voltage of 4 V. The effective electron mobility and extrinsic transconductance are found to be about 2300 cm ²/V·s and 2.7 mS/mm, respectively. The capacitance-voltage characteristics of the sulfide passivated InP MIS diodes show little hysteresis and the minimum density of interface trap states as low as 2.6×10¹⁴/cm² eV has been attained     

The effect of surface passivation on the microwave characteristicsof undoped AlGaN/GaN HEMTs

Surface passivation of undoped AlGaN/CaN HEMT's reduces or eliminates the surface effects responsible for limiting both the RF current and breakdown voltages of the devices. Power measurements on a 2×125×0.5 μm AlGaN/GaN sapphire based HEMT demonstrate an increase in 4 GHz saturated output power from 1.0 W/mm [36% peak power-added efficiency (PAE)] to 2.0 W/mm (46% peak PAE) with 15 V applied to the drain in each case. Breakdown measurement data show a 25% average increase in breakdown voltage for 0.5 μm gate length HEMT's on the same wafer. Finally, 4 GHz power sweep data for a 2×75×0.4 μm AlGaN/GaN HEMT on sapphire processed using the Si₃N₄ passivation layer produced 4.0 W/mm saturated output power at 41% PAE (25 V drain bias). This result represents the highest reported microwave power density for undoped sapphire substrated AlGaN/GaN HEMT's     

Traps centers impact on Silicon nanocrystal memories given by Random Telegraph Signal and low frequency noise

This work reports on a comprehensive process of trapping centers in Silicon nanocrystal (nc-Si) memories devices. The trap centers have been studied using Random Telegraph Signal (RTS) and Low Frequency (LF) techniques. The study of the traps which are responsible for RTS noise in non-volatile memories (NVM) devices as a function of gate voltage and temperature, offers the opportunity of studying the trapping/detrapping behaviour of a single interface trap center. The RTS parameters of the devices having random discrete fluctuations in the drain current get more information about trap energy level and spatial localization from the SiO₂/Si interface. The impact of trap centers has been also investigated showing the significant noise between memories and references devices. Furthermore, it has convincingly been shown that this discrete switching of the drain current between a high and a low state is the basic feature responsible for l/f^γ flicker noise in MOSFETs transistors.     

Deuterium passivation of interface traps in MOS devices

The mechanism for deuterium passivation of interface traps in MOS devices is studied. Normal channel hot electron (CHE) stress was performed on hydrogen-passivated devices to locally desorb hydrogen from the interface at the drain region. The stressed devices were annealed in deuterium at 400°C, resulting in a full recovery of device characteristics. These devices were then subjected to CHE stress again in two modes. Some of them were stressed in the normal mode while others were stressed in the reverse mode in which the source and drain were interchanged. Compared with hydrogenated devices, these deuterated devices under the normal stress exhibit a significant reduction in interface trap generation and threshold voltage shift. In contrast, insignificant reliability improvement was observed for the reverse stress case. The asymmetric degradation behaviors on these deuterated devices suggest that the effectiveness of implementing deuterium to improve device reliability is limited by its replacement of pre-existing hydrogen at the oxide/silicon interface     

Hot electron induced degradation of undoped AlGaN/GaN HFETs

This work presents the effects of hot electron stress on the degradation of undoped Al_0.3GaN_0.7/GaN power HFET’s with SiN passivation. Typical degradation characteristics consist of a decrease in the drain current and maximum transconductance, an increase in the drain series resistance, gate leakage and a subthreshold current. Degradation mechanism has been investigated by means of gate lag measurements (pulsed I-V) and current-mode deep level transient spectroscopy (DLTS). Stressed devices suffered from aggravated drain current slump (DC to RF dispersion) which indicates possible changes in surface charge profiles occurred during hot electron stress test. The DLTS was used to identify the trap creation by hot electron stress. The DLTS spectra of stressed device revealed the evidence of trap creation due to hot electron stress.     

湿法化学腐蚀在GaN基材料中的应用

文中计算了AlGaN材料在不同温度KOH水溶液中的湿法腐蚀速率，并研究了湿法化学腐蚀GaN基材料对消除干法刻蚀所引入损伤的作用。为了对比湿法化学腐蚀消除干法刻蚀损伤的效果，分别利用扫描电子显微镜(SEM)、原子力显微镜(AFM)和俄歇电子能谱(AES)对比Ar+干法刻蚀后经湿法化学腐蚀处理和未经处理的表面形貌及组分，并制作了单元可见盲器件，测试其反向漏电流，发现在干法刻蚀后引入湿法化学腐蚀工艺可使器件的反向漏电流得到较大程度的减小。     

The effects of plasma etching induced gate oxide degradation onMOSFET's 1/f noise

The effects of the plasma etching process induced gate oxide damages on device's low frequency noise behavior are investigated on MOSFET's fabricated with different field plate perimeter to gate area ratio antennas. Abnormal 1/f noise spectrum with a shoulder centered in the frequency range of 100 and to 1 kHz was frequently observed in small geometry devices, and it is attributable to a nonuniform distribution of oxide traps induced by plasma etching process     

Etched mirror and groove-coupled GaInAsP/InP laser devices for integrated optics

Recent advances in wet and dry etching techniques for GaInAsP/InP laser structures allow the reproducible fabrication of planar and vertical walled facets and grooves. These elements provide efficient mirrors and interstage couplers that may provide the basis for a new generation of monolithic integrated optical devices. Initial experimental results on etched facet lasers and groove-coupled two-section lasers verify theoretical expectations.     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%