电容式压力传感器的厚膜集成化研究

本文采用厚膜传感技术研制电容式感压元件，并通过厚膜混合集成技术和工艺交叉将信号处理电路集成在感压元件上成为一体，进行电容式压力传感器的厚膜集成化研究。结果表明，研制成的新型厚膜电容式集成压力传感器，线性达到0．5％，迟滞小于0．5％，重复性好。具有受分布电容、寄生电容影响小，抗干扰能力强，精度高，抗过载、耐腐蚀等特点。     

平板显示器驱动芯片中NLDMOS寄生电容

功率器件寄生电容的大小直接关系到平板显示器驱动芯片的功耗及性能．本文利用器件的动态电流来分析NLDMOS寄生电容特性．在不影响NLDMOS直流特性的前提下,通过改变鸟嘴位置,得到具有低寄生电容的高性能器件．将该器件应用于平板显示器驱动芯片高低压转换电路,模拟结果证明该电路的自身功耗降低了34%,高压输出对低压控制信号的扰动减小了32%．     

平板显示器驱动芯片中NLDMOS寄生电容

功率器件寄生电容的大小直接关系到平板显示器驱动芯片的功耗及性能.本文利用器件的动态电流来分析NLDMOS寄生电容特性.在不影响NLDMOS直流特性的前提下,通过改变鸟嘴位置,得到具有低寄生电容的高性能器件.将该器件应用于平板显示器驱动芯片高低压转换电路,模拟结果证明该电路的自身功耗降低了34%,高压输出对低压控制信号的扰动减小了32%.     

用分布电容模型分析和优化差分电感

建立了预测片上等效寄生电容的片上电感分布电容模型.预测和解释了差分电感的自激振荡频率的差异.实测数据显示,与单端驱动模式下的相同对称电感相比,差分驱动模式电感提高最大品质因数127%,具有更大的工作频率范围.设计和验证了低寄生电容的差分电感.     

彩色PDP低功耗驱动技术探讨

目前彩色PDP的功耗比较大,这主要是由于它的发光效率比较低,高压高速电路损耗较大,以及显示屏寄生电容的充、放电而带来的无用功耗比较大而造成的。为了降低彩色PDP的功耗,介绍了能量恢复技术、降低电路损耗的电路技术、以及多种提高发光效率的驱动方式等多种方法,这些方法的综合采用,可以显著降低PDP的功耗。     

基于厚膜技术的电容集成压力传感器的感压元件研究

采用厚膜技术研制新型电容式集成压力传感器用感压元件,具有抗干扰能力强,灵敏度高,受分布电容、寄生电容影响小,耐腐蚀,耐高温的特点。本主要介绍其原理、感压元件设计,并对非线性等相关技术及工问题进行了探讨。     

传感器网络中信息驱动路由算法及其仿真实现

传感器网络集成了传感器、计算机和网络三大技术，是一种全新的信息获取和处理技术。信息驱动路由就是基于信息的内容和通信开销来决定节点的选择，以达到优化信息获取和降低通信开销的目的。现介绍了信息驱动路由算法，并通过仿真对其性能进行了分析。     

多传感器技术工业机器人的应用分析

随着信息技术的不断发展，多传感器技术得到了广泛应用，其在工业机器人领域中发挥着重要作用。多传感器技术的应用价值主要表现在精准定位与检测、环境感知与安全保障以及任务规划与执行优化等方面。然而，在应用多传感器技术的过程中，也存在成本较高、技术门槛较高以及系统集成困难等不足之处。为了克服这些限制，需要加强技术研发，提高工作人员素质，并加强系统集成，进一步提高多传感器技术在工业机器人领域中的应用效果。     

机电技术中传感器技术的应用

随着科技的发展，传感器的种类越来越多，性能越来越丰富，应用领域也在不断地扩展，在社会生产和人们的日常生活中具有不可替代的地位和作用。本文分析了传感器技术在机器人、汽车自控系统和机械加工等机电技术中的地位和应用，指出了其目前存在的问题和不足，并探讨其未来的发展方向。     

光纤传感技术的应用及发展

介绍了传光型与传感型光纤传感器的基本原理，阐述了强度调制型光纤传感器、干涉型光纤传感器、光纤光栅以及光纤声发射传感器的应用，指出我国光纤传感技术存在的问题以及发展方向。     

Low-frequency capacitance measurements

The letter proposes a technique for the fast determination at extremely low frequencies of the capacitance and leakage components of capacitors. The proposed method permits the measurement of C and G in only a few cycles. An apparatus is described employing this technique for the automatic measurement of m.o.s. capacitance as a function of frequency and bias voltage.     

Junction capacitance switches

The design of junction capacitance switches consisting of a combination of abrupt junctions is considered. Theoretical characteristics are calculated for ideally abrupt junctions. The possibilities of fabrication by alloying and epitaxial growth are briefly discussed.     

Inductor winding capacitance cancellation using mutual capacitance concept for noise reduction application

In this paper, the properties of mutual capacitance between two capacitors are first discussed. It is found that the effects of mutual capacitance can be represented by two positive or negative capacitors across the two capacitors. These two equivalent capacitors can be used to cancel the parasitic capacitance of inductors. Because the mutual capacitance can be emulated using two small capacitors, the proposed method can easily be implemented in practical components. The prototypes are then built and the cancellation is verified using a network analyzer. Further EMI measurements in a practical power circuit prove that there is a significant improvement in the inductor's filtering performance.     

A basic capacitance switch

The use of a thin dielectric electron tunneling element along with basic conventional circuit elements is discussed. The circuits considered perform as a voltage-controlled capacitance switch, a voltage-controlled capacitance staircase generator, and a read only computer memory element.     

Tunnel-diode junction capacitance measurement

This paper describes a basic HF (as contrasted to VHF or microwave frequency) substitution technique for measurement of tunnel-diode junction capacitance. This technique was devised to solve the problem of series lead inductance errors resulting from the high conductance of these diodes and the resultant fractional Q's of their junction capacitances in the HF region. The paper also describes an extension of this technique which has made possible the determination of diode capacitances as low as 2 µµf in the negative resistance region for diodes having time constants<10^{-10}with an uncertainty of less than ±0.25 µµf.     

MIS capacitance and derivative of capacitance,with application to nonparabolic band semiconductors

Theoretical capacitance (C-V) and derivative of capacitance (C′-V) curves for an MIS structure with a semiconductor having a nonparabolic conduction band and a parabolic valence band are calculated for single level trap, uniform and nonuniform surface state distributions. The Kane model is used to describe the nonparabolic conduction band. The effects of varying the hole effective mass, Kane matrix element, temperature, surface state densities (both donor and acceptor types), and the degeneracy factors for the surface states is examined. The computed results are based on Hg_0·8Cd_0·2TeZnS device parameters.     

Parasitic capacitance of submicrometer MOSFET's

We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer devices. Furthermore, we proposed a simple model that ensures the same accuracy as that of the Kamchouchi model     

Investigation of interconnect capacitance characterization usingcharge-based capacitance measurement (CBCM) technique andthree-dimensional simulation

This paper examines the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure     

Unified quasi-static MOSFET capacitance model

An accurate calculation of MOSFET capacitance-voltage (C V) characteristics has to account for the bulk charge which is affected by nonuniform doping profiles and short-channel effects. In an approach based on the unified charge control model (UCCM), the voltage dependencies of the bulk charge are related to the standard parameters of the body plots which are routinely measured during MOSFET characterization. The results of the C-V calculations based on this model are in good agreement with experimental data and calculations based on the standard BSIM model. Compared to the BSIM simulations, the present model more accurately describes capacitances related to the bulk charge and the device subthreshold behavior, and it is suitable for incorporation into circuit simulators     

大容量MLCC的工艺设计

采用四层端电极(Ni/Cu/Ni/Sn)结构设计,底层为Ni,电镀Cu/Ni/Sn的工艺方法,制作了大容量MLCC。研究了四层结构和三层结构(Cu/Ni/Sn)对电容量等基本电性能、可靠性和内应力的影响。结果表明:制作1206规格10μFMLCC,C为9.86～10.46μF、tanδ为(360～390)×10–4、绝缘电阻≥1.5×108Ω、耐电压值为175～205V,四层结构与三层结构电性能相当。可靠性测试中,四层结构抗机械和热冲击能力提高了20%,且有利于瓷体内应力释放。