A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic

Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.     

电压微分式静电探测系统设计与实现

空中运动目标带电量高且难以去除,这为静电探测系统提供了理论依据。介绍了一种电压微分式的静电探测系统,利用目标在探测器位置的场强变化得到了感应电压公式,然后对其微分后得到了变化的电流。通过仿真验证了该公式的正确性和实用性,并据此设计了相应的探测电路,通过实验验证了该探测系统的可行性。     

Design and implementation of monostable multivibrators employing differential voltage current conveyors

In this paper, two novel application circuits utilizing the differential voltage current conveyor (DVCC) are introduced and implemented. To the best knowledge of authors, this is the first reported monostable multivibrators employing DVCC device. Each presented circuit is constructed by single DVCC as the basic active building block together with a few passive components. Both of them can be operated via a positive-edge triggering signal to generate a pulse waveform with an adjustable width. The first one is a general monostable circuit. The second design is an improved construction, which shortens the recovery time for applying the consecutive triggering signals. The circuit operations are first described and then the non-ideal issues and design considerations of the proposed circuits are discussed. To demonstrate their feasibility, the presented circuits are simulated using circuit simulation program Is-Spice. Available commercial ICs and discrete components are used to implement the prototype circuits. Simulation and experimental results agree well with the theoretical analysis.     

Design and implementation of differential pulsewidth control loop for GHz VLSI systems

A novel differential pulsewidth control loop (PWCL) is proposed, in which a balanced charge pump is employed so that the PWCL does not require a 50% duty cycle reference clock. A test chip is realised in a 0.35 /spl mu/m CMOS process, and the measured results show that the tuning range for the duty cycle of the input clock is from 27 to 71% at 1 GHz operating frequency.     

A mesochronous pipelining scheme for high-performance digital systems

A novel mesochronous pipelining scheme is described in this paper. In this scheme, data and clock travel together. At any given time a pipeline stage could be operating on more than one data wave. The clock period in the proposed pipeline scheme is determined by the pipeline stage with largest difference between its minimum and maximum delays. This is a significant performance gain compared to conventional pipeline scheme where clock period is determined by the stage with the largest delay. A detailed analysis of the clock period constraints is provided to show the performance gains and Speedup of mesochronous pipelining over other pipelining schemes. Also, the number of pipeline stages and pipeline registers is small. The clock distribution scheme is simple in the mesochronous pipeline architecture. An 8 /spl times/ 8-bit carry-save adder multiplier has been implemented in mesochronous pipeline architecture using modest TSMC 180-nm (drawn length 200 nm) CMOS technology. The multiplier architecture and simulation results are described in detail in this paper. The pipelined multiplier is able to operate on a clock period of 350 ps (2.86 GHz). This is a Speedup of 1.7 times over conventional pipeline scheme, with fewer pipeline stages and pipeline registers.     

LVDS技术的应用

LVDS技术 随着互联网日趋普及,各式各样的通信设备也日渐受到消费者的欢迎,令数据传输的需求急剧增加.此外,数字电视、高分辨率电视及彩色图像均需要更高的频宽.因此,系统设计工程师必须依靠模拟技术设计电路系统及支持数据传输.     

Charge recycling differential logic (CRDL) for low powerapplication

A novel logic family, called charge recycling differential logic (CRDL), has been proposed and analyzed. CRDL reduces power consumption by utilizing a charge recycling technique with the speed comparable to those of conventional dynamic logic circuits. It has an additional benefit of improved noise margin due to inherently static operation. The noise margin problem of true single-phase-clock latch (TSPC) is also eliminated when a CRDL logic circuit is connected to it. Two swing-suppressed-input latches (SSILs), which are introduced for use with CRDL, have better performance than the conventional transmission gate latch. Moreover, a pipeline configuration with CRDL in a true two-phase clocking scheme shows completely race-free operation with no constraints on logic composition. Eight-bit Manchester carry chains and full adders were fabricated using a 0.8 μm single-poly double-metal n-well CMOS technology to verify the relative performance of the proposed logic family. The measurement results indicate that about 16-48% improvements in power-delay product are obtained compared with differential cascode voltage switch (DCVS) logic     

数字音频电压放大器的设计

首先介绍了两种专用数字音频处理器的性能特点和原理，然后阐述高品质数字音频电压放大器的几种电路设计方案。     

Latched CMOS differential logic (LCDL) for complex high-speed VLSI

A CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results verified the high speed and race-free performance of the proposed LCDL     

基亏ARM的数字调压控制系统设计与实现

随着电子信息技术和半导体技术的深入发展,嵌入式系统的应用日趋广泛,在控制领域之中更多的使用了高性能微处理器．以满足各方面越来越多的控制应用需求。基于ARM嵌入式平台的数字调压控制系统,克服了传统上以旋钮或滑变式变阻器对交流电压进行模拟控制的弊端。本系统以嵌入式技术为基础,在嵌入式平台上利用ARM微处理器实时控制数模信号的转换．以控制正弦波调压模块对交流电压的大小调节。本文中通过对本系统的实际测试,验证了数字调压控制系统的功能特性．并且定量测试得出了本系统可以实现对交流电压进行线性调节的结论。数字调压控制系统可作为对电压的智能调节装置应用于家庭、医疗及工业自动化等领域,并且具有调节精度高、调节线性度好．易于操作等特性。     

PLA implementation of a differential predictive coder for digital television signals

Implementation of reduced bit rate television communication systems for teleconference and videophone applications heavily depends on coder costs. This paper analyses the structure of a Differential Predictive Coder (DPCM) based on PLAs down to the lay-out and simulation stages. The DPCM algorithm is represented by its Z-transform, and by a dependency graph which allows the introduction at a high representation level of the basic architectural parameters: parallelism and sequentiality. As a third step a modular architecture is introduced for realizing the algorithm with functional modules. Modules are then realized with predetermined building blocks: PLAs and transmission gates. At last, circuit implementation is described in order to gain a global idea of the system structure and performances. The integrated circuit has been implemented by SGS-Microelettronica and should be able to process video signals up to a sampling frequency of 5 Mhz.     

多通道数字接收机的设计与实现

为了解决传统模拟中频接收机相位分辨率低等缺点,提出一种基于软件无线电的中频数字接收机技术。针对雷达信号的特点提出了脉宽匹配滤波器的设计方法。采用基于多相滤波的正交变换理论,以及基于脉宽匹配的数字滤波器方法完成了一种五通道中频数字接收机的设计。接收机利用五路高速A/D变换器对输入的模拟信号进行采样,然后将采样数据送入FPGA进行处理,最终完成了每两路信号相位差的提取。实验结果表明系统具有成本低、精度高、结构简单等特点,而且具有一定的工程应用价值。     

多功能数字测试仪的设计与实现

为把数字万用表、绝缘电阻表、漏电开关测试仪等三种功能的测量仪器,合并为一种新型手持式测量仪表。采用专用集成电路ES51921和高性能微控制器MSP430F2111及外部扩展电路、液晶显示器（LCD）等组成,将多功能测试仪设计成具有多功能、智能化的特点和显示直观、读数精准、功能完善、耗电省、体积小、易于携带等优点。该多功能测试仪经测试符合相关技术标准。     

Design and implementation of digital tomographic filters

A technique is proposed which allows the selective filtering of conventional radiographs in order to obtain depth-dependent information by utilizing the depth-dependent information contained therein. This technique, referred to as tomographic filtering or tomographic filtration process (TFP), takes advantage of the finite size of the X-ray source, so that after processing, the image of a particular layer is improved while the others are not. This paper starts with a brief review of technique and then concentrates on the design and implementation of digital tomographic filters. Examples are shown, including images of simulated radiographs processed with such filters. Evaluations of the performance of these filters show that the image quality cannot be as good as that of standard tomography or multiprojection reconstruction techniques; nevertheless they represent an improvement over conventional radiology, and highlight additional depth-dependent information contained in radiographs. This paper concludes with suggestions for further research in this area.     

Design of high-performance digital hearing aid processor

A digital hearing aid processor (DHAP) chip built around a general-purpose 16 bit DSP core is presented. The designed DHAP performs a nonlinear loudness correction of eight frequency bands based on acoustic measurements. The DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the chip has a low power feature and 5,500×5,000 μm² dimensions that make it suitable for wearable hearing aids     

Design and implementation of a digital filter for beat-by-beatimpedance cardiography

A digital filter for thoracic impedance cardiography was developed and implemented on a 16-bit personal computer after examining the effect of respiratory movement on the first derivative of the thoracic impedance signal. Four male subjects exercised with a cycle ergometer at 100 and 150 W successively, after resting for 5 min. Thoracic impedance and its first derivative (dZ/dt) were recorded by a standard four-electrode cardiograph. The peak-power spectral densities of the pneumogenic (P_p,c) and the cardiogenic (P_p,c) components of dZ/dt were separated with a simultaneous recording of the ECG and thoracic circumferences. P_pP_c increased with each increment of work rate: 0.12 (0.05-0.19) at rest, 0.67 (0.49-0.97) at 100 W, and 0.97 (0.58-1.52) at 150 W     

摩托车数字点火器标定系统的设计与实现

针对摩托车数字点火器,实现了一种低成本的标定系统。通过USB-RS232接口电路实现标定系统上、下位机的硬件连接。基于.NET Framework的Visual C#多线程编程技术完成上位机软件标定界面、监控模块、标定数据文件管理的设计;采用前后台模式完成下位机软件的标定通信和点火控制模块设计。实验表明,该标定系统工作稳定,操作方便,为数字点火器的快速开发提供了有效工具。     

Design and implementation of current mode circuit for digital modulation

This paper proposes a new current-mode digital modulation circuit. The proposed circuit is MOS only hence, easily integrable. It employs an Extra X Current Conveyor (EX-CCII), two MOS transistors as switches, and a two MOS transistor-based active resistor. The amplitude shift keying/phase shift keying/frequency shift keying (ASK/PSK/FSK) modulator is obtained by proper selection of carriers (I_C1, I_C2). This circuit provides the current output signal at high output impedance, which is favorable for cascading. Also, the circuit is employing only MOS transistors, so it can be monolithically IC implementable. The effects of non-idealities and parasitics of the active element on the circuit performance are also investigated in detail. The functionality of the proposed digital modulator is verified through the Cadence Virtuoso tool using 0.18 μm Generic Process Design Kits parameters with the ±0.9 V supply voltage. The total area of the layout is 968.75 μm². Also, the experimental results are verified by using the IC AD-844 and IC CD4007.     

Design and application of pipelined dynamic CMOS ternary logic andsimple ternary differential logic

Dynamic CMOS ternary logic circuits that can be used to form a pipelined system with nonoverlapped two-phase clocks are proposed and investigated. The proposed dynamic ternary gates do not dissipate DC power and have full voltage swings. A circuit structure called the simple ternary differential logic (STDL) is also proposed and analyzed, and an optimal procedure is developed. An experimental chip has been fabricated in a 1.2-μm CMOS process and tested. A binary pipelined multiplier has been designed, using the proposed dynamic ternary logic circuits in the interior of the multiplier for coding of radix-2 redundant positive-digit number. The structure has the advantages of higher operating frequency, less latency, and lower device count as compared with the conventional binary parallel pipelined multiplier. The advantages of the circuits over other dynamic ternary logic circuits are shown     

Design of high-speed digital filters suitable for multi-DSP implementation

A multipath signal processing scheme is proposed to overcome the limitation on throughput rate of present-day LSI devices using a number of digital signal processors. Two methods are proposed to realize a given transfer function H(z) for a digital filter with a throughput rate speed that is N times higher than in conventional methods. The first method, the delayed multipath approach, uses an N-path structure as a building element. These N elements are connected successively with increasing delay units to realize a given transfer function. The second method preprocesses the input signal sequence with an FFT processor and follows it up by N of constituent transfer functions derived from H(z) having real coefficients. The output of these N constituent transfer functions is finally post processed by an inverse FFT processor to obtain the desired output signal. The number of the constituent transfer functions is double for a special case when the transfer function to be implemented has complex valued coefficients.