A 1-V 10.7-MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using double-sampling finite-gain-compensation technique

A 1 V switched-capacitor (SC) bandpass sigma-delta (/spl Sigma//spl Delta/) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution /spl Sigma//spl Delta/ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-/spl mu/m CMOS process (V/sub TP/=0.82 V and V/sub TN/=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm/sup 2/.     

A 80-MHz bandpass ΔΣ modulator for a 100-MHz IFreceiver

A fully differential fourth-order bandpass ΔΣ modulator is presented. The circuit is targeted for a 100-MHz GSM/WCDMA-multimode IF-receiver and operates at a sampling frequency of 80 MHz. It combines frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an intermediate frequency of 100 MHz to a digital intermediate frequency of 20 MHz. The modulator is based on a double-delay single-op amp switched-capacitor (SC) resonator structure which is well suited for low supply voltages. Furthermore, the center frequency of the topology is insensitive to different component nonidealities. The measured peak signal-to-noise ratio is 80 and 42 dB for 270 kHz (GSM) and 3.84-MHz (WCDMA) bandwidths, respectively. The circuit is implemented with a 0.35-μm CMOS technology and consumes 56 mW from a 3.0-V supply     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

Low-voltage temperature sensor for micro-power harvesters in silicon-on-sapphire CMOS

A low-voltage temperature sensor designed for MEMS power harvesting systems is fabricated. The core of the sensor is a bandgap voltage reference circuit operating with a supply voltage in the range 1-1.5 V. The prototype was fabricated on a conventional 0.5 /spl mu/m silicon-on-sapphire (SOS) process. The sensor design consumes 15 /spl mu/A of current at 1 V. The internal reference voltage is 550 mV. The temperature sensor has a digital square wave output the frequency of which is proportional to temperature. A linear model of the dependency of output frequency with temperature has a conversion factor of 1.6 kHz//spl deg/C. The output is also independent of supply voltage in the range 1-1.5 V. Measured results and targeted applications for the proposed circuit are reported.     

A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal

This paper describes the design strategy and implementation of a low-voltage pseudodifferential double-sampled timing-skew-insensitive sample-and-hold (S/H) circuit with low hold pedestal based on the Miller-effect scheme. The S/H circuit employs bootstrapped switches in order to facilitate low voltage operation. The design considerations for each building block are described in detail. The S/H circuit has been designed using a 0.35-/spl mu/m 2P4M CMOS technology and experimental results are presented. The 1.5-V S/H circuit operates up to a sampling frequency of 50 MHz with less than -54.6 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8 V/sub pp/. In these conditions, a differential hold pedestal of less than 0.8 mV, 1.6 ns acquisition time at 0.8-V step input, and 0.8 V/sub pp/ full-scale differential input range are achieved.     

IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator for digital receiver applications

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allow direct sampling of an IF signal, reducing analog hardware, and make it easier to realize completely software-programmable receivers. This paper presents the circuit design of and test results from a continuous-time tunable IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator implemented in InP HBT IC technology for use in a multimode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs-GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The fourth-order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wide-band and narrow-band operation. The IF is tunable from 140 to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5-V power supplies, the fabricated fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal-to-(noise + distortion) ratio (SNDR) of 78 dB at 1 MHz BW and 50 dB at 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB at 1 MHz BW and 47.7 dB at 60 MHz BW.     

A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-railoutput swing

A low-voltage switched capacitor (SC) filter operated from a single 1 V supply and realized in a standard 0.5-μm CMOS technology is presented. Proper operation is obtained using the switched-opamp technique without any clock voltage multiplier or low-threshold devices. This makes the circuit compatible with future deep submicrometer technology. As opposed to previous switched-opamp implementations, the filter uses a fully differential topology. This allows operation with a rail-rail output swing and reduction of the number of opamps required to build high order infinite impulse response (IIR) filters. On the other hand, a low-voltage common-mode feedback (CMFB) circuit is required. In addition, the circuit uses an opamp which is only partially turned off during the off phase. This enables an increase in the maximum sampling frequency. The filter implements a bandpass response (f_s/f _o=4, Q=7) and it has been characterized with a 1.8 MHz sampling frequency. Its power consumption is about 160 μW. The filter is still fully functional down to 0.9 V supply voltage     

A Low-Voltage Fully Differential Constant-Gm Rail-to-Rail CMOS Operational Amplifier

A low-voltage fully differential CMOS operational amplifier withconstant-g_mand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel circuit to ensure constanttransconductance has been implemented [1]. The input stage is a rail-to-railstructure formed by two symmetrical OTAs in parallel (the input transistorsare operating in weak inversion). The class-AB output stages have also afull voltage swing. A rail-to-rail input common mode feedback structureallows the output voltage control. Measurements in a 0.7 µ standardCMOS process with threshold voltages of about 0.7 V have been done. Theminimum experimental supply voltage is about 1.1 V. The circuit provides a60 dB low frequency voltage gain and about 1.5 MHz unity gain frequency fora total power consumption of about 0.72 mW at a 1.5 V supply voltage.     

80 MHz bandpass delta-sigma modulator using switched-capacitorresonator structure

A fully differential 80 MHz fourth-order bandpass ΔΣ modulator, meant for a 100 MHz GSM/WCDMA multimode IF receiver, is presented. The modulator is based on a double-delay single opamp SC-resonator structure which is well suited for low supply voltages. Furthermore, the centre frequency of the topology is insensitive to different component variances. The measured peak SNR is 78 dB and 43.3 dB for 270 kHz (GSM) and 3.84 MHz (WCDMA) bandwidths, respectively     

1.5 V 1 K-CMOS-RAM with only 8 pins

A 256-bit/spl times/4-bit static RAM working on a supply voltage down to 1.2 V is described. A serial interface for the address and the data with a 4-bit bus reduces the pincount of the RAM to only 8. Special design techniques to reach the design goal-very low power at a reasonable circuit speed-are discussed in detail. The device is fabricated in a low power silicon gate CMOS process. An operating power of 500 /spl mu/W/MHz and a standby power of less than 1 /spl mu/W at 1.5 V supply voltage was achieved. With this serial interface a cycle time of 1 /spl mu/s at 1.5 V was measured.     

Real-time programmable low power SC bandpass filter

A real-time programmable switched capacitor (SC) second-order bandpass filter is presented. It is based on the voltage inverter switch (VIS) principle using inverse recharging devices. These devices are realized with dynamic amplifiers in order to achieve low power dissipation. The filter contains only grounded or virtually grounded network capacitances and, therefore, it is insensitive to the parasitic capacitances between the bottom plate of the implemented MOS capacitors and the substrate. The circuit offers digital programming capability (two Q factors and three center frequencies) and low power dissipation (185 /spl mu/W at a sampling frequency of 8 kHz and with a power supply voltage of 10 V). The filter has been integrated in CMOS metal-gate technology.     

A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator

This paper describes a 0.35-/spl mu/m CMOS fourth-order bandpass analog-digital sigma-delta (/spl Sigma//spl Delta/) modulator for wide-band base stations receivers. The modulator, based on a time-interleaved four-path architecture, achieves an equivalent sampling frequency of 280 MHz, although the building blocks operate at only 70 MHz. In measurements, the prototype chip achieves a dynamic range of 72 dB (12 bits of resolution) with a signal bandwidth of 4.375 MHz centered around an intermediate frequency of 70 MHz. The measured spurious-free dynamic range is 69 dB. The /spl Sigma//spl Delta/ modulator dissipates 480 mW from a 3.3-V supply, including voltage reference buffers and output pads with high-driving capabilities, and occupies 20 mm/sup 2/ of silicon area.     

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.     

80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers

Three fully differential bandpass (BP) /spl Delta//spl Sigma/ modulators are presented. Two double-delay resonators are implemented using only one operational amplifier. The prototype circuits operate at a sampling frequency of 80 MHz. The BP /spl Delta//spl Sigma/ modulators can be used in an intermediate-frequency (IF) receiver to combine frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an IF of 60 MHz to a digital IF of 20 MHz. The measured peak signal-to-noise-plus-distortion ratios are 78 dB for 270 kHz (GSM), 75 dB for 1.25 MHz (IS-95), 69 dB for 1.762 MHz (DECT), and 48 dB for 3.84 MHz (WCDMA/CDMA2000) bandwidths. The circuits are implemented with a 0.35-/spl mu/m CMOS technology and consume 24-38 mW from a 3.0-V supply, depending on the architecture.     

A 5-GHz fully integrated full PMOS low-phase-noise LC VCO

A 5-GHz fully integrated, full PMOS, low-phase-noise and low-power differential voltage-controlled oscillator (VCO) is presented. This circuit is implemented in a 0.35-/spl mu/m four-metal BiCMOS SiGe process. At 2.7-V power supply voltage and a total power dissipation of only 13.5 mW, the proposed VCO features a worst case phase noise of -97 dBc/Hz and -117 dBc/Hz at 100 kHz and 1 MHz frequency offset, respectively. The oscillator is tuned from 5.13 to 5.68 GHz with a tuning voltage varying from 0 to 2.7 V.     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.     

A high-frequency and high-resolution fourth-order /spl Sigma//spl Delta/ A/D converter in BiCMOS technology

A high-performance cascaded sigma-delta modulator is presented. It has a new three-stage fourth-order topology and provides functionally a maximum signal to quantization noise ratio of 16 bits and 16.5-bit dynamic range with an oversampling ratio of only 32. This modulator is implemented with fully differential switch-capacitor circuits and is manufactured in a 2-/spl mu/m BiCMOS process. The converter, operated from +/-2.5 V power supply, +/-1.25 V reference voltage and oversampling clock of 48 MHz, achieves 97 dB resolution at a Nyquist conversion rate of 1.5 MHz after comb-filtering decimation. The power consumption of the converter is 180 mW.<>     

A vertically integrated tool for automated design of /spl Sigma//spl Delta/ modulators

We present a tool that starting from high-level specifications of switched-capacitor (SC) /spl Sigma//spl Delta/ modulators calculates optimum specifications for their building blocks and then optimum sizes for the block schematics. At both design levels, optimization is performed using statistical techniques to enable global design and innovative heuristics for increased computer efficiency as compared with conventional statistical optimization. The tool uses an equation-based approach at the modulator level, a simulation-based approach at the cell level, and incorporates an advanced /spl Sigma//spl Delta/ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: (1) a 16 b @ 16 kHz output rate second-order /spl Sigma//spl Delta/ modulator; and (2) a 17 b @ 40 kHz output rate fourth-order /spl Sigma//spl Delta/ modulator. Both use SC fully differential circuits and were designed using the proposed tool and manufactured in a 1.2 /spl mu/m CMOS double-metal double-poly technology.<>     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

A low-power precomputation-based fully parallel content-addressable memory

This paper presents a novel VLSI architecture for a fully parallel precomputation-based content-addressable memory (PB-CAM) with low-power, low-cost, and low-voltage features. This design is based on a precomputation approach that saves not only power consumption of the CAM system, but also reduces transistor count and operating voltage of the CAM cell. In addition, the proposed PB-CAM word structure adopts the static pseudo-nMOS circuit design to improve system performance. The whole design was fabricated with the TSMC 0.35-/spl mu/m single-poly quadruple-metal CMOS process. With a 128 words by 30 bits CAM size, the measurement results indicate that the proposed circuit works up to 100 MHz with power consumption of 33 mW at 3.3-V supply voltage and works up to 30 MHz under 1.5-V supply voltage.