低功耗三输入AND/XOR门的设计

三输入AND/XOR门是Reed-Muller(RM)逻辑电路的一种基本复合门电路单元.针对现有AND/XOR门电路由AND门和XOR/XNOR门级联而成,导致电路延时长、功耗大等问题,提出一种晶体管级的CMOS逻辑和传输逻辑混合的低功耗三输入AND/XOR门电路.首先在55nm CMOS工艺下,对所设计电路进行原理图和版图设计;然后对版图进行寄生参数提取,并在不同工艺角下与基于典型级联结构的电路进行后仿真分析和比较.实验结果表明,在典型工艺角下,所提出的电路的面积、功耗和功耗延迟积的改进最高分别达到18.79%,26.67%与31.25%.     

AXIG及其基于双逻辑的面积优化

针对逻辑函数基于单一的传统布尔逻辑(TB逻辑)进行逻辑优化的局限性,提出基于TB逻辑和Reed-Muller逻辑(RM逻辑)的双逻辑图形表示的面积优化方法.首先将逻辑函数表示成以"与"、"异或"、"非"为运算集的AXIG(AND/XOR/INV graph),得到逻辑函数的双逻辑图形表示;然后将所得到的AXIG划分成适合TB逻辑和适合RM逻辑的2部分分别进行逻辑优化;最终实现逻辑函数的面积优化.实验结果表明,该方法优于已有的逻辑综合方法.     

基于图卷积网络的重大事件趋势预测

针对基于公开新闻数据的重大事件趋势预测研究在文本特征提取上语义理解不足问题,提出基于图卷积网络的重大事件趋势预测方法.利用结构化事件信息构建以事件为中心的语义关联图;按时间片粒度分割出局部事件语义关联图,利用预训练词向量对节点文本初始化特征表示;将带有节点特征的局部事件语义关联图输入图卷积网络,聚合节点邻域信息计算图特征表示并输入到分类器,训练预测模型并输出预测结果.以朝鲜核行为趋势预测问题验证所提出方法的有效性,对测试集(2017年3月～2018年3月)预测准确率达到76.92％,全时间段预测准确率为89.58％.预测结果表明,该方法增强了对文本的语义理解,预测精度优于基于专家知识构建特征的方法.     

基于图裁减和图搜索的工作流图验证算法

工作流程中的结构冲突将导致工作流管理系统无法正常运行,因此需要在工作流图付诸实施之前要验证工作流的正确性,检测出其中的冲突。目前,无环工作流图的冲突检测在Mahanti-Sinnakkrishnan算法中已经得到了较好的解决,L.Kai和L.Qiang提出了CWRS算法用来检测有环工作流图的结构冲突,但该算法存在缺陷,会产生误判。对CWRS算法进行分析,指出了该算法的缺陷,并提出了改进方法,解决了有环工作流图AND型节点不配对时的冲突检测问题。     

逻辑函数适于双逻辑实现的探测算法

提出一种判定逻辑函数是否适于双逻辑实现的探测算法,直接从XOR逻辑的特点出发,即2个汉明距离为2 的最小项可以由 XOR 逻辑表示.通过计算函数最小项之间的汉明距离分析其所具有的逻辑模式,给出探测适用于双逻辑实现的判断条件.该算法已用 C 语言实现,并应用于 MCNC benchmark 电路的判定测试,实验结果验证了其有效性.     

校时脉冲发生电路

<正> 在用编码器等的输出脉冲进行程序控制的情况下,编码器的非同步输出脉冲必须要跟时钟脉冲同步(逻辑微分电路)。在此,介绍一种用非同步信号的上升沿和下降沿进行逻辑微分的校时脉冲发生电路。图中表示校时脉冲发生电路的构成与时间图。     

0～_-~+180°相位差的测量

<正> 同频率的两个波形之间的相位差通常是采用异或电路将输入信号转换成方波来测得,异或门输出的平均值与相位差戍比例。这个方法可测量0～180℃的相位,但不能指示相位超前或滞后的方向。图1所示的电路就是上述方案的变形,该电路可测量0～±180°的相位。产生的方波信号A和B送至D触发器,当输入1超前输入2时,触发器输出C为逻辑1;当输入1滞后输入2时,输出为逻辑0。在输出运放电路中,D触发器的输出C用来控制晶体管2N2369的导通和关断。当C为逻辑0时,运算放大器输出F为正且与异或电路输出的平均值E成正比;当C为逻辑1时,F为负,     

基于截止时间满意度的网格工作流调度算法

动态网格环境中用户截止时间保障是工作流调度问题的一个挑战.利用随机服务模型来描述网格资源的动态处理能力及其动态负载压力,提出了截止时间满意度的概念和工作流截止时间满意度的计算方法.将以DAG图形式表示的任务执行关系转换为以数值表示的任务执行优先级,并根据最大截止时间满意度优先的思想,确定执行工作流子任务的候选资源;将工作流全局截止时间划分问题描述为一个约束下的非线性规划问题并通过已有方法求解该问题,提出了一种截止时间满意度增强的工作流调度算法(DSESAW).仿真实验采用实际网格应用和系统数据来验证所提出算法的性能表现,实验结果表明新算法在网格环境的自适应性和用户截止时间保障方面优于其他两种实际网格系统中的调度算法.     

正逻辑与负逻辑

在数字电路中,输出信号与输入信号之间有一定的逻辑关系,例如非门,当输人信号为高电平时,输出为低电平;反之,当输入为低电平,输出为高电平。为了方便,在逻辑电路中用符号1和0来表示高电平和低电平两种状态,换言之即高电平是逻辑“1”,低电平是逻辑“0”。这是一种人为的规定,亦可以反过来将高电平定为逻辑“0”,低电平定为逻辑“1”。由于大多数数字电路采用的是正电源、硅管电路,用高电平作逻辑1、低电平作逻辑0比较方便,所以定为用1表示高电     

混合极性列表技术及其在MPRM电路面积优化中的应用

通过对AND/XOR展开式和函数转换的研究,提出多输出混合极性Reed-Muller(MPRM)表达式列表技术.根据Reed-Muller可编程逻辑阵列(RMPLA)的映射方法以及电路结构建立MPRM电路面积估计模型;在此基础上,结合列表技术和面积估计模型,沿非循环格雷码极性遍历路径进行MPRM电路面积最佳极性搜索,得到面积最优的MPRM电路.通过对19个MCNC和ISCAS基准电路进行测试的结果表明:与Boolean电路和固定极性Reed-Muller(FPRM)电路相比,MPRM电路面积平均减少73.5%和51.8%.     

异或门低功耗优化展开方法

异或门实际输出信号具有空间相关性，为了便于进行低功耗优化的研究，现有方法将异或门输出信号假设为随机信号，并以异或门输入信号的置1概率为依据进行低功耗优化。文中不仅从概率的角度指出现有方法的局限性，而且推导出直接用输入信号的跳变密度计算2输入端异或门输出信号跳变密度的计算公式，进而提出用输入信号跳变密度对异或门进行低功耗优化展开的新方法。实验结果表明：文中方法的功耗降幅为现有方法的3倍多；同时，文中方法优化展开后与异或门功耗的实际模拟结果相比，其理论计算值的误差比较小（平均仅为0．97％），从实验的角度证明了文中关于异或门低功耗优化展开所做的理论分析的正确性。     

Formalizing the specification and execution of workflows using the event calculus

The event calculus is a logic programming formalism for representing events and their effects especially in database applications. This paper proposes the event calculus as a logic-based methodology for the specification and execution of workflows. It is shown that the control flow graph of a workflow specification can be expressed as a set of logical formulas and the event calculus can be used to specify the role of a workflow manager through a set of rules for the execution dependencies of activities. The proposed framework for a workflow manager maintains a history of events to control the execution of activities. The events are instructions to the workflow manager to coordinate the execution of activities. Based on the already occurred events, the workflow manager triggers new events to schedule new activities in accordance with the control flow graph of the workflow. The net effect is an alternative approach for defining a workflow engine whose operational semantics is naturally integrated with the operational semantics of a deductive database. Within this framework it is possible to model sequential and concurrent activities with or without synchronization. It is also possible to model agent assignment and execution of concurrent workflow instances. The paper, thus, contributes a logical perspective to the task of developing formalization for the workflow management systems.     

XOR transform with actin quantum automata for better security against cryptanalysis

XOR is a basic cryptographic transform, used as a one way function inside of complex cryptosystems. In this paper we propose first of a kind design of the XOR transform with a universal logic designing paradigm. The system offers enhanced security to the transform by propagating randomly generated information along with the XOR output over the unsecured channel. This additional security is a inherent attribute of the actin automata and is exploited in this paper. The system can be enacted on a Partitioned one-Dimensional Quantum Cellular Automata. A simulation of the proposed system is illustrated with Simulink tool in MATLAB. Based on the work done by Adamatzky et al. we observe that the actin automata is capable of operating on quantum input bits and can generate appropriate results when required. In this paper, the actin automata is simulated with classical bits instead of quantum bits for designing the transform. We have also tried to establish the proposed system by means of low power consumption verified with NI Multisim and comparison with cryptographic complexity with traditional XOR transform. Additionally, we have analyzed the system for enhanced cryptanalytic complexity against various attacks.

     

求S盒布尔表达式的若干算法探讨

S盒是许多加密算法唯一的非线性部件,其安全性对这些算法的密码分析至关重要。S盒输出的布尔表达式（即模2域上的代数多项式）被用于衡量S盒的非线性度等用途。在已知S盒真值表情况下,对求S盒各输出布尔表达式的各种算法进行了探讨和总结。其中,折半异或法在普通PC计算机上只需要[m2m-1]次操作,其中[m]为S盒的输入位数,且不需要占用额外的内存。     

Min-max quadratic cost control of systems described by approximate models

This paper considers the design of output regulators with the use of approximate models. The measure of the approximation between process and model outputs is represented by a bound in norm of the output error signals and it requires the computation of two numbers. The design is achieved with a rain-max approach where control and error signals are the two antagonists. The min-max solution is obtained as a linear function of the model state (open-loop solution). It is shown that no dosed-loop controls can improve the open-loop min-max performance. Conditions are given so as to preserve the min-max performance by means of proportional feedback of the system's output. In this case the min-max feedback law is obtained (closed-loop solution).     

An empirical study of control logic specifications for programmable logic controllers

This paper presents an empirical study of control logic specifications used to document industrial control logic code in manufacturing applications. More than one hundred input/output related property specifications from ten different reusable function blocks were investigated. The main purpose of the study was to provide understanding of how the specifications are expressed by industrial practitioners, in order to develop new tools and methods for specifying control logic software, as well as for evaluating existing ones. In this paper, the studied specifications are used to evaluate linear temporal logic in general and the specification language ST-LTL, tailored for functions blocks, in particular. The study shows that most specifications are expressed as implications, that should always be fulfilled, between input and output conditions. Many of these implications are complex since the input and output conditions may be mixed and involve sequences, timer issues and non-boolean variables. Using ST-LTL it was possible to represent all implications of this study. The few non-implication specifications could be specified in ST-LTL as well after being altered to suit the specification language. The paper demonstrates some advantages of ST-LTL compared to standard linear temporal logic and discusses possible improvements such as support for automatic rewrite of complex specifications.     

A primary algorithm for the understanding of logic circuit diagrams

This paper describes a primary algorithm that inputs information of logic circuit diagrams by designers into a computer automatically executing a local area processing. The algorithm tracks signal lines that have thickness using a line sensor. A line sensor detects particular areas such as branches, crosses, L type junctions, logic symbol areas and so on. When the pending signal line is recognized as ending at the output-side of a logic symbol, its input-side is examined precisely and the kind (OR, AND or INVERTER), the numbers of input signal lines and so forth are recognized.     

A new backpropagation learning algorithm for layered neural networks with nondifferentiable units

We propose a digital version of the backpropagation algorithm (DBP) for three-layered neural networks with nondifferentiable binary units. This approach feeds teacher signals to both the middle and output layers, whereas with a simple perceptron, they are given only to the output layer. The additional teacher signals enable the DBP to update the coupling weights not only between the middle and output layers but also between the input and middle layers. A neural network based on DBP learning is fast and easy to implement in hardware. Simulation results for several linearly nonseparable problems such as XOR demonstrate that the DBP performs favorably when compared to the conventional approaches. Furthermore, in large-scale networks, simulation results indicate that the DBP provides high performance.     

基于业务规则的工作流管理系统模型

ECA规则通过条件与处理集中定义业务流程中活动与活动间的转换关系,并通过事件驱动机制驱动业务流程中相应业务逻辑实现,在一定程度上增加了系统代码的可维护性,但是并没有改变业务逻辑发生变化时需要修改系统代码以维护系统的现状.业务规则可准确描述业务流程中所有业务逻辑,建立与业务流程事件无关的运行机制,更加直接明确地反映业务需求,适应业务需求变化,而无需修改系统代码,基于此建立基于业务规则的工作流管理系统模型.