Efficient algorithm for FPGA board routing

A simple and fast algorithm for solving the two-terminal board level routing problem in FPGA-based logic emulation systems is presented. The method is based on the net scan selection process. Experimental results are the first implemented results for an algorithm presented previously. The comparison results show that the current approach achieves better effectiveness and uses less CPU time.     

Innovative circuit board level routing designs for BGA packages

Advances in the performance of electronic devices have resulted in high input/output counts both at the chip and the package level, which has led to the development of new packaging technologies that can accommodate these high counts. This paper presents and analyzes a novel method for the placement of ball grid array (BGA) bonding pads and routing wires on printed circuit boards to maximize signal density, which ultimately reduces the number of circuit board layers needed for routing. This method has been termed as the "balls shifted as needed" method and all the ball placement/trace routing designs shown in this paper are based on this method. We also present a performance metric defined as the number of balls routed out divided by the area of package footprint on the circuit board, and we compare various placement/routing schemes using this method.     

Architecture level optimization of 3-dimensional tree-based FPGA

We describe a methodology to design and optimize Three-dimensional (3D) Tree-based FPGA by introducing a break-point at particular tree level interconnect to optimize the speed, area, and power consumption. The ability of the design flow to decide a horizontal or vertical network break-point based on design specifications is a defining feature of our design methodology. The vertical partitioning is organized in such a way to balance the placement of logic blocks and switch blocks into multiple tiers while the horizontal partitioning optimizes the interconnect delay by segregating the logic blocks and programmable interconnect resources into multiple tiers to build a 3D stacked Tree-based FPGA. We finally evaluate the effect of Look-Up-Table (LUT) size, cluster size, speed, area and power consumption of the proposed 3D Tree-based FPGA using our home grown experimental flow and show that the horizontal partitioned 3D stacked Tree-based FPGA with LUT and cluster sizes equal to 4 has the best area-delay product to design and manufacture 3D Tree-based FPGA.     

Timing slack optimization approach using FPGA hybrid routing strategy of rip-up-retry and pathfinder

To improve the path slack of Field Programmable Gate Array （FPGA）, this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a col- location table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized （reduced） by 85.8% on average compared with the Versatile Place and Route （VPR） tim- ing-driven routing algorithm, while the run-time is only increased by 15.02% on average.     

Placement and routing tools for the Triptych FPGA

Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniques are often developed specifically for only a single FPGA architecture. In this paper we describe automatic mapping tools for Triptych, an FPGA architecture with improved logic density and performance over commercial FPGAs. These tools include a simulated-annealing placement algorithm that handles the routability issues of fine-grained FPGAs, and an architecture-adaptive routing algorithm that can easily be retargeted to other FPGAs. We also describe extensions to these algorithms for mapping asynchronous circuits to Montage, the first FPGA architecture to completely support asynchronous and synchronous interface applications     

Joint optimization of energy allocation and routing problems in wireless sensor networks

Energy allocation problems and routing problems are both important research issues in the wireless sensor network (WSN) field. The former usually aims at considering how to allocate a certain number of sensor devices in a sensing region to form a WSN so that the objective function value (e.g., the network connectivity or the network lifetime) of the constructed network is optimized. For the message routing problem in WSNs, researchers tend to consider how to find an energy conservable message transmission routing scheme for notifying the supervisor of the WSN when an event occurs. Till now, many solutions have been proposed for the above two categories of optimization problems. However, unifying the above two network optimization problems to maximize the network lifetime, to the best of our knowledge, still lacks related research. This paper considers a joint optimization problem for energy allocation and energy‐aware routing called the joint optimization of energy allocation and routing problem (JOEARP) for a hierarchical cluster‐based WSN. We propose an exact algorithm to provide the optimum solution for the JOEARP. The simulation results show that this solution performed better in prolonging the network lifetime of a WSN in a real situation, compared to other compositions of conventional energy allocation schemes with some known routing algorithms. Copyright © 2009 John Wiley & Sons, Ltd.     

Probabilistic routing protocol for a hybrid wireless underground sensor networks

A wireless underground sensor network (WUSN) is defined as a network of wireless sensor devices in which all sensor devices are deployed completely underground (network sinks or any devices specifically for relay between sensors and a sink may be aboveground). In hybrid wireless underground sensor network (HWUSN), communication between nodes is implemented from underground‐to‐air or air‐to‐underground, not underground‐to‐underground. This paper proposes a novel hybrid underground probabilistic routing protocol that provides an efficient means of communication for sensor nodes in HWUSN. In addition, signal propagation based on the shadowing model for underground medium is developed. The proposed routing protocol ensures high packet throughput, prolongs the lifetime of HWUSN and the random selection of the next hop with multi‐path forwarding contributes to built‐in security. Moreover, the proposed mechanism utilizes an optimal forwarding (OF) decision that takes into account of the link quality, and the remaining power of next hop sensor nodes. The performance of proposed routing protocol has been successfully studied and verified through the simulation and real test bed. Copyright © 2011 John Wiley & Sons, Ltd.     

A satisfiability formulation for FPGA routing with pin rearrangements

This paper presents a satisfiability formulation for FPGA segmented channel routing with pin rearrangements. In our new routing model, the pins in each module have certain degree of freedom to be rearranged. With this flexibility, the wire routability can be improved in segmented channel routing. We present an efficient SAT-based approach to solve the problem. We use one of the best SAT-solvers, zChaff, to perform our experiments. Experimental results show the promising performance of the method.     

一种多线程FPGA时序驱动布线算法

随着现场可编程门阵列(FPGA)器件尺寸不断增大,计算机辅助设计(CAD)工具运行时间成为突出的问题。布线是FPGA的CAD流程中最为耗时的一个阶段,一种能有效缩短布线时间的方法就是并行布线。本文提出一种减少FPGA时序驱动布线算法运行时间的多线程方法。该算法首先将信号按照线网的扇出数量进行排序,再将排序后的线网均匀分配到各个线程中,最后并发执行所有的线程。在布线质量没有受到显著影响的前提下,即线长增加2.58%,关键路径延时增加1.78%的情况下,相对于传统通用布局布线工具(VPR)时序驱动布线算法8线程下的加速比为2.46。     

QoS-based multicast routing optimization algorithms for Internet

Most of the multimedia applications require strict Quality-of-Service （QoS） guarantee during the communication between a single source and multiple destinations. The paper mainly presents a QoS Multicast Routing algorithms based on Genetic Algorithm （QMRGA）. Simulation results demonstrate that the algorithm is capable of discovering a set of QoS-based near optimized, non-dominated multicast routes within a few iterations, even for the networks environment with uncertain parameters.     

基于跨层设计的AODV路由优化机制

以AODV(无线自组网按需平面距离矢量路由)协议为原型,针对WMN(无线Mesh网)中传统AODV协议路由判据单一从而导致路由性能较差的缺陷,采用跨层设计方法为WMN设计了一种新的IAODV(优化的AODV)协议。在路由计算过程中通过跨层操作机制提取节点当前负载和链路投递率这两个影响链路质量的因素,结合路由跳数设计出合理的路由判决函数。理论分析和NS2仿真结果证明,这种路由优化机制提高了吞吐量,降低了网络时延,并且能够达到负载均衡的路由效果。     

Distributed probabilistic routing for sensor network lifetime optimization

A probabilistic and distributed routing approach for multi-hop sensor network lifetime optimization is presented in this paper. In particular, each sensor self-adjusts their routing probabilities locally to their forwarders based on its neighborhood knowledge, while aiming at optimizing the overall network lifetime (defined as the elapsed time before the first node runs out of energy). The theoretical feasibility and a practical routing algorithm are presented. Specifically, a sufficient distributed condition regarding the neighborhood state for distributed probabilistic routing to achieve the optimal network lifetime is presented theoretically. Based on it, a distributed adaptive probabilistic routing (DAPR) algorithm, which considered both the transmission scheduling and the routing probability evolvement is developed. We prove quantitatively that DAPR could lead the routing probabilities of the distributed sensors to converge to an optimal state which optimizes the network lifetime. Further, when network dynamics happen, such as topology changes, DAPR can adjust the routing probabilities quickly to converge to a new state for optimizing the remained network lifetime. We presented the convergence speed of DAPR. Extensive simulations verified its convergence and near-optimal properties. The results also showed its quick adaptation to both the network topology and data rate dynamics.     

SAT based solutions for detailed routing of island style FPGA architectures

Detailed routing solutions for island style FPGA architectures using Boolean satisfiability (SAT) based formulations have been proposed in this paper. Due to decreasing size of ICs and hence, the increasing complexity of the routing resource constraints, routing has been a big challenge in electronic design automation field. Our proposed techniques work on multi-pin net routing where all nets are considered for routing in their intact form whereas, most of the existing routing solutions decompose multi-pin nets into two-pin nets for detailed routing to ease the problem. However this approach, apart from increasing the number of nets in the circuits, may also introduce pin doglegging which, when not permitted by the architecture of FPGA, would require extra constraints to eliminate. Many detailed routers adopt sequential detailed routing approaches which are vulnerable to the net ordering problem which may cause a routable circuit to be erroneously classified as unroutable. Our proposed techniques avoid these pitfalls by keeping the multi-pin nets intact and solve all nets simultaneously using SAT. The SAT-based multi-pin net dogleg-free formulations presented here achieve significant improvement over existing SAT-based solutions with respect to the number of variables and clauses used, thereby achieving greater scalability and also display comparable and sometimes better routability results on benchmark circuits when compared with other detailed routing solutions. Detailed routing is also significantly affected by the architecture of the switching blocks. This paper proposes SAT-based formulation for three different switch box architectures i.e. Subset, Wilton, and Universal switches. Our experiments clearly demonstrate how routing solutions for a circuit can differ significantly for different types of switch boxes.     

FPGA routing and routability estimation via Boolean satisfiability

Guaranteeing or even estimating the routability of a portion of a placed field programmable gate array (FPGA) remains difficult or impossible in most practical applications. In this paper, we develop a novel formulation of both routing and routability estimation that relies on a rendering of the routing constraints as a single large Boolean equation. Any satisfying assignment to this equation specifies a complete detailed routing. By representing the equation as a binary decision diagram (BDD), we represent all possible routes for all nets simultaneously. Routability estimation is transformed to Boolean satisfiability, which is trivial for BDD's. We use the technique in the context of a perfect routability estimator for a global router. Experimental results from a standard FPGA benchmark suite suggest the technique is feasible for realistic circuits, but refinements are needed for very large designs     

An overview of routing optimization for internet traffic engineering

Traffic engineering is an important mechanism for Internet network providers seeking to optimize network performance and traffic delivery. Routing optimization plays a key role in traffic engineering, finding efficient routes so as to achieve the desired network performance. In this survey we review Internet traffic engineering from the perspective of routing optimization. A taxonomy of routing algorithms in the literature is provided, dating from the advent of the TE concept in the late 1990s. We classify the algorithms into multiple dimensions: unicast/multicast, intra-/inter- domain, IP-/MPLS-based and offline/online TE schemes. In addition, we investigate some important traffic engineering issues, including robustness, TE interactions, and interoperability with overlay selfish routing. In addition to a review of existing solutions, we also point out some challenges in TE operation and important issues that are worthy of investigation in future research activities.     

A novel optimization algorithm for video placement and routing

In this paper, we propose a novel optimization algorithm for the solution of the video placement and routing problem based on Lagrangean relaxation,and decomposition. The main contribution can be stated as the use of integer programming models to obtain feasible solutions to the problem within the algorithm. Computational experimentation reveals that the use of such integer models help greatly in obtaining good quality solutions in a small amount of solution time.     

求解动态最优路径的混合优化算法

对动态网络环境下动态需求的最优路径搜索问题进行了研究,首次提出了一个能同时利用演化算法的全局优化能力和蚁群算法的局部探索能力的混合智能优化算法Evo-Ant,并将其应用于DVRP.为了验证算法的有效性,给出了DVRP的混合整数规划模型,建立了DVRP的动态性能测试类,并进行了大量的仿真实验和比较.结果表明,Evo-Ant算法能够根据实时接收到的信息对当前规划路径进行及时调整,具有明显改善的性能优势.     

互域移动性的一种新的安全路由最优化协议

下一代移动网络提供一种方法支持移动用户在异构的接入网络之间漫游。我们需要在不同的移动管理域之间建立信任关系。在这篇文章中,提出了基于公钥密钥交换协议的互域网移动性的新的安全最优化路由协议。移动节点之间的信息交换将比通常的方法少。     

一种SRAM型FPGA互连资源的位流码配置方法

针对静态随机存取存储器(SRAM)型现场可编程门阵列(FPGA)位流码配置问题,提出一种自动配置互连资源的方法。该方法从描述FPGA结构的行为级Verilog文件中,采用基于端口映射的记忆FPGA配置模型搜索(MCMS)算法自动提取互连资源的配置位模型,然后结合布线结果生成布线路径上互连资源的位流码。实验结果表明,对于包含30 Mb配置位的3 000万门SRAM型同质FPGA,采用人工方法提取互连资源配置位模型需要6天时间,而采用端口映射MCMS算法仅需要29分钟,效率提高了298倍;对于同等规模的异质FPGA,采用人工方法需要7天时间,而采用端口映射MCMS算法仅需26分钟,效率提高了394倍。该算法作为一种通用的互连资源配置位模型提取方法,可以应用于不同的FPGA芯片。在缩短位流码配置时间的同时,提高位流码配置的准确性。