总剂量辐射下的NMOS/SOI器件背栅阈值电压漂移模型

SOI(绝缘体上硅)器件在总剂量辐照下的主要性能退化是由于SOI器件的背栅阈值电压漂移引起的背沟道漏电。本文首先采用二维有限元方法,对辐射在SOI器件的埋氧层中的感生氧化物电荷进行模拟,然后分析此氧化物电荷对器件的外部电学特性的影响,建立了器件在最劣偏置下辐射引起的背栅MOSFET的阈值电压漂移模型,提取背栅MOSFET受辐射影响参数,以用于在SOI电路设计中准确的评估辐射对SOI电路的影响。模拟数据和试验数据具有很好的一致性。     

纳米 MOSFET/SOI器件新结构

重点介绍器件进入纳米尺度后出现的MOSFET／SOI器件的新结构，如超薄SOI器件、双栅MOSFET、FinFET和应变沟道等SOI器件，并对它们的性能进行了分析。     

Pseudo-MOS方法表征SIMOX SOI材料总剂量辐照效应

为了缩短SOI材料的改性研究周期,利用pseudo-MOS方法研究了SIMOX SOI材料的总剂量辐照效应.试验采用硅注入绝缘埋层后退火得到改性的SIMOX SOI材料,通过对比改性前后样品在辐照前后的pseudo-MOSFET ID-VG特性曲线,分析改性工艺的影响.研究结果表明,合适的改性工艺能有效提高材料抗总剂量辐照效应的能力,pseudo-MOS方法在大大缩短SOI材料改性周期的基础上,能准确、快捷地对材料的总剂量辐照效应进行表征.     

SOI的自加热效应与SOI新结构的研究

阐述了自加热效应产生的原因以及它对SOI电路的影响，并介绍了为克服自加热效应和满足某些特殊器件和电路的要求，国内外正在竞相探索研究的新型SOI结构，如SOIM，Silicon onAlN,GPSOI,SiCOI,GeSiOI,SON,SSOI等，结论SOI新结构制备工作，报道了SOI的自加热效应及其新结构的研究进展。     

SOI在高压器件中的应用

综述了绝缘层上的硅(SOI)材料在高压器件中的应用,分析了SOI高压器件的不同结构,并对现在最常用的RESURF LDMOS高压器件结构,以及不同器件参数对击穿电压的影响进行了分析和讨论.     

SOI光电子集成

SOI（Silicon-on-Insulator)光电子集成已成为十分引人注目的研究课题，其工艺与CMOS工艺完全兼容，可以实现低成本的SOI基整片集成光电子回路。本文综述了近几年来SOI集成光电子器件的发展以及一些最新的研究进展，着重分析几种最新型光无源器件的工作原理和结构，包括SOI光波导、SOI光波导耦合器、SOI光波导开关、相位阵列波导光栅（PAWG）、基于SOI的光探测器等，并介绍了中国科学院半导体所集成光电子国家重点实验室的研究进展。     

高性能图形化SOI功率器件的研制

利用掩膜注氧隔离技术（Masked SIMOX）制备图形化SOI衬底,采用与常规1μmSOI CMOS工艺兼容的工艺流程,制备了图形化SOI LDMOS功率器件。器件的输出特性曲线中未呈现翘曲效应、开态击穿电压高于6V、关态击穿电压达到13V、泄漏电流的量级为10^-8A;截止频率为8GHz;当漏工作电压3．6V,频率为1GHz时,小信号电压增益为6dB。直流和射频电学性能表明,图形化SOI LDMOS结构作为射频功率器件具有较好的开发前景。     

SOI和应变Si的将来

利用SOI衬底生长部分／完全耗尽结构的晶体管或用应变沟道提高器件性能可制备出高性能CMOS逻辑器件；这两种方法均可用于CMOS结构，也可单独用于提高器件性能。将应变用于器件沟道，可将沟道迁移率提高50％，从而提高了器件电流。SOI晶体管的好     

Notching效应在MEMS单步干法制造工艺中的应用

研究了一种基于深反应离子刻蚀（DRIE）中notching效应的MEMS单步干法制造工艺.首先,基于DRIE刻蚀SOI硅片时notching现象产生的机理,设计了多种不同线宽的槽结构,验证notching效应的发生条件.实验结果表明,对于所采用的具有30μm器件层的SOI硅片,发生notching现象的临界槽宽为12μm,而notching释放的极限结构宽度同样为12μm.其次,为实现大面积结构的notching释放,研究了正方形、矩形、三角形及六边形等4种典型释放孔结构的干法释放效果.实验结果表明,六边形释放孔不但能够快速有效地释放结构,同时还能降低notch-ing效应的磨损,有利于惯性MEMS器件的加工.最后,设计了一种Z轴微机械陀螺结构以验证提出的设计及工艺.加工及测试结果表明,所提出的单步干法制造工艺完全满足微机械陀螺设计加工要求,工艺简单、成品率高,所测试的陀螺在常压下即可达到122的品质因数.     

单粒子效应的激光模拟方法研究进展

单粒子效应是一种会引起器件状态改变的辐射效应现象,会对器件性能、状态造成重大影响,甚至可能造成器件无法正常工作.本文介绍了目前各种单粒子效应的研究方法,重点综述了脉冲激光模拟研究的进展,汇总了近些年来国内外的代表性研究机构以及相应的测试装置参数,同时对脉冲激光诱导产生单粒子效应的机理、研究测试方法和代表性前沿器件研究的成果进行了概括,最后对脉冲激光模拟单粒子效应的方法、器件的研究方向等进行展望.     

Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile

The effects of a nonuniform source/drain (S/D) doping profile on the FinFET characteristics are investigated using three-dimensional device simulation. With a fixed S/D doping profile, larger silicon-on-insulator (SOI) thickness can suppress short-channel effects due to the coexistence of longer channel regions. There can be some design margin in the channel thickness due to this reduced short-channel effect. Drain saturation current in FinFET is proportional to the effective device width and SOI thickness. To determine the appropriate SOI thickness of FinFET, alternating current (AC) characteristics are investigated. Device capacitance increases with SOI thickness, but this is not for the gate delay, as the drive current also increases and compensates for the increase of capacitance. When driving a constant capacitance load such as interconnect, devices with larger drain current or thicker SOI are more favorable for the fixed S/D doping condition.     

Capacitorless single transistor dynamic random-access memory devices fabricated on silicon-germanium-on-insulator substrates

Capacitorless single transistor dynamic random-access memory (1T-DRAM) cells on silicon-germanium-on-insulator (SGOI) substrates with various Ge mole fractions in the relaxed-SiGe layers were investigated. SGOI substrates with strained-Si channels showed higher on-currents and carrier mobility than a silicon-on-insulator (SOI) substrate with unstrained-Si channels. SGOI 1T-DRAM devices had larger memory windows than a similar device with SOI; memory window increased with increasing Ge mole fraction in the relaxed-SiGe layer. The SGOI 1T-DRAMs showed degraded retention times. High-temperature annealing reduced the effects of crystalline defects and thus improved the electrical properties of the SGOI substrates, leading to higher carrier mobility, larger memory window, and longer data retention.     

Electrical characteristics of nanoscale NAND silicon-oxide-nitride-oxide-silicon flash memory devices fabricated on SOI substrates

NAND silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with double gates fabricated on silicon-on-insulator (SOI) substrates were proposed. The current-voltage characteristics related to the programming operation of the designed nanoscale NAND SONOS flash memory devices on a SOI substrate and on the conventional bulk-Si substrate were simulated and compared in order to investigate device characteristics of the scaled-down memory devices. The simulation results showed that the short channel effect and the subthreshod leakage current for the memory device with a large spacer length were lower than that of the memory device with a small spacer length due to increase of the effective channel length. The device performance of the memory device utilizing the SOI substrate exhibited a smaller subthreshold swing and a larger drain current level in comparison with those on the bulk-Si substrate. These improved electrical characteristices for the SOI devices could be explained by comparing the electric field distribution in a channel region for both devices.     

采用半背沟注入提高PDSOI nMOSFETs的热载流子可靠性

提出了一个提高PDSOI nMOSFETs可靠性的方法,并且研究了这种器件的热载流子可靠性.这种方法是在制造器件中,进行背沟道注入时只注入背沟道一半的区域.应力试验结果表明这种新的器件和常规器件相比,展示了较低的热载流子退变.2D器件模拟表明在漏端降低的峰值电场有助于这种器件提高的热载流子可靠性.     

基于BSIM3V3的部分耗尽SOI MOSFET解析模型

提出了部分耗尽SOI MOSFET物理模型,SOI MOSFET可以看作体硅MOSFET和双极晶体管的结合,模型通过详细地分析SOI器件在各工作区域的工作机理得出,并提取出了相应的模型参数.用本模型得出的模拟数据与器件模拟数据进行了对比,取得了很好的一致性.     

Transfer of physically-based models from process to device simulations: Application to advanced SOI MOSFETs

Dopant implantation, followed by spike annealing is one of the main focus areas in the simulation of silicon processing due to its ability to form highly-activated ultra-shallow junctions. Coupled with the growing interest in the use of silicon-on-insulator (SOI) wafers, modelling and simulation of the influence of SOI structure on damage evolution and ultra-shallow junction formation on one hand, and on electrical MOSFET device characteristics on the other hand, are required.In this work, physically-based models of dopant implantation and diffusion, including amorphization, defect interactions and evolution, as well as dopant-defect interactions in both bulk silicon and SOI are integrated within a unique simulation tool to model the different physical mechanisms involved in the process of ultra-shallow junction formation.The application to 65 nm SOI MOSFET devices demonstrated the strong impact of the process simulation models on the simulated electrical device characteristics, in particular for both defect evolution and defect dopant interaction with the additional silicon/buried oxide (Si/BOX) interface. Simulation results of the threshold voltage (V_th) and the variation of the on- and off-state currents of the explored structures are in good agreement with experimental data and can provide important insight for optimizing the process in both bulk silicon and SOI technologies.     

基于SCR的SOI ESD保护器件研究

本文具体分析了体硅SCR(晶闸管)和SOI SCR的抗静电特性,利用软件Sentaurus对埋氧层3μm,顶层硅1.5μm的SOI衬底上的SCR进行了工艺和性能仿真,仿真结果达到了4.5kV的抗静电能力,符合目前人体模型的标准2KV.研究发现,注入剂量(9*13 -8*14cm-2)增加会引起触发电压减小,维持电压升高...     

Networks of quantum nanorings: programmable spintronic devices

An array of quantum rings with local (ring by ring) modulation of the spin orbit interaction (SOI) can lead to novel effects in spin state transformation of electrons. It is shown that already small (3 x 3, 5 x 5) networks are remarkably versatile from this point of view: Working in a given network geometry, the input current can be directed to any of the output ports, simply by changing the SOI strengths by external gate voltages. Additionally, the same network with different SOI strengths can be completely analogous to the Stern-Gerlach device, exhibiting spatial-spin entanglement.     

An approach for quantum mechanical modeling and simulation for MOS devices, covering the whole operation region

A quantum mechanical (QM) approach for modeling and simulation of MOS devices, covering the whole operation region, was proposed. This formulation is applicable continuously from the subthreshold to the saturation regions, since it exactly treats the QM effects on the in-depth distribution of the gate induced carriers in the channel by solving one dimensional Poisson equation and Schrödinger equation self-consistently and it treats the lateral drift–diffusion transport using quasi-Fermi potential. A QM simulator was implemented using this QM approach. This QM simulator was verified by classical three-dimensional device simulator, CADDETH, in the whole range of operation of bulk MOSFET with low dopant density where QM effect is negligible. The QM simulation elucidated that the threshold voltage shift in thin SOI MOSFETs in saturation region as well as in linear region results from energy shift of the lowest conduction electron level and effective increase of gate oxide thickness.